jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
target/riscv: add vector configure instruction
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
authored by
LIU Zhiwei
and committed by
Alistair Francis
2b7168fc
8e3a1f18
+210
-12
+1
-1
target/riscv/Makefile.objs
+1
-1
target/riscv/Makefile.objs
+54
-9
target/riscv/cpu.h
+54
-9
target/riscv/cpu.h
···
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#define RISCV_CPU_H
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#include "hw/core/cpu.h"
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#include "hw/registerfields.h"
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat-types.h"
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···
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#include "pmp.h"
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#define RV_VLEN_MAX 512
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FIELD(VTYPE, VLMUL, 0, 2)
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FIELD(VTYPE, VSEW, 2, 3)
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FIELD(VTYPE, VEDIV, 5, 2)
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FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
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FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 2, 1)
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struct CPURISCVState {
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target_ulong gpr[32];
···
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#define TB_FLAGS_MMU_MASK 3
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#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
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typedef CPURISCVState CPUArchState;
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typedef RISCVCPU ArchCPU;
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#include "exec/cpu-all.h"
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FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
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FIELD(TB_FLAGS, LMUL, 3, 2)
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FIELD(TB_FLAGS, SEW, 5, 3)
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FIELD(TB_FLAGS, VILL, 8, 1)
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+
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/*
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* A simplification for VLMAX
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* = (1 << LMUL) * VLEN / (8 * (1 << SEW))
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* = (VLEN << LMUL) / (8 << SEW)
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* = (VLEN << LMUL) >> (SEW + 3)
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* = VLEN >> (SEW + 3 - LMUL)
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*/
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static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
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{
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uint8_t sew, lmul;
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sew = FIELD_EX64(vtype, VTYPE, VSEW);
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lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
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return cpu->cfg.vlen >> (sew + 3 - lmul);
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}
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static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *flags)
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target_ulong *cs_base, uint32_t *pflags)
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{
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uint32_t flags = 0;
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*pc = env->pc;
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*cs_base = 0;
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if (riscv_has_ext(env, RVV)) {
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uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
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bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
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flags = FIELD_DP32(flags, TB_FLAGS, VILL,
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FIELD_EX64(env->vtype, VTYPE, VILL));
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flags = FIELD_DP32(flags, TB_FLAGS, SEW,
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FIELD_EX64(env->vtype, VTYPE, VSEW));
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flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
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FIELD_EX64(env->vtype, VTYPE, VLMUL));
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flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
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} else {
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
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}
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#ifdef CONFIG_USER_ONLY
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*flags = TB_FLAGS_MSTATUS_FS;
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flags |= TB_FLAGS_MSTATUS_FS;
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#else
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*flags = cpu_mmu_index(env, 0);
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flags |= cpu_mmu_index(env, 0);
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if (riscv_cpu_fp_enabled(env)) {
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*flags |= env->mstatus & MSTATUS_FS;
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flags |= env->mstatus & MSTATUS_FS;
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}
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#endif
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*pflags = flags;
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}
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int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
···
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void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
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typedef CPURISCVState CPUArchState;
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typedef RISCVCPU ArchCPU;
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#include "exec/cpu-all.h"
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#endif /* RISCV_CPU_H */
+3
target/riscv/helper.h
+3
target/riscv/helper.h
+5
target/riscv/insn32.decode
+5
target/riscv/insn32.decode
···
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@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
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@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
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@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
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@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
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@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
···
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# *** RV32H Base Instruction Set ***
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hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
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hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
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# *** RV32V Extension ***
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
+79
target/riscv/insn_trans/trans_rvv.inc.c
+79
target/riscv/insn_trans/trans_rvv.inc.c
···
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/*
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* RISC-V translation routines for the RVV Standard Extension.
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*
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* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
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{
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TCGv s1, s2, dst;
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if (!has_ext(ctx, RVV)) {
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return false;
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}
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s2 = tcg_temp_new();
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dst = tcg_temp_new();
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/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
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if (a->rs1 == 0) {
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/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
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s1 = tcg_const_tl(RV_VLEN_MAX);
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} else {
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s1 = tcg_temp_new();
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gen_get_gpr(s1, a->rs1);
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}
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gen_get_gpr(s2, a->rs2);
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gen_helper_vsetvl(dst, cpu_env, s1, s2);
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gen_set_gpr(a->rd, dst);
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
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lookup_and_goto_ptr(ctx);
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ctx->base.is_jmp = DISAS_NORETURN;
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tcg_temp_free(s1);
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tcg_temp_free(s2);
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tcg_temp_free(dst);
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return true;
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}
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static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
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{
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TCGv s1, s2, dst;
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if (!has_ext(ctx, RVV)) {
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return false;
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}
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s2 = tcg_const_tl(a->zimm);
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dst = tcg_temp_new();
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/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
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if (a->rs1 == 0) {
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/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
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s1 = tcg_const_tl(RV_VLEN_MAX);
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} else {
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s1 = tcg_temp_new();
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gen_get_gpr(s1, a->rs1);
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}
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gen_helper_vsetvl(dst, cpu_env, s1, s2);
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gen_set_gpr(a->rd, dst);
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gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
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ctx->base.is_jmp = DISAS_NORETURN;
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tcg_temp_free(s1);
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tcg_temp_free(s2);
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tcg_temp_free(dst);
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return true;
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}
+15
-2
target/riscv/translate.c
+15
-2
target/riscv/translate.c
···
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to reset this known value. */
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int frm;
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bool ext_ifencei;
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/* vector extension */
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bool vill;
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uint8_t lmul;
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uint8_t sew;
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uint16_t vlen;
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bool vl_eq_vlmax;
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} DisasContext;
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#ifdef TARGET_RISCV64
···
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#include "insn_trans/trans_rvf.inc.c"
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#include "insn_trans/trans_rvd.inc.c"
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#include "insn_trans/trans_rvh.inc.c"
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#include "insn_trans/trans_rvv.inc.c"
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#include "insn_trans/trans_privileged.inc.c"
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/* Include the auto-generated decoder for 16 bit insn */
···
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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CPURISCVState *env = cs->env_ptr;
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RISCVCPU *cpu = RISCV_CPU(cs);
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uint32_t tb_flags = ctx->base.tb->flags;
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ctx->pc_succ_insn = ctx->base.pc_first;
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ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
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ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
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ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
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ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
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ctx->priv_ver = env->priv_ver;
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#if !defined(CONFIG_USER_ONLY)
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if (riscv_has_ext(env, RVH)) {
···
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ctx->misa = env->misa;
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ctx->frm = -1; /* unknown rounding mode */
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ctx->ext_ifencei = cpu->cfg.ext_ifencei;
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ctx->vlen = cpu->cfg.vlen;
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ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
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ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
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ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
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ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
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}
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static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
+53
target/riscv/vector_helper.c
+53
target/riscv/vector_helper.c
···
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/*
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* RISC-V Vector Extension Helpers for QEMU.
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*
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* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
8
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
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*
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* You should have received a copy of the GNU General Public License along with
16
+
* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include <math.h>
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target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
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target_ulong s2)
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{
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int vlmax, vl;
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RISCVCPU *cpu = env_archcpu(env);
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uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
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uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
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bool vill = FIELD_EX64(s2, VTYPE, VILL);
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target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
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if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
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/* only set vill bit. */
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env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
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env->vl = 0;
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env->vstart = 0;
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return 0;
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}
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vlmax = vext_get_vlmax(cpu, s2);
44
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if (s1 <= vlmax) {
45
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vl = s1;
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} else {
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vl = vlmax;
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}
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env->vl = vl;
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env->vtype = s2;
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env->vstart = 0;
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return vl;
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}