Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging

+1 -1

target/xtensa/cpu.c

··· 78 78 env->sregs[VECBASE] = env->config->vecbase; 79 79 env->sregs[IBREAKENABLE] = 0; 80 80 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask; 81 - env->sregs[CACHEATTR] = 0x22222222; 82 81 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 83 82 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 84 83 env->sregs[CONFIGID0] = env->config->configid[0]; 85 84 env->sregs[CONFIGID1] = env->config->configid[1]; 85 + env->exclusive_addr = -1; 86 86 87 87 #ifndef CONFIG_USER_ONLY 88 88 reset_mmu(env);

+35 -23

target/xtensa/cpu.h

··· 99 99 /* Memory protection and translation */ 100 100 XTENSA_OPTION_REGION_PROTECTION, 101 101 XTENSA_OPTION_REGION_TRANSLATION, 102 + XTENSA_OPTION_MPU, 102 103 XTENSA_OPTION_MMU, 103 104 XTENSA_OPTION_CACHEATTR, 104 105 ··· 137 138 PTEVADDR = 83, 138 139 MMID = 89, 139 140 RASID = 90, 141 + MPUENB = 90, 140 142 ITLBCFG = 91, 141 143 DTLBCFG = 92, 144 + MPUCFG = 92, 145 + ERACCESS = 95, 142 146 IBREAKENABLE = 96, 143 147 MEMCTL = 97, 144 148 CACHEATTR = 98, 149 + CACHEADRDIS = 98, 145 150 ATOMCTL = 99, 146 151 DDR = 104, 152 + MEPC = 106, 153 + MEPS = 107, 154 + MESAVE = 108, 155 + MESR = 109, 156 + MECR = 110, 157 + MEVADDR = 111, 147 158 IBREAKA = 128, 148 159 DBREAKA = 144, 149 160 DBREAKC = 160, ··· 228 239 #define MAX_TLB_WAY_SIZE 8 229 240 #define MAX_NDBREAK 2 230 241 #define MAX_NMEMORY 4 242 + #define MAX_MPU_FOREGROUND_SEGMENTS 32 231 243 232 244 #define REGION_PAGE_MASK 0xe0000000 233 245 ··· 268 280 LEVEL1_INTERRUPT_CAUSE, 269 281 ALLOCA_CAUSE, 270 282 INTEGER_DIVIDE_BY_ZERO_CAUSE, 271 - PRIVILEGED_CAUSE = 8, 283 + PC_VALUE_ERROR_CAUSE, 284 + PRIVILEGED_CAUSE, 272 285 LOAD_STORE_ALIGNMENT_CAUSE, 273 - 274 - INSTR_PIF_DATA_ERROR_CAUSE = 12, 286 + EXTERNAL_REG_PRIVILEGE_CAUSE, 287 + EXCLUSIVE_ERROR_CAUSE, 288 + INSTR_PIF_DATA_ERROR_CAUSE, 275 289 LOAD_STORE_PIF_DATA_ERROR_CAUSE, 276 290 INSTR_PIF_ADDR_ERROR_CAUSE, 277 291 LOAD_STORE_PIF_ADDR_ERROR_CAUSE, 278 - 279 292 INST_TLB_MISS_CAUSE, 280 293 INST_TLB_MULTI_HIT_CAUSE, 281 294 INST_FETCH_PRIVILEGE_CAUSE, ··· 298 311 INTTYPE_DEBUG, 299 312 INTTYPE_WRITE_ERR, 300 313 INTTYPE_PROFILING, 314 + INTTYPE_IDMA_DONE, 315 + INTTYPE_IDMA_ERR, 316 + INTTYPE_GS_ERR, 301 317 INTTYPE_MAX 302 318 } interrupt_type; 303 319 ··· 317 333 bool varway56; 318 334 unsigned nrefillentries; 319 335 } xtensa_tlb; 336 + 337 + typedef struct xtensa_mpu_entry { 338 + uint32_t vaddr; 339 + uint32_t attr; 340 + } xtensa_mpu_entry; 320 341 321 342 typedef struct XtensaGdbReg { 322 343 int targno; ··· 446 467 447 468 unsigned icache_ways; 448 469 unsigned dcache_ways; 470 + unsigned dcache_line_bytes; 449 471 uint32_t memctl_mask; 450 472 451 473 XtensaMemory instrom; ··· 468 490 469 491 xtensa_tlb itlb; 470 492 xtensa_tlb dtlb; 493 + 494 + uint32_t mpu_align; 495 + unsigned n_mpu_fg_segments; 496 + unsigned n_mpu_bg_segments; 497 + const xtensa_mpu_entry *mpu_bg; 471 498 }; 472 499 473 500 typedef struct XtensaConfigList { ··· 500 527 } fregs[16]; 501 528 float_status fp_status; 502 529 uint32_t windowbase_next; 530 + uint32_t exclusive_addr; 531 + uint32_t exclusive_val; 503 532 504 533 #ifndef CONFIG_USER_ONLY 505 534 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; 506 535 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; 536 + xtensa_mpu_entry mpu_fg[MAX_MPU_FOREGROUND_SEGMENTS]; 507 537 unsigned autorefill_idx; 508 538 bool runstall; 509 539 AddressSpace *address_space_er; ··· 590 620 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \ 591 621 XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) 592 622 623 + void xtensa_collect_sr_names(const XtensaConfig *config); 593 624 void xtensa_translate_init(void); 594 625 void **xtensa_get_regfile_by_name(const char *name); 595 626 void xtensa_breakpoint_handler(CPUState *cs); ··· 658 689 } 659 690 660 691 #ifndef CONFIG_USER_ONLY 661 - uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 662 - bool dtlb, uint32_t way); 663 - void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 664 - uint32_t *vpn, uint32_t wi, uint32_t *ei); 665 - int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 666 - uint32_t *pwi, uint32_t *pei, uint8_t *pring); 667 - void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 668 - xtensa_tlb_entry *entry, bool dtlb, 669 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 670 - void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 671 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); 672 692 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, 673 693 uint32_t vaddr, int is_write, int mmu_idx, 674 694 uint32_t *paddr, uint32_t *page_size, unsigned *access); ··· 678 698 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) 679 699 { 680 700 return env->system_er; 681 - } 682 - 683 - static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, 684 - bool dtlb, unsigned wi, unsigned ei) 685 - { 686 - return dtlb ? 687 - env->dtlb[wi] + ei : 688 - env->itlb[wi] + ei; 689 701 } 690 702 #endif 691 703

+1

target/xtensa/helper.c

··· 141 141 } 142 142 #endif 143 143 } 144 + xtensa_collect_sr_names(config); 144 145 } 145 146 146 147 static void xtensa_finalize_config(XtensaConfig *config)

+6

target/xtensa/helper.h

··· 24 24 DEF_HELPER_2(intset, void, env, i32) 25 25 DEF_HELPER_2(intclear, void, env, i32) 26 26 DEF_HELPER_3(check_atomctl, void, env, i32, i32) 27 + DEF_HELPER_4(check_exclusive, void, env, i32, i32, i32) 27 28 DEF_HELPER_2(wsr_memctl, void, env, i32) 28 29 29 30 DEF_HELPER_2(itlb_hit_test, void, env, i32) ··· 33 34 DEF_HELPER_3(itlb, void, env, i32, i32) 34 35 DEF_HELPER_3(ptlb, i32, env, i32, i32) 35 36 DEF_HELPER_4(wtlb, void, env, i32, i32, i32) 37 + DEF_HELPER_2(wsr_mpuenb, void, env, i32) 38 + DEF_HELPER_3(wptlb, void, env, i32, i32) 39 + DEF_HELPER_FLAGS_2(rptlb0, TCG_CALL_NO_RWG_SE, i32, env, i32) 40 + DEF_HELPER_FLAGS_2(rptlb1, TCG_CALL_NO_RWG_SE, i32, env, i32) 41 + DEF_HELPER_2(pptlb, i32, env, i32) 36 42 37 43 DEF_HELPER_2(wsr_ibreakenable, void, env, i32) 38 44 DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32)

+456 -76

target/xtensa/mmu_helper.c

··· 35 35 #include "exec/exec-all.h" 36 36 #include "exec/cpu_ldst.h" 37 37 38 + #define XTENSA_MPU_SEGMENT_MASK 0x0000001f 39 + #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 40 + #define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 41 + #define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 42 + #define XTENSA_MPU_MEM_TYPE_SHIFT 12 43 + #define XTENSA_MPU_ATTR_MASK 0x001fff00 44 + 45 + #define XTENSA_MPU_PROBE_B 0x40000000 46 + #define XTENSA_MPU_PROBE_V 0x80000000 47 + 48 + #define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 49 + #define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 50 + #define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 51 + #define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 52 + 53 + #define XTENSA_MPU_TYPE_SYS_C 0x0010 54 + #define XTENSA_MPU_TYPE_SYS_W 0x0020 55 + #define XTENSA_MPU_TYPE_SYS_R 0x0040 56 + #define XTENSA_MPU_TYPE_CPU_C 0x0100 57 + #define XTENSA_MPU_TYPE_CPU_W 0x0200 58 + #define XTENSA_MPU_TYPE_CPU_R 0x0400 59 + #define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 60 + #define XTENSA_MPU_TYPE_B 0x1000 61 + #define XTENSA_MPU_TYPE_INT 0x2000 62 + 38 63 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) 39 64 { 40 65 /* ··· 78 103 /*! 79 104 * Get bit mask for the virtual address bits translated by the TLB way 80 105 */ 81 - uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 82 - bool dtlb, uint32_t way) 106 + static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, 107 + bool dtlb, uint32_t way) 83 108 { 84 109 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 85 110 bool varway56 = dtlb ? ··· 145 170 * Split virtual address into VPN (with index) and entry index 146 171 * for the given TLB way 147 172 */ 148 - void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, 149 - uint32_t *vpn, uint32_t wi, uint32_t *ei) 173 + static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, 174 + bool dtlb, uint32_t *vpn, 175 + uint32_t wi, uint32_t *ei) 150 176 { 151 177 bool varway56 = dtlb ? 152 178 env->config->dtlb.varway56 : ··· 213 239 } 214 240 } 215 241 242 + static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, 243 + unsigned wi, unsigned ei) 244 + { 245 + return dtlb ? 246 + env->dtlb[wi] + ei : 247 + env->itlb[wi] + ei; 248 + } 249 + 216 250 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, 217 251 uint32_t v, bool dtlb, uint32_t *pwi) 218 252 { ··· 227 261 return xtensa_tlb_get_entry(env, dtlb, wi, ei); 228 262 } 229 263 230 - uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 231 - { 232 - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 233 - uint32_t wi; 234 - const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 235 - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 236 - } else { 237 - return v & REGION_PAGE_MASK; 238 - } 239 - } 240 - 241 - uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 242 - { 243 - const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 244 - return entry->paddr | entry->attr; 245 - } 246 - 247 - void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 248 - { 249 - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 250 - uint32_t wi; 251 - xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 252 - if (entry->variable && entry->asid) { 253 - tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); 254 - entry->asid = 0; 255 - } 256 - } 257 - } 258 - 259 - uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 260 - { 261 - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 262 - uint32_t wi; 263 - uint32_t ei; 264 - uint8_t ring; 265 - int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 266 - 267 - switch (res) { 268 - case 0: 269 - if (ring >= xtensa_get_ring(env)) { 270 - return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 271 - } 272 - break; 273 - 274 - case INST_TLB_MULTI_HIT_CAUSE: 275 - case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 276 - HELPER(exception_cause_vaddr)(env, env->pc, res, v); 277 - break; 278 - } 279 - return 0; 280 - } else { 281 - return (v & REGION_PAGE_MASK) | 0x1; 282 - } 283 - } 284 - 285 - void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 286 - xtensa_tlb_entry *entry, bool dtlb, 287 - unsigned wi, unsigned ei, uint32_t vpn, 288 - uint32_t pte) 264 + static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, 265 + xtensa_tlb_entry *entry, bool dtlb, 266 + unsigned wi, unsigned ei, uint32_t vpn, 267 + uint32_t pte) 289 268 { 290 269 entry->vaddr = vpn; 291 270 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); ··· 293 272 entry->attr = pte & 0xf; 294 273 } 295 274 296 - void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 297 - unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte) 275 + static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, 276 + unsigned wi, unsigned ei, 277 + uint32_t vpn, uint32_t pte) 298 278 { 299 279 XtensaCPU *cpu = xtensa_env_get_cpu(env); 300 280 CPUState *cs = CPU(cpu); ··· 320 300 } 321 301 entry->attr = pte & 0xf; 322 302 } 323 - } 324 - 325 - void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 326 - { 327 - uint32_t vpn; 328 - uint32_t wi; 329 - uint32_t ei; 330 - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 331 - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 332 303 } 333 304 334 305 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) ··· 436 407 reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); 437 408 reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); 438 409 reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); 410 + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 411 + unsigned i; 412 + 413 + env->sregs[MPUENB] = 0; 414 + env->sregs[MPUCFG] = env->config->n_mpu_fg_segments; 415 + env->sregs[CACHEADRDIS] = 0; 416 + assert(env->config->n_mpu_bg_segments > 0 && 417 + env->config->mpu_bg[0].vaddr == 0); 418 + for (i = 1; i < env->config->n_mpu_bg_segments; ++i) { 419 + assert(env->config->mpu_bg[i].vaddr >= 420 + env->config->mpu_bg[i - 1].vaddr); 421 + } 439 422 } else { 423 + env->sregs[CACHEATTR] = 0x22222222; 440 424 reset_tlb_region_way0(env, env->itlb); 441 425 reset_tlb_region_way0(env, env->dtlb); 442 426 } ··· 462 446 * \param pring: [out] access ring 463 447 * \return 0 if ok, exception cause code otherwise 464 448 */ 465 - int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, 466 - uint32_t *pwi, uint32_t *pei, uint8_t *pring) 449 + static int xtensa_tlb_lookup(const CPUXtensaState *env, 450 + uint32_t addr, bool dtlb, 451 + uint32_t *pwi, uint32_t *pei, uint8_t *pring) 467 452 { 468 453 const xtensa_tlb *tlb = dtlb ? 469 454 &env->config->dtlb : &env->config->itlb; ··· 495 480 (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); 496 481 } 497 482 483 + uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 484 + { 485 + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 486 + uint32_t wi; 487 + const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 488 + return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; 489 + } else { 490 + return v & REGION_PAGE_MASK; 491 + } 492 + } 493 + 494 + uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 495 + { 496 + const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); 497 + return entry->paddr | entry->attr; 498 + } 499 + 500 + void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 501 + { 502 + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 503 + uint32_t wi; 504 + xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); 505 + if (entry->variable && entry->asid) { 506 + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr); 507 + entry->asid = 0; 508 + } 509 + } 510 + } 511 + 512 + uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) 513 + { 514 + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { 515 + uint32_t wi; 516 + uint32_t ei; 517 + uint8_t ring; 518 + int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring); 519 + 520 + switch (res) { 521 + case 0: 522 + if (ring >= xtensa_get_ring(env)) { 523 + return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8); 524 + } 525 + break; 526 + 527 + case INST_TLB_MULTI_HIT_CAUSE: 528 + case LOAD_STORE_TLB_MULTI_HIT_CAUSE: 529 + HELPER(exception_cause_vaddr)(env, env->pc, res, v); 530 + break; 531 + } 532 + return 0; 533 + } else { 534 + return (v & REGION_PAGE_MASK) | 0x1; 535 + } 536 + } 537 + 538 + void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) 539 + { 540 + uint32_t vpn; 541 + uint32_t wi; 542 + uint32_t ei; 543 + split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); 544 + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); 545 + } 546 + 498 547 /*! 499 548 * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. 500 549 * See ISA, 4.6.5.10 ··· 568 617 return access[attr & 0xf]; 569 618 } 570 619 620 + struct attr_pattern { 621 + uint32_t mask; 622 + uint32_t value; 623 + }; 624 + 625 + static int attr_pattern_match(uint32_t attr, 626 + const struct attr_pattern *pattern, 627 + size_t n) 628 + { 629 + size_t i; 630 + 631 + for (i = 0; i < n; ++i) { 632 + if ((attr & pattern[i].mask) == pattern[i].value) { 633 + return 1; 634 + } 635 + } 636 + return 0; 637 + } 638 + 639 + static unsigned mpu_attr_to_cpu_cache(uint32_t attr) 640 + { 641 + static const struct attr_pattern cpu_c[] = { 642 + { .mask = 0x18f, .value = 0x089 }, 643 + { .mask = 0x188, .value = 0x080 }, 644 + { .mask = 0x180, .value = 0x180 }, 645 + }; 646 + 647 + unsigned type = 0; 648 + 649 + if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { 650 + type |= XTENSA_MPU_TYPE_CPU_CACHE; 651 + if (attr & 0x10) { 652 + type |= XTENSA_MPU_TYPE_CPU_C; 653 + } 654 + if (attr & 0x20) { 655 + type |= XTENSA_MPU_TYPE_CPU_W; 656 + } 657 + if (attr & 0x40) { 658 + type |= XTENSA_MPU_TYPE_CPU_R; 659 + } 660 + } 661 + return type; 662 + } 663 + 664 + static unsigned mpu_attr_to_type(uint32_t attr) 665 + { 666 + static const struct attr_pattern device_type[] = { 667 + { .mask = 0x1f6, .value = 0x000 }, 668 + { .mask = 0x1f6, .value = 0x006 }, 669 + }; 670 + static const struct attr_pattern sys_nc_type[] = { 671 + { .mask = 0x1fe, .value = 0x018 }, 672 + { .mask = 0x1fe, .value = 0x01e }, 673 + { .mask = 0x18f, .value = 0x089 }, 674 + }; 675 + static const struct attr_pattern sys_c_type[] = { 676 + { .mask = 0x1f8, .value = 0x010 }, 677 + { .mask = 0x188, .value = 0x080 }, 678 + { .mask = 0x1f0, .value = 0x030 }, 679 + { .mask = 0x180, .value = 0x180 }, 680 + }; 681 + static const struct attr_pattern b[] = { 682 + { .mask = 0x1f7, .value = 0x001 }, 683 + { .mask = 0x1f7, .value = 0x007 }, 684 + { .mask = 0x1ff, .value = 0x019 }, 685 + { .mask = 0x1ff, .value = 0x01f }, 686 + }; 687 + 688 + unsigned type = 0; 689 + 690 + attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT; 691 + if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { 692 + type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE; 693 + if (attr & 0x80) { 694 + type |= XTENSA_MPU_TYPE_INT; 695 + } 696 + } 697 + if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { 698 + type |= XTENSA_MPU_SYSTEM_TYPE_NC; 699 + } 700 + if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { 701 + type |= XTENSA_MPU_SYSTEM_TYPE_C; 702 + if (attr & 0x1) { 703 + type |= XTENSA_MPU_TYPE_SYS_C; 704 + } 705 + if (attr & 0x2) { 706 + type |= XTENSA_MPU_TYPE_SYS_W; 707 + } 708 + if (attr & 0x4) { 709 + type |= XTENSA_MPU_TYPE_SYS_R; 710 + } 711 + } 712 + if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { 713 + type |= XTENSA_MPU_TYPE_B; 714 + } 715 + type |= mpu_attr_to_cpu_cache(attr); 716 + 717 + return type; 718 + } 719 + 720 + static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) 721 + { 722 + static const unsigned access[2][16] = { 723 + [0] = { 724 + [4] = PAGE_READ, 725 + [5] = PAGE_READ | PAGE_EXEC, 726 + [6] = PAGE_READ | PAGE_WRITE, 727 + [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 728 + [8] = PAGE_WRITE, 729 + [9] = PAGE_READ | PAGE_WRITE, 730 + [10] = PAGE_READ | PAGE_WRITE, 731 + [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 732 + [12] = PAGE_READ, 733 + [13] = PAGE_READ | PAGE_EXEC, 734 + [14] = PAGE_READ | PAGE_WRITE, 735 + [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 736 + }, 737 + [1] = { 738 + [8] = PAGE_WRITE, 739 + [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 740 + [10] = PAGE_READ, 741 + [11] = PAGE_READ | PAGE_EXEC, 742 + [12] = PAGE_READ, 743 + [13] = PAGE_READ | PAGE_EXEC, 744 + [14] = PAGE_READ | PAGE_WRITE, 745 + [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, 746 + }, 747 + }; 748 + unsigned rv; 749 + unsigned type; 750 + 751 + type = mpu_attr_to_cpu_cache(attr); 752 + rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> 753 + XTENSA_MPU_ACC_RIGHTS_SHIFT]; 754 + 755 + if (type & XTENSA_MPU_TYPE_CPU_CACHE) { 756 + rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT; 757 + } else { 758 + rv |= PAGE_CACHE_BYPASS; 759 + } 760 + return rv; 761 + } 762 + 571 763 static bool is_access_granted(unsigned access, int is_write) 572 764 { 573 765 switch (is_write) { ··· 712 904 return 0; 713 905 } 714 906 907 + static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, 908 + uint32_t vaddr, unsigned *segment) 909 + { 910 + unsigned nhits = 0; 911 + unsigned i; 912 + 913 + for (i = 0; i < n; ++i) { 914 + if (vaddr >= entry[i].vaddr && 915 + (i == n - 1 || vaddr < entry[i + 1].vaddr)) { 916 + if (nhits++) { 917 + break; 918 + } 919 + *segment = i; 920 + } 921 + } 922 + return nhits; 923 + } 924 + 925 + void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) 926 + { 927 + XtensaCPU *cpu = xtensa_env_get_cpu(env); 928 + 929 + v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1; 930 + 931 + if (v != env->sregs[MPUENB]) { 932 + env->sregs[MPUENB] = v; 933 + tlb_flush(CPU(cpu)); 934 + } 935 + } 936 + 937 + void HELPER(wptlb)(CPUXtensaState *env, uint32_t p, uint32_t v) 938 + { 939 + unsigned segment = p & XTENSA_MPU_SEGMENT_MASK; 940 + 941 + if (segment < env->config->n_mpu_fg_segments) { 942 + env->mpu_fg[segment].vaddr = v & -env->config->mpu_align; 943 + env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK; 944 + env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v); 945 + tlb_flush(CPU(xtensa_env_get_cpu(env))); 946 + } 947 + } 948 + 949 + uint32_t HELPER(rptlb0)(CPUXtensaState *env, uint32_t s) 950 + { 951 + unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 952 + 953 + if (segment < env->config->n_mpu_fg_segments) { 954 + return env->mpu_fg[segment].vaddr | 955 + extract32(env->sregs[MPUENB], segment, 1); 956 + } else { 957 + return 0; 958 + } 959 + } 960 + 961 + uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s) 962 + { 963 + unsigned segment = s & XTENSA_MPU_SEGMENT_MASK; 964 + 965 + if (segment < env->config->n_mpu_fg_segments) { 966 + return env->mpu_fg[segment].attr; 967 + } else { 968 + return 0; 969 + } 970 + } 971 + 972 + uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) 973 + { 974 + unsigned nhits; 975 + unsigned segment = XTENSA_MPU_PROBE_B; 976 + unsigned bg_segment; 977 + 978 + nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 979 + v, &segment); 980 + if (nhits > 1) { 981 + HELPER(exception_cause_vaddr)(env, env->pc, 982 + LOAD_STORE_TLB_MULTI_HIT_CAUSE, v); 983 + } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 984 + return env->mpu_fg[segment].attr | segment | XTENSA_MPU_PROBE_V; 985 + } else { 986 + xtensa_mpu_lookup(env->config->mpu_bg, 987 + env->config->n_mpu_bg_segments, 988 + v, &bg_segment); 989 + return env->config->mpu_bg[bg_segment].attr | segment; 990 + } 991 + } 992 + 993 + static int get_physical_addr_mpu(CPUXtensaState *env, 994 + uint32_t vaddr, int is_write, int mmu_idx, 995 + uint32_t *paddr, uint32_t *page_size, 996 + unsigned *access) 997 + { 998 + unsigned nhits; 999 + unsigned segment; 1000 + uint32_t attr; 1001 + 1002 + nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, 1003 + vaddr, &segment); 1004 + if (nhits > 1) { 1005 + return is_write < 2 ? 1006 + LOAD_STORE_TLB_MULTI_HIT_CAUSE : 1007 + INST_TLB_MULTI_HIT_CAUSE; 1008 + } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { 1009 + attr = env->mpu_fg[segment].attr; 1010 + } else { 1011 + xtensa_mpu_lookup(env->config->mpu_bg, 1012 + env->config->n_mpu_bg_segments, 1013 + vaddr, &segment); 1014 + attr = env->config->mpu_bg[segment].attr; 1015 + } 1016 + 1017 + *access = mpu_attr_to_access(attr, mmu_idx); 1018 + if (!is_access_granted(*access, is_write)) { 1019 + return is_write < 2 ? 1020 + (is_write ? 1021 + STORE_PROHIBITED_CAUSE : 1022 + LOAD_PROHIBITED_CAUSE) : 1023 + INST_FETCH_PROHIBITED_CAUSE; 1024 + } 1025 + *paddr = vaddr; 1026 + *page_size = env->config->mpu_align; 1027 + return 0; 1028 + } 1029 + 715 1030 /*! 716 1031 * Convert virtual address to physical addr. 717 1032 * MMU may issue pagewalk and change xtensa autorefill TLB way entry. ··· 732 1047 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { 733 1048 return get_physical_addr_region(env, vaddr, is_write, mmu_idx, 734 1049 paddr, page_size, access); 1050 + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1051 + return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, 1052 + paddr, page_size, access); 735 1053 } else { 736 1054 *paddr = vaddr; 737 1055 *page_size = TARGET_PAGE_SIZE; ··· 799 1117 } 800 1118 } 801 1119 1120 + static void dump_mpu(CPUXtensaState *env, 1121 + const xtensa_mpu_entry *entry, unsigned n) 1122 + { 1123 + unsigned i; 1124 + 1125 + qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" 1126 + "\t%s ---------- ---------- ----- ----- ------------- ---------\n", 1127 + env ? "En" : " ", 1128 + env ? "--" : " "); 1129 + 1130 + for (i = 0; i < n; ++i) { 1131 + uint32_t attr = entry[i].attr; 1132 + unsigned access0 = mpu_attr_to_access(attr, 0); 1133 + unsigned access1 = mpu_attr_to_access(attr, 1); 1134 + unsigned type = mpu_attr_to_type(attr); 1135 + char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; 1136 + 1137 + qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", 1138 + env ? 1139 + ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', 1140 + entry[i].vaddr, attr, 1141 + (access0 & PAGE_READ) ? 'R' : '-', 1142 + (access0 & PAGE_WRITE) ? 'W' : '-', 1143 + (access0 & PAGE_EXEC) ? 'X' : '-', 1144 + (access1 & PAGE_READ) ? 'R' : '-', 1145 + (access1 & PAGE_WRITE) ? 'W' : '-', 1146 + (access1 & PAGE_EXEC) ? 'X' : '-'); 1147 + 1148 + switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { 1149 + case XTENSA_MPU_SYSTEM_TYPE_DEVICE: 1150 + qemu_printf("Device %cB %3s\n", 1151 + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1152 + (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); 1153 + break; 1154 + case XTENSA_MPU_SYSTEM_TYPE_NC: 1155 + qemu_printf("Sys NC %cB %c%c%c\n", 1156 + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', 1157 + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1158 + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1159 + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1160 + break; 1161 + case XTENSA_MPU_SYSTEM_TYPE_C: 1162 + qemu_printf("Sys C %c%c%c %c%c%c\n", 1163 + (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', 1164 + (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', 1165 + (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', 1166 + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, 1167 + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, 1168 + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); 1169 + break; 1170 + default: 1171 + qemu_printf("Unknown\n"); 1172 + break; 1173 + } 1174 + } 1175 + } 1176 + 802 1177 void dump_mmu(CPUXtensaState *env) 803 1178 { 804 1179 if (xtensa_option_bits_enabled(env->config, ··· 810 1185 dump_tlb(env, false); 811 1186 qemu_printf("\nDTLB:\n"); 812 1187 dump_tlb(env, true); 1188 + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { 1189 + qemu_printf("Foreground map:\n"); 1190 + dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments); 1191 + qemu_printf("\nBackground map:\n"); 1192 + dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments); 813 1193 } else { 814 1194 qemu_printf("No TLB for this CPU core\n"); 815 1195 }

+42

target/xtensa/op_helper.c

··· 130 130 } 131 131 } 132 132 133 + void HELPER(check_exclusive)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr, 134 + uint32_t is_write) 135 + { 136 + uint32_t paddr, page_size, access; 137 + uint32_t atomctl = env->sregs[ATOMCTL]; 138 + int rc = xtensa_get_physical_addr(env, true, vaddr, is_write, 139 + xtensa_get_cring(env), &paddr, 140 + &page_size, &access); 141 + 142 + if (rc) { 143 + HELPER(exception_cause_vaddr)(env, pc, rc, vaddr); 144 + } 145 + 146 + /* When data cache is not configured use ATOMCTL bypass field. */ 147 + if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) { 148 + access = PAGE_CACHE_BYPASS; 149 + } 150 + 151 + switch (access & PAGE_CACHE_MASK) { 152 + case PAGE_CACHE_WB: 153 + atomctl >>= 2; 154 + /* fall through */ 155 + case PAGE_CACHE_WT: 156 + atomctl >>= 2; 157 + /* fall through */ 158 + case PAGE_CACHE_BYPASS: 159 + if ((atomctl & 0x3) == 0) { 160 + HELPER(exception_cause_vaddr)(env, pc, 161 + EXCLUSIVE_ERROR_CAUSE, vaddr); 162 + } 163 + break; 164 + 165 + case PAGE_CACHE_ISOLATE: 166 + HELPER(exception_cause_vaddr)(env, pc, 167 + LOAD_STORE_ERROR_CAUSE, vaddr); 168 + break; 169 + 170 + default: 171 + break; 172 + } 173 + } 174 + 133 175 void HELPER(wsr_memctl)(CPUXtensaState *env, uint32_t v) 134 176 { 135 177 if (xtensa_option_enabled(env->config, XTENSA_OPTION_ICACHE)) {

+41 -2

target/xtensa/overlay_tool.h

··· 72 72 #define XCHAL_HAVE_EXTERN_REGS 0 73 73 #endif 74 74 75 + #ifndef XCHAL_HAVE_MPU 76 + #define XCHAL_HAVE_MPU 0 77 + #endif 78 + 79 + #ifndef XCHAL_HAVE_EXCLUSIVE 80 + #define XCHAL_HAVE_EXCLUSIVE 0 81 + #endif 82 + 75 83 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0) 76 84 77 85 #define XTENSA_OPTIONS ( \ ··· 92 100 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ 93 101 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ 94 102 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ 95 - XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \ 96 - XTENSA_OPTION_ATOMCTL) | \ 103 + XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \ 104 + XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \ 97 105 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \ 98 106 /* Interrupts and exceptions */ \ 99 107 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \ ··· 112 120 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ 113 121 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ 114 122 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ 123 + XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ 124 + XTENSA_OPTION_MEMORY_ECC_PARITY) | \ 115 125 /* Memory protection and translation */ \ 116 126 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ 117 127 XTENSA_OPTION_REGION_PROTECTION) | \ 118 128 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \ 119 129 XTENSA_OPTION_REGION_TRANSLATION) | \ 130 + XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \ 120 131 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \ 121 132 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \ 122 133 /* Other, TODO */ \ ··· 200 211 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR 201 212 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR 202 213 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING 214 + #define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE 215 + #define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR 216 + #define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR 203 217 204 218 205 219 #define INTERRUPT(i) { \ ··· 356 370 #define XCHAL_SYSRAM0_SIZE 0x04000000 357 371 #endif 358 372 373 + #elif XCHAL_HAVE_MPU 374 + 375 + #ifndef XTENSA_MPU_BG_MAP 376 + #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\ 377 + { .vaddr = 0, .attr = 0x00006700, }, \ 378 + } 379 + #endif 380 + 381 + #define TLB_SECTION \ 382 + .mpu_align = XCHAL_MPU_ALIGN, \ 383 + .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \ 384 + .n_mpu_bg_segments = 1, \ 385 + .mpu_bg = XTENSA_MPU_BG_MAP 386 + 387 + #ifndef XCHAL_SYSROM0_PADDR 388 + #define XCHAL_SYSROM0_PADDR 0x50000000 389 + #define XCHAL_SYSROM0_SIZE 0x04000000 390 + #endif 391 + 392 + #ifndef XCHAL_SYSRAM0_PADDR 393 + #define XCHAL_SYSRAM0_PADDR 0x60000000 394 + #define XCHAL_SYSRAM0_SIZE 0x04000000 395 + #endif 396 + 359 397 #else 360 398 361 399 #ifndef XCHAL_SYSROM0_PADDR ··· 391 429 #define CACHE_SECTION \ 392 430 .icache_ways = XCHAL_ICACHE_WAYS, \ 393 431 .dcache_ways = XCHAL_DCACHE_WAYS, \ 432 + .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ 394 433 .memctl_mask = \ 395 434 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ 396 435 (XCHAL_DCACHE_SIZE ? \

+1940 -1003

target/xtensa/translate.c

··· 87 87 static TCGv_i32 cpu_SR[256]; 88 88 static TCGv_i32 cpu_UR[256]; 89 89 static TCGv_i32 cpu_windowbase_next; 90 + static TCGv_i32 cpu_exclusive_addr; 91 + static TCGv_i32 cpu_exclusive_val; 90 92 91 93 static GHashTable *xtensa_regfile_table; 92 94 93 95 #include "exec/gen-icount.h" 94 96 95 - typedef struct XtensaReg { 96 - const char *name; 97 - uint64_t opt_bits; 98 - enum { 99 - SR_R = 1, 100 - SR_W = 2, 101 - SR_X = 4, 102 - SR_RW = 3, 103 - SR_RWX = 7, 104 - } access; 105 - } XtensaReg; 97 + static char *sr_name[256]; 98 + static char *ur_name[256]; 106 99 107 - #define XTENSA_REG_ACCESS(regname, opt, acc) { \ 108 - .name = (regname), \ 109 - .opt_bits = XTENSA_OPTION_BIT(opt), \ 110 - .access = (acc), \ 111 - } 100 + void xtensa_collect_sr_names(const XtensaConfig *config) 101 + { 102 + xtensa_isa isa = config->isa; 103 + int n = xtensa_isa_num_sysregs(isa); 104 + int i; 112 105 113 - #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX) 106 + for (i = 0; i < n; ++i) { 107 + int sr = xtensa_sysreg_number(isa, i); 114 108 115 - #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \ 116 - .name = (regname), \ 117 - .opt_bits = (opt), \ 118 - .access = (acc), \ 119 - } 109 + if (sr >= 0 && sr < 256) { 110 + const char *name = xtensa_sysreg_name(isa, i); 111 + char **pname = 112 + (xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr; 120 113 121 - #define XTENSA_REG_BITS(regname, opt) \ 122 - XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX) 123 - 124 - static const XtensaReg sregnames[256] = { 125 - [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP), 126 - [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP), 127 - [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP), 128 - [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL), 129 - [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN), 130 - [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R), 131 - [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE), 132 - [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16), 133 - [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16), 134 - [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16), 135 - [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), 136 - [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), 137 - [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), 138 - [PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL), 139 - [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), 140 - [WINDOW_START] = XTENSA_REG("WINDOW_START", 141 - XTENSA_OPTION_WINDOWED_REGISTER), 142 - [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU), 143 - [MMID] = XTENSA_REG_BITS("MMID", XTENSA_OPTION_ALL), 144 - [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU), 145 - [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU), 146 - [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU), 147 - [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG), 148 - [MEMCTL] = XTENSA_REG_BITS("MEMCTL", XTENSA_OPTION_ALL), 149 - [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR), 150 - [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL), 151 - [DDR] = XTENSA_REG("DDR", XTENSA_OPTION_DEBUG), 152 - [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG), 153 - [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG), 154 - [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG), 155 - [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG), 156 - [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG), 157 - [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG), 158 - [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R), 159 - [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION), 160 - [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 161 - [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 162 - [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 163 - [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 164 - [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 165 - [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 166 - [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION), 167 - [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 168 - [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 169 - [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 170 - [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 171 - [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 172 - [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 173 - [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R), 174 - [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION), 175 - [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2", 176 - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 177 - [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3", 178 - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 179 - [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4", 180 - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 181 - [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5", 182 - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 183 - [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6", 184 - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 185 - [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7", 186 - XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT), 187 - [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR), 188 - [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW), 189 - [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W), 190 - [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT), 191 - [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL), 192 - [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR), 193 - [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION), 194 - [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R), 195 - [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT), 196 - [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R), 197 - [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG), 198 - [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG), 199 - [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION), 200 - [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT), 201 - [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1", 202 - XTENSA_OPTION_TIMER_INTERRUPT), 203 - [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2", 204 - XTENSA_OPTION_TIMER_INTERRUPT), 205 - [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR), 206 - [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR), 207 - [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR), 208 - [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR), 209 - }; 114 + if (*pname) { 115 + if (strstr(*pname, name) == NULL) { 116 + char *new_name = 117 + malloc(strlen(*pname) + strlen(name) + 2); 210 118 211 - static const XtensaReg uregnames[256] = { 212 - [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), 213 - [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), 214 - [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), 215 - [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), 216 - }; 119 + strcpy(new_name, *pname); 120 + strcat(new_name, "/"); 121 + strcat(new_name, name); 122 + free(*pname); 123 + *pname = new_name; 124 + } 125 + } else { 126 + *pname = strdup(name); 127 + } 128 + } 129 + } 130 + } 217 131 218 132 void xtensa_translate_init(void) 219 133 { ··· 283 197 } 284 198 285 199 for (i = 0; i < 256; ++i) { 286 - if (sregnames[i].name) { 200 + if (sr_name[i]) { 287 201 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env, 288 - offsetof(CPUXtensaState, sregs[i]), 289 - sregnames[i].name); 202 + offsetof(CPUXtensaState, 203 + sregs[i]), 204 + sr_name[i]); 290 205 } 291 206 } 292 207 293 208 for (i = 0; i < 256; ++i) { 294 - if (uregnames[i].name) { 209 + if (ur_name[i]) { 295 210 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env, 296 - offsetof(CPUXtensaState, uregs[i]), 297 - uregnames[i].name); 211 + offsetof(CPUXtensaState, 212 + uregs[i]), 213 + ur_name[i]); 298 214 } 299 215 } 300 216 ··· 302 218 tcg_global_mem_new_i32(cpu_env, 303 219 offsetof(CPUXtensaState, windowbase_next), 304 220 "windowbase_next"); 221 + cpu_exclusive_addr = 222 + tcg_global_mem_new_i32(cpu_env, 223 + offsetof(CPUXtensaState, exclusive_addr), 224 + "exclusive_addr"); 225 + cpu_exclusive_val = 226 + tcg_global_mem_new_i32(cpu_env, 227 + offsetof(CPUXtensaState, exclusive_val), 228 + "exclusive_val"); 305 229 } 306 230 307 231 void **xtensa_get_regfile_by_name(const char *name) ··· 536 460 tcg_temp_free(tmp); 537 461 } 538 462 539 - static bool check_sr(DisasContext *dc, uint32_t sr, unsigned access) 540 - { 541 - if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) { 542 - if (sregnames[sr].name) { 543 - qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name); 544 - } else { 545 - qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr); 546 - } 547 - return false; 548 - } else if (!(sregnames[sr].access & access)) { 549 - static const char * const access_text[] = { 550 - [SR_R] = "rsr", 551 - [SR_W] = "wsr", 552 - [SR_X] = "xsr", 553 - }; 554 - assert(access < ARRAY_SIZE(access_text) && access_text[access]); 555 - qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name, 556 - access_text[access]); 557 - return false; 558 - } 559 - return true; 560 - } 561 - 562 - #ifndef CONFIG_USER_ONLY 563 - static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) 564 - { 565 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 566 - gen_io_start(); 567 - } 568 - gen_helper_update_ccount(cpu_env); 569 - tcg_gen_mov_i32(d, cpu_SR[sr]); 570 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 571 - gen_io_end(); 572 - } 573 - } 574 - 575 - static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 576 - { 577 - tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10); 578 - tcg_gen_or_i32(d, d, cpu_SR[sr]); 579 - tcg_gen_andi_i32(d, d, 0xfffffffc); 580 - } 581 - #endif 582 - 583 - static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr) 584 - { 585 - static void (* const rsr_handler[256])(DisasContext *dc, 586 - TCGv_i32 d, uint32_t sr) = { 587 - #ifndef CONFIG_USER_ONLY 588 - [CCOUNT] = gen_rsr_ccount, 589 - [INTSET] = gen_rsr_ccount, 590 - [PTEVADDR] = gen_rsr_ptevaddr, 591 - #endif 592 - }; 593 - 594 - if (rsr_handler[sr]) { 595 - rsr_handler[sr](dc, d, sr); 596 - } else { 597 - tcg_gen_mov_i32(d, cpu_SR[sr]); 598 - } 599 - } 600 - 601 - static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s) 602 - { 603 - tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f); 604 - if (dc->sar_m32_5bit) { 605 - tcg_gen_discard_i32(dc->sar_m32); 606 - } 607 - dc->sar_5bit = false; 608 - dc->sar_m32_5bit = false; 609 - } 610 - 611 - static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s) 612 - { 613 - tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff); 614 - } 615 - 616 - static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s) 617 - { 618 - tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001); 619 - } 620 - 621 - static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) 622 - { 623 - tcg_gen_ext8s_i32(cpu_SR[sr], s); 624 - } 625 - 626 - #ifndef CONFIG_USER_ONLY 627 - static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) 628 - { 629 - tcg_gen_mov_i32(cpu_windowbase_next, v); 630 - } 631 - 632 - static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) 633 - { 634 - tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1); 635 - } 636 - 637 - static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v) 638 - { 639 - tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000); 640 - } 641 - 642 - static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v) 643 - { 644 - gen_helper_wsr_rasid(cpu_env, v); 645 - } 646 - 647 - static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v) 648 - { 649 - tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000); 650 - } 651 - 652 - static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 653 - { 654 - gen_helper_wsr_ibreakenable(cpu_env, v); 655 - } 656 - 657 - static void gen_wsr_memctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 658 - { 659 - gen_helper_wsr_memctl(cpu_env, v); 660 - } 661 - 662 - static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v) 663 - { 664 - tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f); 665 - } 666 - 667 - static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 668 - { 669 - unsigned id = sr - IBREAKA; 670 - TCGv_i32 tmp = tcg_const_i32(id); 671 - 672 - assert(id < dc->config->nibreak); 673 - gen_helper_wsr_ibreaka(cpu_env, tmp, v); 674 - tcg_temp_free(tmp); 675 - } 676 - 677 - static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v) 678 - { 679 - unsigned id = sr - DBREAKA; 680 - TCGv_i32 tmp = tcg_const_i32(id); 681 - 682 - assert(id < dc->config->ndbreak); 683 - gen_helper_wsr_dbreaka(cpu_env, tmp, v); 684 - tcg_temp_free(tmp); 685 - } 686 - 687 - static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v) 688 - { 689 - unsigned id = sr - DBREAKC; 690 - TCGv_i32 tmp = tcg_const_i32(id); 691 - 692 - assert(id < dc->config->ndbreak); 693 - gen_helper_wsr_dbreakc(cpu_env, tmp, v); 694 - tcg_temp_free(tmp); 695 - } 696 - 697 - static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 698 - { 699 - tcg_gen_andi_i32(cpu_SR[sr], v, 0xff); 700 - } 701 - 702 - static void gen_check_interrupts(DisasContext *dc) 703 - { 704 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 705 - gen_io_start(); 706 - } 707 - gen_helper_check_interrupts(cpu_env); 708 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 709 - gen_io_end(); 710 - } 711 - } 712 - 713 - static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v) 463 + static bool test_ill_sr(DisasContext *dc, const OpcodeArg arg[], 464 + const uint32_t par[]) 714 465 { 715 - gen_helper_intset(cpu_env, v); 466 + return !xtensa_option_enabled(dc->config, par[1]); 716 467 } 717 468 718 - static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v) 469 + static bool test_ill_ccompare(DisasContext *dc, const OpcodeArg arg[], 470 + const uint32_t par[]) 719 471 { 720 - gen_helper_intclear(cpu_env, v); 721 - } 472 + unsigned n = par[0] - CCOMPARE; 722 473 723 - static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) 724 - { 725 - tcg_gen_mov_i32(cpu_SR[sr], v); 474 + return test_ill_sr(dc, arg, par) || n >= dc->config->nccompare; 726 475 } 727 476 728 - static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) 477 + static bool test_ill_dbreak(DisasContext *dc, const OpcodeArg arg[], 478 + const uint32_t par[]) 729 479 { 730 - uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | 731 - PS_UM | PS_EXCM | PS_INTLEVEL; 732 - 733 - if (option_enabled(dc, XTENSA_OPTION_MMU)) { 734 - mask |= PS_RING; 735 - } 736 - tcg_gen_andi_i32(cpu_SR[sr], v, mask); 737 - } 480 + unsigned n = MAX_NDBREAK; 738 481 739 - static void gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 740 - { 741 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 742 - gen_io_start(); 482 + if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) { 483 + n = par[0] - DBREAKA; 743 484 } 744 - gen_helper_wsr_ccount(cpu_env, v); 745 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 746 - gen_io_end(); 485 + if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) { 486 + n = par[0] - DBREAKC; 747 487 } 488 + return test_ill_sr(dc, arg, par) || n >= dc->config->ndbreak; 748 489 } 749 490 750 - static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v) 491 + static bool test_ill_ibreak(DisasContext *dc, const OpcodeArg arg[], 492 + const uint32_t par[]) 751 493 { 752 - if (dc->icount) { 753 - tcg_gen_mov_i32(dc->next_icount, v); 754 - } else { 755 - tcg_gen_mov_i32(cpu_SR[sr], v); 756 - } 757 - } 494 + unsigned n = par[0] - IBREAKA; 758 495 759 - static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v) 760 - { 761 - tcg_gen_andi_i32(cpu_SR[sr], v, 0xf); 496 + return test_ill_sr(dc, arg, par) || n >= dc->config->nibreak; 762 497 } 763 498 764 - static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) 499 + static bool test_ill_hpi(DisasContext *dc, const OpcodeArg arg[], 500 + const uint32_t par[]) 765 501 { 766 - uint32_t id = sr - CCOMPARE; 767 - TCGv_i32 tmp = tcg_const_i32(id); 502 + unsigned n = MAX_NLEVEL + 1; 768 503 769 - assert(id < dc->config->nccompare); 770 - tcg_gen_mov_i32(cpu_SR[sr], v); 771 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 772 - gen_io_start(); 773 - } 774 - gen_helper_update_ccompare(cpu_env, tmp); 775 - tcg_temp_free(tmp); 776 - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 777 - gen_io_end(); 504 + if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) { 505 + n = par[0] - EXCSAVE1 + 1; 778 506 } 779 - } 780 - #else 781 - static void gen_check_interrupts(DisasContext *dc) 782 - { 783 - } 784 - #endif 785 - 786 - static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) 787 - { 788 - static void (* const wsr_handler[256])(DisasContext *dc, 789 - uint32_t sr, TCGv_i32 v) = { 790 - [SAR] = gen_wsr_sar, 791 - [BR] = gen_wsr_br, 792 - [LITBASE] = gen_wsr_litbase, 793 - [ACCHI] = gen_wsr_acchi, 794 - #ifndef CONFIG_USER_ONLY 795 - [WINDOW_BASE] = gen_wsr_windowbase, 796 - [WINDOW_START] = gen_wsr_windowstart, 797 - [PTEVADDR] = gen_wsr_ptevaddr, 798 - [RASID] = gen_wsr_rasid, 799 - [ITLBCFG] = gen_wsr_tlbcfg, 800 - [DTLBCFG] = gen_wsr_tlbcfg, 801 - [IBREAKENABLE] = gen_wsr_ibreakenable, 802 - [MEMCTL] = gen_wsr_memctl, 803 - [ATOMCTL] = gen_wsr_atomctl, 804 - [IBREAKA] = gen_wsr_ibreaka, 805 - [IBREAKA + 1] = gen_wsr_ibreaka, 806 - [DBREAKA] = gen_wsr_dbreaka, 807 - [DBREAKA + 1] = gen_wsr_dbreaka, 808 - [DBREAKC] = gen_wsr_dbreakc, 809 - [DBREAKC + 1] = gen_wsr_dbreakc, 810 - [CPENABLE] = gen_wsr_cpenable, 811 - [INTSET] = gen_wsr_intset, 812 - [INTCLEAR] = gen_wsr_intclear, 813 - [INTENABLE] = gen_wsr_intenable, 814 - [PS] = gen_wsr_ps, 815 - [CCOUNT] = gen_wsr_ccount, 816 - [ICOUNT] = gen_wsr_icount, 817 - [ICOUNTLEVEL] = gen_wsr_icountlevel, 818 - [CCOMPARE] = gen_wsr_ccompare, 819 - [CCOMPARE + 1] = gen_wsr_ccompare, 820 - [CCOMPARE + 2] = gen_wsr_ccompare, 821 - #endif 822 - }; 823 - 824 - if (wsr_handler[sr]) { 825 - wsr_handler[sr](dc, sr, s); 826 - } else { 827 - tcg_gen_mov_i32(cpu_SR[sr], s); 507 + if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) { 508 + n = par[0] - EPC1 + 1; 828 509 } 829 - } 830 - 831 - static void gen_wur(uint32_t ur, TCGv_i32 s) 832 - { 833 - switch (ur) { 834 - case FCR: 835 - gen_helper_wur_fcr(cpu_env, s); 836 - break; 837 - 838 - case FSR: 839 - tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); 840 - break; 841 - 842 - default: 843 - tcg_gen_mov_i32(cpu_UR[ur], s); 844 - break; 510 + if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) { 511 + n = par[0] - EPS2 + 2; 845 512 } 513 + return test_ill_sr(dc, arg, par) || n > dc->config->nlevel; 846 514 } 847 515 848 516 static void gen_load_store_alignment(DisasContext *dc, int shift, ··· 925 593 { 926 594 uint32_t op_flags = dc->op_flags; 927 595 596 + #ifndef CONFIG_USER_ONLY 928 597 if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { 929 - gen_check_interrupts(dc); 598 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 599 + gen_io_start(); 600 + } 601 + gen_helper_check_interrupts(cpu_env); 602 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 603 + gen_io_end(); 604 + } 930 605 } 606 + #endif 931 607 if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { 932 608 gen_helper_sync_windowbase(cpu_env); 933 609 } ··· 1645 1321 { 1646 1322 XtensaCPU *cpu = XTENSA_CPU(cs); 1647 1323 CPUXtensaState *env = &cpu->env; 1324 + xtensa_isa isa = env->config->isa; 1648 1325 int i, j; 1649 1326 1650 1327 qemu_fprintf(f, "PC=%08x\n\n", env->pc); 1651 1328 1652 - for (i = j = 0; i < 256; ++i) { 1653 - if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) { 1654 - qemu_fprintf(f, "%12s=%08x%c", 1655 - sregnames[i].name, env->sregs[i], 1656 - (j++ % 4) == 3 ? '\n' : ' '); 1657 - } 1658 - } 1659 - 1660 - qemu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n"); 1329 + for (i = j = 0; i < xtensa_isa_num_sysregs(isa); ++i) { 1330 + const uint32_t *reg = 1331 + xtensa_sysreg_is_user(isa, i) ? env->uregs : env->sregs; 1332 + int regno = xtensa_sysreg_number(isa, i); 1661 1333 1662 - for (i = j = 0; i < 256; ++i) { 1663 - if (xtensa_option_bits_enabled(env->config, uregnames[i].opt_bits)) { 1664 - qemu_fprintf(f, "%s=%08x%c", 1665 - uregnames[i].name, env->uregs[i], 1334 + if (regno >= 0) { 1335 + qemu_fprintf(f, "%12s=%08x%c", 1336 + xtensa_sysreg_name(isa, i), 1337 + reg[regno], 1666 1338 (j++ % 4) == 3 ? '\n' : ' '); 1667 1339 } 1668 1340 } ··· 1923 1595 tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm)); 1924 1596 } 1925 1597 1598 + static void translate_clrex(DisasContext *dc, const OpcodeArg arg[], 1599 + const uint32_t par[]) 1600 + { 1601 + tcg_gen_movi_i32(cpu_exclusive_addr, -1); 1602 + } 1603 + 1926 1604 static void translate_const16(DisasContext *dc, const OpcodeArg arg[], 1927 1605 const uint32_t par[]) 1928 1606 { ··· 1951 1629 arg[2].imm, arg[3].imm); 1952 1630 } 1953 1631 1632 + static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[], 1633 + const uint32_t par[]) 1634 + { 1635 + tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes); 1636 + } 1637 + 1954 1638 static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], 1955 1639 const uint32_t par[]) 1956 1640 { ··· 1992 1676 tcg_temp_free(tmp); 1993 1677 } 1994 1678 1679 + static void translate_getex(DisasContext *dc, const OpcodeArg arg[], 1680 + const uint32_t par[]) 1681 + { 1682 + TCGv_i32 tmp = tcg_temp_new_i32(); 1683 + 1684 + tcg_gen_extract_i32(tmp, cpu_SR[ATOMCTL], 8, 1); 1685 + tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], arg[0].in, 8, 1); 1686 + tcg_gen_mov_i32(arg[0].out, tmp); 1687 + tcg_temp_free(tmp); 1688 + } 1689 + 1995 1690 static void translate_icache(DisasContext *dc, const OpcodeArg arg[], 1996 1691 const uint32_t par[]) 1997 1692 { ··· 2039 1734 tcg_temp_free(addr); 2040 1735 } 2041 1736 1737 + #ifdef CONFIG_USER_ONLY 1738 + static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write) 1739 + { 1740 + } 1741 + #else 1742 + static void gen_check_exclusive(DisasContext *dc, TCGv_i32 addr, bool is_write) 1743 + { 1744 + if (!option_enabled(dc, XTENSA_OPTION_MPU)) { 1745 + TCGv_i32 tpc = tcg_const_i32(dc->pc); 1746 + TCGv_i32 write = tcg_const_i32(is_write); 1747 + 1748 + gen_helper_check_exclusive(cpu_env, tpc, addr, write); 1749 + tcg_temp_free(tpc); 1750 + tcg_temp_free(write); 1751 + } 1752 + } 1753 + #endif 1754 + 1755 + static void translate_l32ex(DisasContext *dc, const OpcodeArg arg[], 1756 + const uint32_t par[]) 1757 + { 1758 + TCGv_i32 addr = tcg_temp_new_i32(); 1759 + 1760 + tcg_gen_mov_i32(addr, arg[1].in); 1761 + gen_load_store_alignment(dc, 2, addr, true); 1762 + gen_check_exclusive(dc, addr, false); 1763 + tcg_gen_qemu_ld_i32(arg[0].out, addr, dc->ring, MO_TEUL); 1764 + tcg_gen_mov_i32(cpu_exclusive_addr, addr); 1765 + tcg_gen_mov_i32(cpu_exclusive_val, arg[0].out); 1766 + tcg_temp_free(addr); 1767 + } 1768 + 2042 1769 static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], 2043 1770 const uint32_t par[]) 2044 1771 { ··· 2323 2050 #endif 2324 2051 } 2325 2052 2053 + static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[], 2054 + const uint32_t par[]) 2055 + { 2056 + #ifndef CONFIG_USER_ONLY 2057 + tcg_gen_movi_i32(cpu_pc, dc->pc); 2058 + gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in); 2059 + #endif 2060 + } 2061 + 2326 2062 static void translate_quos(DisasContext *dc, const OpcodeArg arg[], 2327 2063 const uint32_t par[]) 2328 2064 { ··· 2465 2201 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); 2466 2202 } 2467 2203 2468 - static bool test_ill_rsr(DisasContext *dc, const OpcodeArg arg[], 2469 - const uint32_t par[]) 2204 + static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], 2205 + const uint32_t par[]) 2470 2206 { 2471 - return !check_sr(dc, par[0], SR_R); 2207 + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); 2472 2208 } 2473 2209 2474 - static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], 2475 - const uint32_t par[]) 2210 + static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[], 2211 + const uint32_t par[]) 2476 2212 { 2477 - gen_rsr(dc, arg[0].out, par[0]); 2213 + #ifndef CONFIG_USER_ONLY 2214 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2215 + gen_io_start(); 2216 + } 2217 + gen_helper_update_ccount(cpu_env); 2218 + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); 2219 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2220 + gen_io_end(); 2221 + } 2222 + #endif 2223 + } 2224 + 2225 + static void translate_rsr_ptevaddr(DisasContext *dc, const OpcodeArg arg[], 2226 + const uint32_t par[]) 2227 + { 2228 + #ifndef CONFIG_USER_ONLY 2229 + TCGv_i32 tmp = tcg_temp_new_i32(); 2230 + 2231 + tcg_gen_shri_i32(tmp, cpu_SR[EXCVADDR], 10); 2232 + tcg_gen_or_i32(tmp, tmp, cpu_SR[PTEVADDR]); 2233 + tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc); 2234 + tcg_temp_free(tmp); 2235 + #endif 2478 2236 } 2479 2237 2480 2238 static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[], ··· 2493 2251 #endif 2494 2252 } 2495 2253 2254 + static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[], 2255 + const uint32_t par[]) 2256 + { 2257 + #ifndef CONFIG_USER_ONLY 2258 + gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in); 2259 + #endif 2260 + } 2261 + 2262 + static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[], 2263 + const uint32_t par[]) 2264 + { 2265 + #ifndef CONFIG_USER_ONLY 2266 + gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in); 2267 + #endif 2268 + } 2269 + 2496 2270 static void translate_rur(DisasContext *dc, const OpcodeArg arg[], 2497 2271 const uint32_t par[]) 2498 2272 { 2499 - if (uregnames[par[0]].name) { 2500 - tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); 2501 - } else { 2502 - qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]); 2503 - } 2273 + tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); 2504 2274 } 2505 2275 2506 2276 static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[], ··· 2551 2321 tcg_temp_free(addr); 2552 2322 } 2553 2323 2324 + static void translate_s32ex(DisasContext *dc, const OpcodeArg arg[], 2325 + const uint32_t par[]) 2326 + { 2327 + TCGv_i32 prev = tcg_temp_new_i32(); 2328 + TCGv_i32 addr = tcg_temp_local_new_i32(); 2329 + TCGv_i32 res = tcg_temp_local_new_i32(); 2330 + TCGLabel *label = gen_new_label(); 2331 + 2332 + tcg_gen_movi_i32(res, 0); 2333 + tcg_gen_mov_i32(addr, arg[1].in); 2334 + gen_load_store_alignment(dc, 2, addr, true); 2335 + tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, label); 2336 + gen_check_exclusive(dc, addr, true); 2337 + tcg_gen_atomic_cmpxchg_i32(prev, cpu_exclusive_addr, cpu_exclusive_val, 2338 + arg[0].in, dc->cring, MO_TEUL); 2339 + tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val); 2340 + tcg_gen_movcond_i32(TCG_COND_EQ, cpu_exclusive_val, 2341 + prev, cpu_exclusive_val, prev, cpu_exclusive_val); 2342 + tcg_gen_movi_i32(cpu_exclusive_addr, -1); 2343 + gen_set_label(label); 2344 + tcg_gen_extract_i32(arg[0].out, cpu_SR[ATOMCTL], 8, 1); 2345 + tcg_gen_deposit_i32(cpu_SR[ATOMCTL], cpu_SR[ATOMCTL], res, 8, 1); 2346 + tcg_temp_free(prev); 2347 + tcg_temp_free(addr); 2348 + tcg_temp_free(res); 2349 + } 2350 + 2554 2351 static void translate_salt(DisasContext *dc, const OpcodeArg arg[], 2555 2352 const uint32_t par[]) 2556 2353 { ··· 2758 2555 #endif 2759 2556 } 2760 2557 2558 + static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[], 2559 + const uint32_t par[]) 2560 + { 2561 + #ifndef CONFIG_USER_ONLY 2562 + gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in); 2563 + #endif 2564 + } 2565 + 2761 2566 static void translate_wer(DisasContext *dc, const OpcodeArg arg[], 2762 2567 const uint32_t par[]) 2763 2568 { ··· 2771 2576 tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in); 2772 2577 } 2773 2578 2774 - static bool test_ill_wsr(DisasContext *dc, const OpcodeArg arg[], 2775 - const uint32_t par[]) 2579 + static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], 2580 + const uint32_t par[]) 2581 + { 2582 + tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); 2583 + } 2584 + 2585 + static void translate_wsr_mask(DisasContext *dc, const OpcodeArg arg[], 2586 + const uint32_t par[]) 2587 + { 2588 + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, par[2]); 2589 + } 2590 + 2591 + static void translate_wsr_acchi(DisasContext *dc, const OpcodeArg arg[], 2592 + const uint32_t par[]) 2776 2593 { 2777 - return !check_sr(dc, par[0], SR_W); 2594 + tcg_gen_ext8s_i32(cpu_SR[par[0]], arg[0].in); 2595 + } 2596 + 2597 + static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[], 2598 + const uint32_t par[]) 2599 + { 2600 + #ifndef CONFIG_USER_ONLY 2601 + uint32_t id = par[0] - CCOMPARE; 2602 + TCGv_i32 tmp = tcg_const_i32(id); 2603 + 2604 + assert(id < dc->config->nccompare); 2605 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2606 + gen_io_start(); 2607 + } 2608 + tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); 2609 + gen_helper_update_ccompare(cpu_env, tmp); 2610 + tcg_temp_free(tmp); 2611 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2612 + gen_io_end(); 2613 + } 2614 + #endif 2778 2615 } 2779 2616 2780 - static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], 2781 - const uint32_t par[]) 2617 + static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[], 2618 + const uint32_t par[]) 2782 2619 { 2783 - gen_wsr(dc, par[0], arg[0].in); 2620 + #ifndef CONFIG_USER_ONLY 2621 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2622 + gen_io_start(); 2623 + } 2624 + gen_helper_wsr_ccount(cpu_env, arg[0].in); 2625 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2626 + gen_io_end(); 2627 + } 2628 + #endif 2784 2629 } 2785 2630 2786 - static void translate_wur(DisasContext *dc, const OpcodeArg arg[], 2787 - const uint32_t par[]) 2631 + static void translate_wsr_dbreaka(DisasContext *dc, const OpcodeArg arg[], 2632 + const uint32_t par[]) 2788 2633 { 2789 - if (uregnames[par[0]].name) { 2790 - gen_wur(par[0], arg[0].in); 2634 + #ifndef CONFIG_USER_ONLY 2635 + unsigned id = par[0] - DBREAKA; 2636 + TCGv_i32 tmp = tcg_const_i32(id); 2637 + 2638 + assert(id < dc->config->ndbreak); 2639 + gen_helper_wsr_dbreaka(cpu_env, tmp, arg[0].in); 2640 + tcg_temp_free(tmp); 2641 + #endif 2642 + } 2643 + 2644 + static void translate_wsr_dbreakc(DisasContext *dc, const OpcodeArg arg[], 2645 + const uint32_t par[]) 2646 + { 2647 + #ifndef CONFIG_USER_ONLY 2648 + unsigned id = par[0] - DBREAKC; 2649 + TCGv_i32 tmp = tcg_const_i32(id); 2650 + 2651 + assert(id < dc->config->ndbreak); 2652 + gen_helper_wsr_dbreakc(cpu_env, tmp, arg[0].in); 2653 + tcg_temp_free(tmp); 2654 + #endif 2655 + } 2656 + 2657 + static void translate_wsr_ibreaka(DisasContext *dc, const OpcodeArg arg[], 2658 + const uint32_t par[]) 2659 + { 2660 + #ifndef CONFIG_USER_ONLY 2661 + unsigned id = par[0] - IBREAKA; 2662 + TCGv_i32 tmp = tcg_const_i32(id); 2663 + 2664 + assert(id < dc->config->nibreak); 2665 + gen_helper_wsr_ibreaka(cpu_env, tmp, arg[0].in); 2666 + tcg_temp_free(tmp); 2667 + #endif 2668 + } 2669 + 2670 + static void translate_wsr_ibreakenable(DisasContext *dc, const OpcodeArg arg[], 2671 + const uint32_t par[]) 2672 + { 2673 + #ifndef CONFIG_USER_ONLY 2674 + gen_helper_wsr_ibreakenable(cpu_env, arg[0].in); 2675 + #endif 2676 + } 2677 + 2678 + static void translate_wsr_icount(DisasContext *dc, const OpcodeArg arg[], 2679 + const uint32_t par[]) 2680 + { 2681 + #ifndef CONFIG_USER_ONLY 2682 + if (dc->icount) { 2683 + tcg_gen_mov_i32(dc->next_icount, arg[0].in); 2791 2684 } else { 2792 - qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]); 2685 + tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); 2793 2686 } 2687 + #endif 2794 2688 } 2795 2689 2796 - static void translate_xor(DisasContext *dc, const OpcodeArg arg[], 2690 + static void translate_wsr_intclear(DisasContext *dc, const OpcodeArg arg[], 2691 + const uint32_t par[]) 2692 + { 2693 + #ifndef CONFIG_USER_ONLY 2694 + gen_helper_intclear(cpu_env, arg[0].in); 2695 + #endif 2696 + } 2697 + 2698 + static void translate_wsr_intset(DisasContext *dc, const OpcodeArg arg[], 2699 + const uint32_t par[]) 2700 + { 2701 + #ifndef CONFIG_USER_ONLY 2702 + gen_helper_intset(cpu_env, arg[0].in); 2703 + #endif 2704 + } 2705 + 2706 + static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[], 2707 + const uint32_t par[]) 2708 + { 2709 + #ifndef CONFIG_USER_ONLY 2710 + gen_helper_wsr_memctl(cpu_env, arg[0].in); 2711 + #endif 2712 + } 2713 + 2714 + static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[], 2715 + const uint32_t par[]) 2716 + { 2717 + #ifndef CONFIG_USER_ONLY 2718 + gen_helper_wsr_mpuenb(cpu_env, arg[0].in); 2719 + #endif 2720 + } 2721 + 2722 + static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[], 2723 + const uint32_t par[]) 2724 + { 2725 + #ifndef CONFIG_USER_ONLY 2726 + uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB | 2727 + PS_UM | PS_EXCM | PS_INTLEVEL; 2728 + 2729 + if (option_enabled(dc, XTENSA_OPTION_MMU)) { 2730 + mask |= PS_RING; 2731 + } 2732 + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask); 2733 + #endif 2734 + } 2735 + 2736 + static void translate_wsr_rasid(DisasContext *dc, const OpcodeArg arg[], 2737 + const uint32_t par[]) 2738 + { 2739 + #ifndef CONFIG_USER_ONLY 2740 + gen_helper_wsr_rasid(cpu_env, arg[0].in); 2741 + #endif 2742 + } 2743 + 2744 + static void translate_wsr_sar(DisasContext *dc, const OpcodeArg arg[], 2745 + const uint32_t par[]) 2746 + { 2747 + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f); 2748 + if (dc->sar_m32_5bit) { 2749 + tcg_gen_discard_i32(dc->sar_m32); 2750 + } 2751 + dc->sar_5bit = false; 2752 + dc->sar_m32_5bit = false; 2753 + } 2754 + 2755 + static void translate_wsr_windowbase(DisasContext *dc, const OpcodeArg arg[], 2756 + const uint32_t par[]) 2757 + { 2758 + #ifndef CONFIG_USER_ONLY 2759 + tcg_gen_mov_i32(cpu_windowbase_next, arg[0].in); 2760 + #endif 2761 + } 2762 + 2763 + static void translate_wsr_windowstart(DisasContext *dc, const OpcodeArg arg[], 2764 + const uint32_t par[]) 2765 + { 2766 + #ifndef CONFIG_USER_ONLY 2767 + tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 2768 + (1 << dc->config->nareg / 4) - 1); 2769 + #endif 2770 + } 2771 + 2772 + static void translate_wur(DisasContext *dc, const OpcodeArg arg[], 2797 2773 const uint32_t par[]) 2798 2774 { 2799 - tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); 2775 + tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); 2800 2776 } 2801 2777 2802 - static bool test_ill_xsr(DisasContext *dc, const OpcodeArg arg[], 2803 - const uint32_t par[]) 2778 + static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[], 2779 + const uint32_t par[]) 2804 2780 { 2805 - return !check_sr(dc, par[0], SR_X); 2781 + gen_helper_wur_fcr(cpu_env, arg[0].in); 2782 + } 2783 + 2784 + static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[], 2785 + const uint32_t par[]) 2786 + { 2787 + tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); 2788 + } 2789 + 2790 + static void translate_xor(DisasContext *dc, const OpcodeArg arg[], 2791 + const uint32_t par[]) 2792 + { 2793 + tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); 2806 2794 } 2807 2795 2808 2796 static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], ··· 2811 2799 TCGv_i32 tmp = tcg_temp_new_i32(); 2812 2800 2813 2801 tcg_gen_mov_i32(tmp, arg[0].in); 2814 - gen_rsr(dc, arg[0].out, par[0]); 2815 - gen_wsr(dc, par[0], tmp); 2802 + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); 2803 + tcg_gen_mov_i32(cpu_SR[par[0]], tmp); 2816 2804 tcg_temp_free(tmp); 2817 2805 } 2818 2806 2807 + static void translate_xsr_mask(DisasContext *dc, const OpcodeArg arg[], 2808 + const uint32_t par[]) 2809 + { 2810 + TCGv_i32 tmp = tcg_temp_new_i32(); 2811 + 2812 + tcg_gen_mov_i32(tmp, arg[0].in); 2813 + tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); 2814 + tcg_gen_andi_i32(cpu_SR[par[0]], tmp, par[2]); 2815 + tcg_temp_free(tmp); 2816 + } 2817 + 2818 + static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[], 2819 + const uint32_t par[]) 2820 + { 2821 + #ifndef CONFIG_USER_ONLY 2822 + TCGv_i32 tmp = tcg_temp_new_i32(); 2823 + 2824 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2825 + gen_io_start(); 2826 + } 2827 + 2828 + gen_helper_update_ccount(cpu_env); 2829 + tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); 2830 + gen_helper_wsr_ccount(cpu_env, arg[0].in); 2831 + tcg_gen_mov_i32(arg[0].out, tmp); 2832 + tcg_temp_free(tmp); 2833 + 2834 + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { 2835 + gen_io_end(); 2836 + } 2837 + #endif 2838 + } 2839 + 2840 + #define gen_translate_xsr(name) \ 2841 + static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \ 2842 + const uint32_t par[]) \ 2843 + { \ 2844 + TCGv_i32 tmp = tcg_temp_new_i32(); \ 2845 + \ 2846 + tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \ 2847 + translate_wsr_##name(dc, arg, par); \ 2848 + tcg_gen_mov_i32(arg[0].out, tmp); \ 2849 + tcg_temp_free(tmp); \ 2850 + } 2851 + 2852 + gen_translate_xsr(acchi) 2853 + gen_translate_xsr(ccompare) 2854 + gen_translate_xsr(dbreaka) 2855 + gen_translate_xsr(dbreakc) 2856 + gen_translate_xsr(ibreaka) 2857 + gen_translate_xsr(ibreakenable) 2858 + gen_translate_xsr(icount) 2859 + gen_translate_xsr(memctl) 2860 + gen_translate_xsr(mpuenb) 2861 + gen_translate_xsr(ps) 2862 + gen_translate_xsr(rasid) 2863 + gen_translate_xsr(sar) 2864 + gen_translate_xsr(windowbase) 2865 + gen_translate_xsr(windowstart) 2866 + 2867 + #undef gen_translate_xsr 2868 + 2819 2869 static const XtensaOpcodeOps core_ops[] = { 2820 2870 { 2821 2871 .name = "abs", ··· 3097 3147 .name = "clrb_expstate", 3098 3148 .translate = translate_clrb_expstate, 3099 3149 }, { 3150 + .name = "clrex", 3151 + .translate = translate_clrex, 3152 + }, { 3100 3153 .name = "const16", 3101 3154 .translate = translate_const16, 3102 3155 }, { ··· 3107 3160 .translate = translate_dcache, 3108 3161 .op_flags = XTENSA_OP_PRIVILEGED, 3109 3162 }, { 3163 + .name = "dhi.b", 3164 + .translate = translate_nop, 3165 + }, { 3110 3166 .name = "dhu", 3111 3167 .translate = translate_dcache, 3112 3168 .op_flags = XTENSA_OP_PRIVILEGED, ··· 3114 3170 .name = "dhwb", 3115 3171 .translate = translate_dcache, 3116 3172 }, { 3173 + .name = "dhwb.b", 3174 + .translate = translate_nop, 3175 + }, { 3117 3176 .name = "dhwbi", 3118 3177 .translate = translate_dcache, 3178 + }, { 3179 + .name = "dhwbi.b", 3180 + .translate = translate_nop, 3119 3181 }, { 3120 3182 .name = "dii", 3121 3183 .translate = translate_nop, ··· 3133 3195 .translate = translate_nop, 3134 3196 .op_flags = XTENSA_OP_PRIVILEGED, 3135 3197 }, { 3198 + .name = "diwbui.p", 3199 + .translate = translate_diwbuip, 3200 + .op_flags = XTENSA_OP_PRIVILEGED, 3201 + }, { 3136 3202 .name = "dpfl", 3137 3203 .translate = translate_dcache, 3138 3204 .op_flags = XTENSA_OP_PRIVILEGED, 3139 3205 }, { 3206 + .name = "dpfm.b", 3207 + .translate = translate_nop, 3208 + }, { 3209 + .name = "dpfm.bf", 3210 + .translate = translate_nop, 3211 + }, { 3140 3212 .name = "dpfr", 3141 3213 .translate = translate_nop, 3142 3214 }, { 3215 + .name = "dpfr.b", 3216 + .translate = translate_nop, 3217 + }, { 3218 + .name = "dpfr.bf", 3219 + .translate = translate_nop, 3220 + }, { 3143 3221 .name = "dpfro", 3144 3222 .translate = translate_nop, 3145 3223 }, { 3146 3224 .name = "dpfw", 3225 + .translate = translate_nop, 3226 + }, { 3227 + .name = "dpfw.b", 3228 + .translate = translate_nop, 3229 + }, { 3230 + .name = "dpfw.bf", 3147 3231 .translate = translate_nop, 3148 3232 }, { 3149 3233 .name = "dpfwo", ··· 3170 3254 }, { 3171 3255 .name = "extw", 3172 3256 .translate = translate_memw, 3257 + }, { 3258 + .name = "getex", 3259 + .translate = translate_getex, 3173 3260 }, { 3174 3261 .name = "hwwdtlba", 3175 3262 .op_flags = XTENSA_OP_ILL, ··· 3241 3328 .name = "l32e", 3242 3329 .translate = translate_l32e, 3243 3330 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD, 3331 + }, { 3332 + .name = "l32ex", 3333 + .translate = translate_l32ex, 3334 + .op_flags = XTENSA_OP_LOAD, 3244 3335 }, { 3245 3336 .name = (const char * const[]) { 3246 3337 "l32i", "l32i.n", NULL, ··· 3653 3744 .par = (const uint32_t[]){true}, 3654 3745 .op_flags = XTENSA_OP_PRIVILEGED, 3655 3746 }, { 3747 + .name = "pfend.a", 3748 + .translate = translate_nop, 3749 + }, { 3750 + .name = "pfend.o", 3751 + .translate = translate_nop, 3752 + }, { 3753 + .name = "pfnxt.f", 3754 + .translate = translate_nop, 3755 + }, { 3756 + .name = "pfwait.a", 3757 + .translate = translate_nop, 3758 + }, { 3759 + .name = "pfwait.o", 3760 + .translate = translate_nop, 3761 + }, { 3656 3762 .name = "pitlb", 3657 3763 .translate = translate_ptlb, 3658 3764 .par = (const uint32_t[]){false}, 3765 + .op_flags = XTENSA_OP_PRIVILEGED, 3766 + }, { 3767 + .name = "pptlb", 3768 + .translate = translate_pptlb, 3659 3769 .op_flags = XTENSA_OP_PRIVILEGED, 3660 3770 }, { 3661 3771 .name = "quos", ··· 3744 3854 .par = (const uint32_t[]){false, 1}, 3745 3855 .op_flags = XTENSA_OP_PRIVILEGED, 3746 3856 }, { 3857 + .name = "rptlb0", 3858 + .translate = translate_rptlb0, 3859 + .op_flags = XTENSA_OP_PRIVILEGED, 3860 + }, { 3861 + .name = "rptlb1", 3862 + .translate = translate_rptlb1, 3863 + .op_flags = XTENSA_OP_PRIVILEGED, 3864 + }, { 3747 3865 .name = "rotw", 3748 3866 .translate = translate_rotw, 3749 3867 .op_flags = XTENSA_OP_PRIVILEGED | ··· 3759 3877 }, { 3760 3878 .name = "rsr.176", 3761 3879 .translate = translate_rsr, 3762 - .test_ill = test_ill_rsr, 3763 3880 .par = (const uint32_t[]){176}, 3764 3881 .op_flags = XTENSA_OP_PRIVILEGED, 3765 3882 }, { 3766 3883 .name = "rsr.208", 3767 3884 .translate = translate_rsr, 3768 - .test_ill = test_ill_rsr, 3769 3885 .par = (const uint32_t[]){208}, 3770 3886 .op_flags = XTENSA_OP_PRIVILEGED, 3771 3887 }, { 3772 3888 .name = "rsr.acchi", 3773 3889 .translate = translate_rsr, 3774 - .test_ill = test_ill_rsr, 3775 - .par = (const uint32_t[]){ACCHI}, 3890 + .test_ill = test_ill_sr, 3891 + .par = (const uint32_t[]){ 3892 + ACCHI, 3893 + XTENSA_OPTION_MAC16, 3894 + }, 3776 3895 }, { 3777 3896 .name = "rsr.acclo", 3778 3897 .translate = translate_rsr, 3779 - .test_ill = test_ill_rsr, 3780 - .par = (const uint32_t[]){ACCLO}, 3898 + .test_ill = test_ill_sr, 3899 + .par = (const uint32_t[]){ 3900 + ACCLO, 3901 + XTENSA_OPTION_MAC16, 3902 + }, 3781 3903 }, { 3782 3904 .name = "rsr.atomctl", 3783 3905 .translate = translate_rsr, 3784 - .test_ill = test_ill_rsr, 3785 - .par = (const uint32_t[]){ATOMCTL}, 3906 + .test_ill = test_ill_sr, 3907 + .par = (const uint32_t[]){ 3908 + ATOMCTL, 3909 + XTENSA_OPTION_ATOMCTL, 3910 + }, 3786 3911 .op_flags = XTENSA_OP_PRIVILEGED, 3787 3912 }, { 3788 3913 .name = "rsr.br", 3789 3914 .translate = translate_rsr, 3790 - .test_ill = test_ill_rsr, 3791 - .par = (const uint32_t[]){BR}, 3915 + .test_ill = test_ill_sr, 3916 + .par = (const uint32_t[]){ 3917 + BR, 3918 + XTENSA_OPTION_BOOLEAN, 3919 + }, 3920 + }, { 3921 + .name = "rsr.cacheadrdis", 3922 + .translate = translate_rsr, 3923 + .test_ill = test_ill_sr, 3924 + .par = (const uint32_t[]){ 3925 + CACHEADRDIS, 3926 + XTENSA_OPTION_MPU, 3927 + }, 3928 + .op_flags = XTENSA_OP_PRIVILEGED, 3792 3929 }, { 3793 3930 .name = "rsr.cacheattr", 3794 3931 .translate = translate_rsr, 3795 - .test_ill = test_ill_rsr, 3796 - .par = (const uint32_t[]){CACHEATTR}, 3932 + .test_ill = test_ill_sr, 3933 + .par = (const uint32_t[]){ 3934 + CACHEATTR, 3935 + XTENSA_OPTION_CACHEATTR, 3936 + }, 3797 3937 .op_flags = XTENSA_OP_PRIVILEGED, 3798 3938 }, { 3799 3939 .name = "rsr.ccompare0", 3800 3940 .translate = translate_rsr, 3801 - .test_ill = test_ill_rsr, 3802 - .par = (const uint32_t[]){CCOMPARE}, 3941 + .test_ill = test_ill_ccompare, 3942 + .par = (const uint32_t[]){ 3943 + CCOMPARE, 3944 + XTENSA_OPTION_TIMER_INTERRUPT, 3945 + }, 3803 3946 .op_flags = XTENSA_OP_PRIVILEGED, 3804 3947 }, { 3805 3948 .name = "rsr.ccompare1", 3806 3949 .translate = translate_rsr, 3807 - .test_ill = test_ill_rsr, 3808 - .par = (const uint32_t[]){CCOMPARE + 1}, 3950 + .test_ill = test_ill_ccompare, 3951 + .par = (const uint32_t[]){ 3952 + CCOMPARE + 1, 3953 + XTENSA_OPTION_TIMER_INTERRUPT, 3954 + }, 3809 3955 .op_flags = XTENSA_OP_PRIVILEGED, 3810 3956 }, { 3811 3957 .name = "rsr.ccompare2", 3812 3958 .translate = translate_rsr, 3813 - .test_ill = test_ill_rsr, 3814 - .par = (const uint32_t[]){CCOMPARE + 2}, 3959 + .test_ill = test_ill_ccompare, 3960 + .par = (const uint32_t[]){ 3961 + CCOMPARE + 2, 3962 + XTENSA_OPTION_TIMER_INTERRUPT, 3963 + }, 3815 3964 .op_flags = XTENSA_OP_PRIVILEGED, 3816 3965 }, { 3817 3966 .name = "rsr.ccount", 3818 - .translate = translate_rsr, 3819 - .test_ill = test_ill_rsr, 3820 - .par = (const uint32_t[]){CCOUNT}, 3967 + .translate = translate_rsr_ccount, 3968 + .test_ill = test_ill_sr, 3969 + .par = (const uint32_t[]){ 3970 + CCOUNT, 3971 + XTENSA_OPTION_TIMER_INTERRUPT, 3972 + }, 3821 3973 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 3822 3974 }, { 3823 3975 .name = "rsr.configid0", 3824 3976 .translate = translate_rsr, 3825 - .test_ill = test_ill_rsr, 3826 3977 .par = (const uint32_t[]){CONFIGID0}, 3827 3978 .op_flags = XTENSA_OP_PRIVILEGED, 3828 3979 }, { 3829 3980 .name = "rsr.configid1", 3830 3981 .translate = translate_rsr, 3831 - .test_ill = test_ill_rsr, 3832 3982 .par = (const uint32_t[]){CONFIGID1}, 3833 3983 .op_flags = XTENSA_OP_PRIVILEGED, 3834 3984 }, { 3835 3985 .name = "rsr.cpenable", 3836 3986 .translate = translate_rsr, 3837 - .test_ill = test_ill_rsr, 3838 - .par = (const uint32_t[]){CPENABLE}, 3987 + .test_ill = test_ill_sr, 3988 + .par = (const uint32_t[]){ 3989 + CPENABLE, 3990 + XTENSA_OPTION_COPROCESSOR, 3991 + }, 3839 3992 .op_flags = XTENSA_OP_PRIVILEGED, 3840 3993 }, { 3841 3994 .name = "rsr.dbreaka0", 3842 3995 .translate = translate_rsr, 3843 - .test_ill = test_ill_rsr, 3844 - .par = (const uint32_t[]){DBREAKA}, 3996 + .test_ill = test_ill_dbreak, 3997 + .par = (const uint32_t[]){ 3998 + DBREAKA, 3999 + XTENSA_OPTION_DEBUG, 4000 + }, 3845 4001 .op_flags = XTENSA_OP_PRIVILEGED, 3846 4002 }, { 3847 4003 .name = "rsr.dbreaka1", 3848 4004 .translate = translate_rsr, 3849 - .test_ill = test_ill_rsr, 3850 - .par = (const uint32_t[]){DBREAKA + 1}, 4005 + .test_ill = test_ill_dbreak, 4006 + .par = (const uint32_t[]){ 4007 + DBREAKA + 1, 4008 + XTENSA_OPTION_DEBUG, 4009 + }, 3851 4010 .op_flags = XTENSA_OP_PRIVILEGED, 3852 4011 }, { 3853 4012 .name = "rsr.dbreakc0", 3854 4013 .translate = translate_rsr, 3855 - .test_ill = test_ill_rsr, 3856 - .par = (const uint32_t[]){DBREAKC}, 4014 + .test_ill = test_ill_dbreak, 4015 + .par = (const uint32_t[]){ 4016 + DBREAKC, 4017 + XTENSA_OPTION_DEBUG, 4018 + }, 3857 4019 .op_flags = XTENSA_OP_PRIVILEGED, 3858 4020 }, { 3859 4021 .name = "rsr.dbreakc1", 3860 4022 .translate = translate_rsr, 3861 - .test_ill = test_ill_rsr, 3862 - .par = (const uint32_t[]){DBREAKC + 1}, 4023 + .test_ill = test_ill_dbreak, 4024 + .par = (const uint32_t[]){ 4025 + DBREAKC + 1, 4026 + XTENSA_OPTION_DEBUG, 4027 + }, 3863 4028 .op_flags = XTENSA_OP_PRIVILEGED, 3864 4029 }, { 3865 4030 .name = "rsr.ddr", 3866 4031 .translate = translate_rsr, 3867 - .test_ill = test_ill_rsr, 3868 - .par = (const uint32_t[]){DDR}, 4032 + .test_ill = test_ill_sr, 4033 + .par = (const uint32_t[]){ 4034 + DDR, 4035 + XTENSA_OPTION_DEBUG, 4036 + }, 3869 4037 .op_flags = XTENSA_OP_PRIVILEGED, 3870 4038 }, { 3871 4039 .name = "rsr.debugcause", 3872 4040 .translate = translate_rsr, 3873 - .test_ill = test_ill_rsr, 3874 - .par = (const uint32_t[]){DEBUGCAUSE}, 4041 + .test_ill = test_ill_sr, 4042 + .par = (const uint32_t[]){ 4043 + DEBUGCAUSE, 4044 + XTENSA_OPTION_DEBUG, 4045 + }, 3875 4046 .op_flags = XTENSA_OP_PRIVILEGED, 3876 4047 }, { 3877 4048 .name = "rsr.depc", 3878 4049 .translate = translate_rsr, 3879 - .test_ill = test_ill_rsr, 3880 - .par = (const uint32_t[]){DEPC}, 4050 + .test_ill = test_ill_sr, 4051 + .par = (const uint32_t[]){ 4052 + DEPC, 4053 + XTENSA_OPTION_EXCEPTION, 4054 + }, 3881 4055 .op_flags = XTENSA_OP_PRIVILEGED, 3882 4056 }, { 3883 4057 .name = "rsr.dtlbcfg", 3884 4058 .translate = translate_rsr, 3885 - .test_ill = test_ill_rsr, 3886 - .par = (const uint32_t[]){DTLBCFG}, 4059 + .test_ill = test_ill_sr, 4060 + .par = (const uint32_t[]){ 4061 + DTLBCFG, 4062 + XTENSA_OPTION_MMU, 4063 + }, 3887 4064 .op_flags = XTENSA_OP_PRIVILEGED, 3888 4065 }, { 3889 4066 .name = "rsr.epc1", 3890 4067 .translate = translate_rsr, 3891 - .test_ill = test_ill_rsr, 3892 - .par = (const uint32_t[]){EPC1}, 4068 + .test_ill = test_ill_sr, 4069 + .par = (const uint32_t[]){ 4070 + EPC1, 4071 + XTENSA_OPTION_EXCEPTION, 4072 + }, 3893 4073 .op_flags = XTENSA_OP_PRIVILEGED, 3894 4074 }, { 3895 4075 .name = "rsr.epc2", 3896 4076 .translate = translate_rsr, 3897 - .test_ill = test_ill_rsr, 3898 - .par = (const uint32_t[]){EPC1 + 1}, 4077 + .test_ill = test_ill_hpi, 4078 + .par = (const uint32_t[]){ 4079 + EPC1 + 1, 4080 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4081 + }, 3899 4082 .op_flags = XTENSA_OP_PRIVILEGED, 3900 4083 }, { 3901 4084 .name = "rsr.epc3", 3902 4085 .translate = translate_rsr, 3903 - .test_ill = test_ill_rsr, 3904 - .par = (const uint32_t[]){EPC1 + 2}, 4086 + .test_ill = test_ill_hpi, 4087 + .par = (const uint32_t[]){ 4088 + EPC1 + 2, 4089 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4090 + }, 3905 4091 .op_flags = XTENSA_OP_PRIVILEGED, 3906 4092 }, { 3907 4093 .name = "rsr.epc4", 3908 4094 .translate = translate_rsr, 3909 - .test_ill = test_ill_rsr, 3910 - .par = (const uint32_t[]){EPC1 + 3}, 4095 + .test_ill = test_ill_hpi, 4096 + .par = (const uint32_t[]){ 4097 + EPC1 + 3, 4098 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4099 + }, 3911 4100 .op_flags = XTENSA_OP_PRIVILEGED, 3912 4101 }, { 3913 4102 .name = "rsr.epc5", 3914 4103 .translate = translate_rsr, 3915 - .test_ill = test_ill_rsr, 3916 - .par = (const uint32_t[]){EPC1 + 4}, 4104 + .test_ill = test_ill_hpi, 4105 + .par = (const uint32_t[]){ 4106 + EPC1 + 4, 4107 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4108 + }, 3917 4109 .op_flags = XTENSA_OP_PRIVILEGED, 3918 4110 }, { 3919 4111 .name = "rsr.epc6", 3920 4112 .translate = translate_rsr, 3921 - .test_ill = test_ill_rsr, 3922 - .par = (const uint32_t[]){EPC1 + 5}, 4113 + .test_ill = test_ill_hpi, 4114 + .par = (const uint32_t[]){ 4115 + EPC1 + 5, 4116 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4117 + }, 3923 4118 .op_flags = XTENSA_OP_PRIVILEGED, 3924 4119 }, { 3925 4120 .name = "rsr.epc7", 3926 4121 .translate = translate_rsr, 3927 - .test_ill = test_ill_rsr, 3928 - .par = (const uint32_t[]){EPC1 + 6}, 4122 + .test_ill = test_ill_hpi, 4123 + .par = (const uint32_t[]){ 4124 + EPC1 + 6, 4125 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4126 + }, 3929 4127 .op_flags = XTENSA_OP_PRIVILEGED, 3930 4128 }, { 3931 4129 .name = "rsr.eps2", 3932 4130 .translate = translate_rsr, 3933 - .test_ill = test_ill_rsr, 3934 - .par = (const uint32_t[]){EPS2}, 4131 + .test_ill = test_ill_hpi, 4132 + .par = (const uint32_t[]){ 4133 + EPS2, 4134 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4135 + }, 3935 4136 .op_flags = XTENSA_OP_PRIVILEGED, 3936 4137 }, { 3937 4138 .name = "rsr.eps3", 3938 4139 .translate = translate_rsr, 3939 - .test_ill = test_ill_rsr, 3940 - .par = (const uint32_t[]){EPS2 + 1}, 4140 + .test_ill = test_ill_hpi, 4141 + .par = (const uint32_t[]){ 4142 + EPS2 + 1, 4143 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4144 + }, 3941 4145 .op_flags = XTENSA_OP_PRIVILEGED, 3942 4146 }, { 3943 4147 .name = "rsr.eps4", 3944 4148 .translate = translate_rsr, 3945 - .test_ill = test_ill_rsr, 3946 - .par = (const uint32_t[]){EPS2 + 2}, 4149 + .test_ill = test_ill_hpi, 4150 + .par = (const uint32_t[]){ 4151 + EPS2 + 2, 4152 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4153 + }, 3947 4154 .op_flags = XTENSA_OP_PRIVILEGED, 3948 4155 }, { 3949 4156 .name = "rsr.eps5", 3950 4157 .translate = translate_rsr, 3951 - .test_ill = test_ill_rsr, 3952 - .par = (const uint32_t[]){EPS2 + 3}, 4158 + .test_ill = test_ill_hpi, 4159 + .par = (const uint32_t[]){ 4160 + EPS2 + 3, 4161 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4162 + }, 3953 4163 .op_flags = XTENSA_OP_PRIVILEGED, 3954 4164 }, { 3955 4165 .name = "rsr.eps6", 3956 4166 .translate = translate_rsr, 3957 - .test_ill = test_ill_rsr, 3958 - .par = (const uint32_t[]){EPS2 + 4}, 4167 + .test_ill = test_ill_hpi, 4168 + .par = (const uint32_t[]){ 4169 + EPS2 + 4, 4170 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4171 + }, 3959 4172 .op_flags = XTENSA_OP_PRIVILEGED, 3960 4173 }, { 3961 4174 .name = "rsr.eps7", 3962 4175 .translate = translate_rsr, 3963 - .test_ill = test_ill_rsr, 3964 - .par = (const uint32_t[]){EPS2 + 5}, 4176 + .test_ill = test_ill_hpi, 4177 + .par = (const uint32_t[]){ 4178 + EPS2 + 5, 4179 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4180 + }, 4181 + .op_flags = XTENSA_OP_PRIVILEGED, 4182 + }, { 4183 + .name = "rsr.eraccess", 4184 + .translate = translate_rsr, 4185 + .par = (const uint32_t[]){ERACCESS}, 3965 4186 .op_flags = XTENSA_OP_PRIVILEGED, 3966 4187 }, { 3967 4188 .name = "rsr.exccause", 3968 4189 .translate = translate_rsr, 3969 - .test_ill = test_ill_rsr, 3970 - .par = (const uint32_t[]){EXCCAUSE}, 4190 + .test_ill = test_ill_sr, 4191 + .par = (const uint32_t[]){ 4192 + EXCCAUSE, 4193 + XTENSA_OPTION_EXCEPTION, 4194 + }, 3971 4195 .op_flags = XTENSA_OP_PRIVILEGED, 3972 4196 }, { 3973 4197 .name = "rsr.excsave1", 3974 4198 .translate = translate_rsr, 3975 - .test_ill = test_ill_rsr, 3976 - .par = (const uint32_t[]){EXCSAVE1}, 4199 + .test_ill = test_ill_sr, 4200 + .par = (const uint32_t[]){ 4201 + EXCSAVE1, 4202 + XTENSA_OPTION_EXCEPTION, 4203 + }, 3977 4204 .op_flags = XTENSA_OP_PRIVILEGED, 3978 4205 }, { 3979 4206 .name = "rsr.excsave2", 3980 4207 .translate = translate_rsr, 3981 - .test_ill = test_ill_rsr, 3982 - .par = (const uint32_t[]){EXCSAVE1 + 1}, 4208 + .test_ill = test_ill_hpi, 4209 + .par = (const uint32_t[]){ 4210 + EXCSAVE1 + 1, 4211 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4212 + }, 3983 4213 .op_flags = XTENSA_OP_PRIVILEGED, 3984 4214 }, { 3985 4215 .name = "rsr.excsave3", 3986 4216 .translate = translate_rsr, 3987 - .test_ill = test_ill_rsr, 3988 - .par = (const uint32_t[]){EXCSAVE1 + 2}, 4217 + .test_ill = test_ill_hpi, 4218 + .par = (const uint32_t[]){ 4219 + EXCSAVE1 + 2, 4220 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4221 + }, 3989 4222 .op_flags = XTENSA_OP_PRIVILEGED, 3990 4223 }, { 3991 4224 .name = "rsr.excsave4", 3992 4225 .translate = translate_rsr, 3993 - .test_ill = test_ill_rsr, 3994 - .par = (const uint32_t[]){EXCSAVE1 + 3}, 4226 + .test_ill = test_ill_hpi, 4227 + .par = (const uint32_t[]){ 4228 + EXCSAVE1 + 3, 4229 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4230 + }, 3995 4231 .op_flags = XTENSA_OP_PRIVILEGED, 3996 4232 }, { 3997 4233 .name = "rsr.excsave5", 3998 4234 .translate = translate_rsr, 3999 - .test_ill = test_ill_rsr, 4000 - .par = (const uint32_t[]){EXCSAVE1 + 4}, 4235 + .test_ill = test_ill_hpi, 4236 + .par = (const uint32_t[]){ 4237 + EXCSAVE1 + 4, 4238 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4239 + }, 4001 4240 .op_flags = XTENSA_OP_PRIVILEGED, 4002 4241 }, { 4003 4242 .name = "rsr.excsave6", 4004 4243 .translate = translate_rsr, 4005 - .test_ill = test_ill_rsr, 4006 - .par = (const uint32_t[]){EXCSAVE1 + 5}, 4244 + .test_ill = test_ill_hpi, 4245 + .par = (const uint32_t[]){ 4246 + EXCSAVE1 + 5, 4247 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4248 + }, 4007 4249 .op_flags = XTENSA_OP_PRIVILEGED, 4008 4250 }, { 4009 4251 .name = "rsr.excsave7", 4010 4252 .translate = translate_rsr, 4011 - .test_ill = test_ill_rsr, 4012 - .par = (const uint32_t[]){EXCSAVE1 + 6}, 4253 + .test_ill = test_ill_hpi, 4254 + .par = (const uint32_t[]){ 4255 + EXCSAVE1 + 6, 4256 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4257 + }, 4013 4258 .op_flags = XTENSA_OP_PRIVILEGED, 4014 4259 }, { 4015 4260 .name = "rsr.excvaddr", 4016 4261 .translate = translate_rsr, 4017 - .test_ill = test_ill_rsr, 4018 - .par = (const uint32_t[]){EXCVADDR}, 4262 + .test_ill = test_ill_sr, 4263 + .par = (const uint32_t[]){ 4264 + EXCVADDR, 4265 + XTENSA_OPTION_EXCEPTION, 4266 + }, 4019 4267 .op_flags = XTENSA_OP_PRIVILEGED, 4020 4268 }, { 4021 4269 .name = "rsr.ibreaka0", 4022 4270 .translate = translate_rsr, 4023 - .test_ill = test_ill_rsr, 4024 - .par = (const uint32_t[]){IBREAKA}, 4271 + .test_ill = test_ill_ibreak, 4272 + .par = (const uint32_t[]){ 4273 + IBREAKA, 4274 + XTENSA_OPTION_DEBUG, 4275 + }, 4025 4276 .op_flags = XTENSA_OP_PRIVILEGED, 4026 4277 }, { 4027 4278 .name = "rsr.ibreaka1", 4028 4279 .translate = translate_rsr, 4029 - .test_ill = test_ill_rsr, 4030 - .par = (const uint32_t[]){IBREAKA + 1}, 4280 + .test_ill = test_ill_ibreak, 4281 + .par = (const uint32_t[]){ 4282 + IBREAKA + 1, 4283 + XTENSA_OPTION_DEBUG, 4284 + }, 4031 4285 .op_flags = XTENSA_OP_PRIVILEGED, 4032 4286 }, { 4033 4287 .name = "rsr.ibreakenable", 4034 4288 .translate = translate_rsr, 4035 - .test_ill = test_ill_rsr, 4036 - .par = (const uint32_t[]){IBREAKENABLE}, 4289 + .test_ill = test_ill_sr, 4290 + .par = (const uint32_t[]){ 4291 + IBREAKENABLE, 4292 + XTENSA_OPTION_DEBUG, 4293 + }, 4037 4294 .op_flags = XTENSA_OP_PRIVILEGED, 4038 4295 }, { 4039 4296 .name = "rsr.icount", 4040 4297 .translate = translate_rsr, 4041 - .test_ill = test_ill_rsr, 4042 - .par = (const uint32_t[]){ICOUNT}, 4298 + .test_ill = test_ill_sr, 4299 + .par = (const uint32_t[]){ 4300 + ICOUNT, 4301 + XTENSA_OPTION_DEBUG, 4302 + }, 4043 4303 .op_flags = XTENSA_OP_PRIVILEGED, 4044 4304 }, { 4045 4305 .name = "rsr.icountlevel", 4046 4306 .translate = translate_rsr, 4047 - .test_ill = test_ill_rsr, 4048 - .par = (const uint32_t[]){ICOUNTLEVEL}, 4307 + .test_ill = test_ill_sr, 4308 + .par = (const uint32_t[]){ 4309 + ICOUNTLEVEL, 4310 + XTENSA_OPTION_DEBUG, 4311 + }, 4049 4312 .op_flags = XTENSA_OP_PRIVILEGED, 4050 4313 }, { 4051 4314 .name = "rsr.intclear", 4052 4315 .translate = translate_rsr, 4053 - .test_ill = test_ill_rsr, 4054 - .par = (const uint32_t[]){INTCLEAR}, 4316 + .test_ill = test_ill_sr, 4317 + .par = (const uint32_t[]){ 4318 + INTCLEAR, 4319 + XTENSA_OPTION_INTERRUPT, 4320 + }, 4055 4321 .op_flags = XTENSA_OP_PRIVILEGED, 4056 4322 }, { 4057 4323 .name = "rsr.intenable", 4058 4324 .translate = translate_rsr, 4059 - .test_ill = test_ill_rsr, 4060 - .par = (const uint32_t[]){INTENABLE}, 4325 + .test_ill = test_ill_sr, 4326 + .par = (const uint32_t[]){ 4327 + INTENABLE, 4328 + XTENSA_OPTION_INTERRUPT, 4329 + }, 4061 4330 .op_flags = XTENSA_OP_PRIVILEGED, 4062 4331 }, { 4063 4332 .name = "rsr.interrupt", 4064 - .translate = translate_rsr, 4065 - .test_ill = test_ill_rsr, 4066 - .par = (const uint32_t[]){INTSET}, 4333 + .translate = translate_rsr_ccount, 4334 + .test_ill = test_ill_sr, 4335 + .par = (const uint32_t[]){ 4336 + INTSET, 4337 + XTENSA_OPTION_INTERRUPT, 4338 + }, 4067 4339 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4068 4340 }, { 4069 4341 .name = "rsr.intset", 4070 - .translate = translate_rsr, 4071 - .test_ill = test_ill_rsr, 4072 - .par = (const uint32_t[]){INTSET}, 4342 + .translate = translate_rsr_ccount, 4343 + .test_ill = test_ill_sr, 4344 + .par = (const uint32_t[]){ 4345 + INTSET, 4346 + XTENSA_OPTION_INTERRUPT, 4347 + }, 4073 4348 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4074 4349 }, { 4075 4350 .name = "rsr.itlbcfg", 4076 4351 .translate = translate_rsr, 4077 - .test_ill = test_ill_rsr, 4078 - .par = (const uint32_t[]){ITLBCFG}, 4352 + .test_ill = test_ill_sr, 4353 + .par = (const uint32_t[]){ 4354 + ITLBCFG, 4355 + XTENSA_OPTION_MMU, 4356 + }, 4079 4357 .op_flags = XTENSA_OP_PRIVILEGED, 4080 4358 }, { 4081 4359 .name = "rsr.lbeg", 4082 4360 .translate = translate_rsr, 4083 - .test_ill = test_ill_rsr, 4084 - .par = (const uint32_t[]){LBEG}, 4361 + .test_ill = test_ill_sr, 4362 + .par = (const uint32_t[]){ 4363 + LBEG, 4364 + XTENSA_OPTION_LOOP, 4365 + }, 4085 4366 }, { 4086 4367 .name = "rsr.lcount", 4087 4368 .translate = translate_rsr, 4088 - .test_ill = test_ill_rsr, 4089 - .par = (const uint32_t[]){LCOUNT}, 4369 + .test_ill = test_ill_sr, 4370 + .par = (const uint32_t[]){ 4371 + LCOUNT, 4372 + XTENSA_OPTION_LOOP, 4373 + }, 4090 4374 }, { 4091 4375 .name = "rsr.lend", 4092 4376 .translate = translate_rsr, 4093 - .test_ill = test_ill_rsr, 4094 - .par = (const uint32_t[]){LEND}, 4377 + .test_ill = test_ill_sr, 4378 + .par = (const uint32_t[]){ 4379 + LEND, 4380 + XTENSA_OPTION_LOOP, 4381 + }, 4095 4382 }, { 4096 4383 .name = "rsr.litbase", 4097 4384 .translate = translate_rsr, 4098 - .test_ill = test_ill_rsr, 4099 - .par = (const uint32_t[]){LITBASE}, 4385 + .test_ill = test_ill_sr, 4386 + .par = (const uint32_t[]){ 4387 + LITBASE, 4388 + XTENSA_OPTION_EXTENDED_L32R, 4389 + }, 4100 4390 }, { 4101 4391 .name = "rsr.m0", 4102 4392 .translate = translate_rsr, 4103 - .test_ill = test_ill_rsr, 4104 - .par = (const uint32_t[]){MR}, 4393 + .test_ill = test_ill_sr, 4394 + .par = (const uint32_t[]){ 4395 + MR, 4396 + XTENSA_OPTION_MAC16, 4397 + }, 4105 4398 }, { 4106 4399 .name = "rsr.m1", 4107 4400 .translate = translate_rsr, 4108 - .test_ill = test_ill_rsr, 4109 - .par = (const uint32_t[]){MR + 1}, 4401 + .test_ill = test_ill_sr, 4402 + .par = (const uint32_t[]){ 4403 + MR + 1, 4404 + XTENSA_OPTION_MAC16, 4405 + }, 4110 4406 }, { 4111 4407 .name = "rsr.m2", 4112 4408 .translate = translate_rsr, 4113 - .test_ill = test_ill_rsr, 4114 - .par = (const uint32_t[]){MR + 2}, 4409 + .test_ill = test_ill_sr, 4410 + .par = (const uint32_t[]){ 4411 + MR + 2, 4412 + XTENSA_OPTION_MAC16, 4413 + }, 4115 4414 }, { 4116 4415 .name = "rsr.m3", 4117 4416 .translate = translate_rsr, 4118 - .test_ill = test_ill_rsr, 4119 - .par = (const uint32_t[]){MR + 3}, 4417 + .test_ill = test_ill_sr, 4418 + .par = (const uint32_t[]){ 4419 + MR + 3, 4420 + XTENSA_OPTION_MAC16, 4421 + }, 4120 4422 }, { 4121 4423 .name = "rsr.memctl", 4122 4424 .translate = translate_rsr, 4123 - .test_ill = test_ill_rsr, 4124 4425 .par = (const uint32_t[]){MEMCTL}, 4125 4426 .op_flags = XTENSA_OP_PRIVILEGED, 4126 4427 }, { 4428 + .name = "rsr.mecr", 4429 + .translate = translate_rsr, 4430 + .test_ill = test_ill_sr, 4431 + .par = (const uint32_t[]){ 4432 + MECR, 4433 + XTENSA_OPTION_MEMORY_ECC_PARITY, 4434 + }, 4435 + .op_flags = XTENSA_OP_PRIVILEGED, 4436 + }, { 4437 + .name = "rsr.mepc", 4438 + .translate = translate_rsr, 4439 + .test_ill = test_ill_sr, 4440 + .par = (const uint32_t[]){ 4441 + MEPC, 4442 + XTENSA_OPTION_MEMORY_ECC_PARITY, 4443 + }, 4444 + .op_flags = XTENSA_OP_PRIVILEGED, 4445 + }, { 4446 + .name = "rsr.meps", 4447 + .translate = translate_rsr, 4448 + .test_ill = test_ill_sr, 4449 + .par = (const uint32_t[]){ 4450 + MEPS, 4451 + XTENSA_OPTION_MEMORY_ECC_PARITY, 4452 + }, 4453 + .op_flags = XTENSA_OP_PRIVILEGED, 4454 + }, { 4455 + .name = "rsr.mesave", 4456 + .translate = translate_rsr, 4457 + .test_ill = test_ill_sr, 4458 + .par = (const uint32_t[]){ 4459 + MESAVE, 4460 + XTENSA_OPTION_MEMORY_ECC_PARITY, 4461 + }, 4462 + .op_flags = XTENSA_OP_PRIVILEGED, 4463 + }, { 4464 + .name = "rsr.mesr", 4465 + .translate = translate_rsr, 4466 + .test_ill = test_ill_sr, 4467 + .par = (const uint32_t[]){ 4468 + MESR, 4469 + XTENSA_OPTION_MEMORY_ECC_PARITY, 4470 + }, 4471 + .op_flags = XTENSA_OP_PRIVILEGED, 4472 + }, { 4473 + .name = "rsr.mevaddr", 4474 + .translate = translate_rsr, 4475 + .test_ill = test_ill_sr, 4476 + .par = (const uint32_t[]){ 4477 + MESR, 4478 + XTENSA_OPTION_MEMORY_ECC_PARITY, 4479 + }, 4480 + .op_flags = XTENSA_OP_PRIVILEGED, 4481 + }, { 4127 4482 .name = "rsr.misc0", 4128 4483 .translate = translate_rsr, 4129 - .test_ill = test_ill_rsr, 4130 - .par = (const uint32_t[]){MISC}, 4484 + .test_ill = test_ill_sr, 4485 + .par = (const uint32_t[]){ 4486 + MISC, 4487 + XTENSA_OPTION_MISC_SR, 4488 + }, 4131 4489 .op_flags = XTENSA_OP_PRIVILEGED, 4132 4490 }, { 4133 4491 .name = "rsr.misc1", 4134 4492 .translate = translate_rsr, 4135 - .test_ill = test_ill_rsr, 4136 - .par = (const uint32_t[]){MISC + 1}, 4493 + .test_ill = test_ill_sr, 4494 + .par = (const uint32_t[]){ 4495 + MISC + 1, 4496 + XTENSA_OPTION_MISC_SR, 4497 + }, 4137 4498 .op_flags = XTENSA_OP_PRIVILEGED, 4138 4499 }, { 4139 4500 .name = "rsr.misc2", 4140 4501 .translate = translate_rsr, 4141 - .test_ill = test_ill_rsr, 4142 - .par = (const uint32_t[]){MISC + 2}, 4502 + .test_ill = test_ill_sr, 4503 + .par = (const uint32_t[]){ 4504 + MISC + 2, 4505 + XTENSA_OPTION_MISC_SR, 4506 + }, 4143 4507 .op_flags = XTENSA_OP_PRIVILEGED, 4144 4508 }, { 4145 4509 .name = "rsr.misc3", 4146 4510 .translate = translate_rsr, 4147 - .test_ill = test_ill_rsr, 4148 - .par = (const uint32_t[]){MISC + 3}, 4511 + .test_ill = test_ill_sr, 4512 + .par = (const uint32_t[]){ 4513 + MISC + 3, 4514 + XTENSA_OPTION_MISC_SR, 4515 + }, 4516 + .op_flags = XTENSA_OP_PRIVILEGED, 4517 + }, { 4518 + .name = "rsr.mpucfg", 4519 + .translate = translate_rsr, 4520 + .test_ill = test_ill_sr, 4521 + .par = (const uint32_t[]){ 4522 + MPUCFG, 4523 + XTENSA_OPTION_MPU, 4524 + }, 4525 + .op_flags = XTENSA_OP_PRIVILEGED, 4526 + }, { 4527 + .name = "rsr.mpuenb", 4528 + .translate = translate_rsr, 4529 + .test_ill = test_ill_sr, 4530 + .par = (const uint32_t[]){ 4531 + MPUENB, 4532 + XTENSA_OPTION_MPU, 4533 + }, 4149 4534 .op_flags = XTENSA_OP_PRIVILEGED, 4150 4535 }, { 4151 4536 .name = "rsr.prefctl", 4152 4537 .translate = translate_rsr, 4153 - .test_ill = test_ill_rsr, 4154 4538 .par = (const uint32_t[]){PREFCTL}, 4155 4539 }, { 4156 4540 .name = "rsr.prid", 4157 4541 .translate = translate_rsr, 4158 - .test_ill = test_ill_rsr, 4159 - .par = (const uint32_t[]){PRID}, 4542 + .test_ill = test_ill_sr, 4543 + .par = (const uint32_t[]){ 4544 + PRID, 4545 + XTENSA_OPTION_PROCESSOR_ID, 4546 + }, 4160 4547 .op_flags = XTENSA_OP_PRIVILEGED, 4161 4548 }, { 4162 4549 .name = "rsr.ps", 4163 4550 .translate = translate_rsr, 4164 - .test_ill = test_ill_rsr, 4165 - .par = (const uint32_t[]){PS}, 4551 + .test_ill = test_ill_sr, 4552 + .par = (const uint32_t[]){ 4553 + PS, 4554 + XTENSA_OPTION_EXCEPTION, 4555 + }, 4166 4556 .op_flags = XTENSA_OP_PRIVILEGED, 4167 4557 }, { 4168 4558 .name = "rsr.ptevaddr", 4169 - .translate = translate_rsr, 4170 - .test_ill = test_ill_rsr, 4171 - .par = (const uint32_t[]){PTEVADDR}, 4559 + .translate = translate_rsr_ptevaddr, 4560 + .test_ill = test_ill_sr, 4561 + .par = (const uint32_t[]){ 4562 + PTEVADDR, 4563 + XTENSA_OPTION_MMU, 4564 + }, 4172 4565 .op_flags = XTENSA_OP_PRIVILEGED, 4173 4566 }, { 4174 4567 .name = "rsr.rasid", 4175 4568 .translate = translate_rsr, 4176 - .test_ill = test_ill_rsr, 4177 - .par = (const uint32_t[]){RASID}, 4569 + .test_ill = test_ill_sr, 4570 + .par = (const uint32_t[]){ 4571 + RASID, 4572 + XTENSA_OPTION_MMU, 4573 + }, 4178 4574 .op_flags = XTENSA_OP_PRIVILEGED, 4179 4575 }, { 4180 4576 .name = "rsr.sar", 4181 4577 .translate = translate_rsr, 4182 - .test_ill = test_ill_rsr, 4183 4578 .par = (const uint32_t[]){SAR}, 4184 4579 }, { 4185 4580 .name = "rsr.scompare1", 4186 4581 .translate = translate_rsr, 4187 - .test_ill = test_ill_rsr, 4188 - .par = (const uint32_t[]){SCOMPARE1}, 4582 + .test_ill = test_ill_sr, 4583 + .par = (const uint32_t[]){ 4584 + SCOMPARE1, 4585 + XTENSA_OPTION_CONDITIONAL_STORE, 4586 + }, 4189 4587 }, { 4190 4588 .name = "rsr.vecbase", 4191 4589 .translate = translate_rsr, 4192 - .test_ill = test_ill_rsr, 4193 - .par = (const uint32_t[]){VECBASE}, 4590 + .test_ill = test_ill_sr, 4591 + .par = (const uint32_t[]){ 4592 + VECBASE, 4593 + XTENSA_OPTION_RELOCATABLE_VECTOR, 4594 + }, 4194 4595 .op_flags = XTENSA_OP_PRIVILEGED, 4195 4596 }, { 4196 4597 .name = "rsr.windowbase", 4197 4598 .translate = translate_rsr, 4198 - .test_ill = test_ill_rsr, 4199 - .par = (const uint32_t[]){WINDOW_BASE}, 4599 + .test_ill = test_ill_sr, 4600 + .par = (const uint32_t[]){ 4601 + WINDOW_BASE, 4602 + XTENSA_OPTION_WINDOWED_REGISTER, 4603 + }, 4200 4604 .op_flags = XTENSA_OP_PRIVILEGED, 4201 4605 }, { 4202 4606 .name = "rsr.windowstart", 4203 4607 .translate = translate_rsr, 4204 - .test_ill = test_ill_rsr, 4205 - .par = (const uint32_t[]){WINDOW_START}, 4608 + .test_ill = test_ill_sr, 4609 + .par = (const uint32_t[]){ 4610 + WINDOW_START, 4611 + XTENSA_OPTION_WINDOWED_REGISTER, 4612 + }, 4206 4613 .op_flags = XTENSA_OP_PRIVILEGED, 4207 4614 }, { 4208 4615 .name = "rsync", ··· 4238 4645 .name = "s32e", 4239 4646 .translate = translate_s32e, 4240 4647 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE, 4648 + }, { 4649 + .name = "s32ex", 4650 + .translate = translate_s32ex, 4651 + .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE, 4241 4652 }, { 4242 4653 .name = (const char * const[]) { 4243 4654 "s32i", "s32i.n", "s32nb", NULL, ··· 4363 4774 .par = (const uint32_t[]){false}, 4364 4775 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4365 4776 }, { 4777 + .name = "wptlb", 4778 + .translate = translate_wptlb, 4779 + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4780 + }, { 4366 4781 .name = "wrmsk_expstate", 4367 4782 .translate = translate_wrmsk_expstate, 4368 4783 }, { 4369 4784 .name = "wsr.176", 4370 - .translate = translate_wsr, 4371 - .test_ill = test_ill_wsr, 4372 - .par = (const uint32_t[]){176}, 4373 - .op_flags = XTENSA_OP_PRIVILEGED, 4785 + .op_flags = XTENSA_OP_ILL, 4374 4786 }, { 4375 4787 .name = "wsr.208", 4376 - .translate = translate_wsr, 4377 - .test_ill = test_ill_wsr, 4378 - .par = (const uint32_t[]){208}, 4379 - .op_flags = XTENSA_OP_PRIVILEGED, 4788 + .op_flags = XTENSA_OP_ILL, 4380 4789 }, { 4381 4790 .name = "wsr.acchi", 4382 - .translate = translate_wsr, 4383 - .test_ill = test_ill_wsr, 4384 - .par = (const uint32_t[]){ACCHI}, 4791 + .translate = translate_wsr_acchi, 4792 + .test_ill = test_ill_sr, 4793 + .par = (const uint32_t[]){ 4794 + ACCHI, 4795 + XTENSA_OPTION_MAC16, 4796 + }, 4385 4797 }, { 4386 4798 .name = "wsr.acclo", 4387 4799 .translate = translate_wsr, 4388 - .test_ill = test_ill_wsr, 4389 - .par = (const uint32_t[]){ACCLO}, 4800 + .test_ill = test_ill_sr, 4801 + .par = (const uint32_t[]){ 4802 + ACCLO, 4803 + XTENSA_OPTION_MAC16, 4804 + }, 4390 4805 }, { 4391 4806 .name = "wsr.atomctl", 4392 - .translate = translate_wsr, 4393 - .test_ill = test_ill_wsr, 4394 - .par = (const uint32_t[]){ATOMCTL}, 4807 + .translate = translate_wsr_mask, 4808 + .test_ill = test_ill_sr, 4809 + .par = (const uint32_t[]){ 4810 + ATOMCTL, 4811 + XTENSA_OPTION_ATOMCTL, 4812 + 0x3f, 4813 + }, 4395 4814 .op_flags = XTENSA_OP_PRIVILEGED, 4396 4815 }, { 4397 4816 .name = "wsr.br", 4398 - .translate = translate_wsr, 4399 - .test_ill = test_ill_wsr, 4400 - .par = (const uint32_t[]){BR}, 4817 + .translate = translate_wsr_mask, 4818 + .test_ill = test_ill_sr, 4819 + .par = (const uint32_t[]){ 4820 + BR, 4821 + XTENSA_OPTION_BOOLEAN, 4822 + 0xffff, 4823 + }, 4824 + }, { 4825 + .name = "wsr.cacheadrdis", 4826 + .translate = translate_wsr_mask, 4827 + .test_ill = test_ill_sr, 4828 + .par = (const uint32_t[]){ 4829 + CACHEADRDIS, 4830 + XTENSA_OPTION_MPU, 4831 + 0xff, 4832 + }, 4833 + .op_flags = XTENSA_OP_PRIVILEGED, 4401 4834 }, { 4402 4835 .name = "wsr.cacheattr", 4403 4836 .translate = translate_wsr, 4404 - .test_ill = test_ill_wsr, 4405 - .par = (const uint32_t[]){CACHEATTR}, 4837 + .test_ill = test_ill_sr, 4838 + .par = (const uint32_t[]){ 4839 + CACHEATTR, 4840 + XTENSA_OPTION_CACHEATTR, 4841 + }, 4406 4842 .op_flags = XTENSA_OP_PRIVILEGED, 4407 4843 }, { 4408 4844 .name = "wsr.ccompare0", 4409 - .translate = translate_wsr, 4410 - .test_ill = test_ill_wsr, 4411 - .par = (const uint32_t[]){CCOMPARE}, 4845 + .translate = translate_wsr_ccompare, 4846 + .test_ill = test_ill_ccompare, 4847 + .par = (const uint32_t[]){ 4848 + CCOMPARE, 4849 + XTENSA_OPTION_TIMER_INTERRUPT, 4850 + }, 4412 4851 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4413 4852 }, { 4414 4853 .name = "wsr.ccompare1", 4415 - .translate = translate_wsr, 4416 - .test_ill = test_ill_wsr, 4417 - .par = (const uint32_t[]){CCOMPARE + 1}, 4854 + .translate = translate_wsr_ccompare, 4855 + .test_ill = test_ill_ccompare, 4856 + .par = (const uint32_t[]){ 4857 + CCOMPARE + 1, 4858 + XTENSA_OPTION_TIMER_INTERRUPT, 4859 + }, 4418 4860 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4419 4861 }, { 4420 4862 .name = "wsr.ccompare2", 4421 - .translate = translate_wsr, 4422 - .test_ill = test_ill_wsr, 4423 - .par = (const uint32_t[]){CCOMPARE + 2}, 4863 + .translate = translate_wsr_ccompare, 4864 + .test_ill = test_ill_ccompare, 4865 + .par = (const uint32_t[]){ 4866 + CCOMPARE + 2, 4867 + XTENSA_OPTION_TIMER_INTERRUPT, 4868 + }, 4424 4869 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4425 4870 }, { 4426 4871 .name = "wsr.ccount", 4427 - .translate = translate_wsr, 4428 - .test_ill = test_ill_wsr, 4429 - .par = (const uint32_t[]){CCOUNT}, 4872 + .translate = translate_wsr_ccount, 4873 + .test_ill = test_ill_sr, 4874 + .par = (const uint32_t[]){ 4875 + CCOUNT, 4876 + XTENSA_OPTION_TIMER_INTERRUPT, 4877 + }, 4430 4878 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4431 4879 }, { 4432 4880 .name = "wsr.configid0", 4433 - .translate = translate_wsr, 4434 - .test_ill = test_ill_wsr, 4435 - .par = (const uint32_t[]){CONFIGID0}, 4436 - .op_flags = XTENSA_OP_PRIVILEGED, 4881 + .op_flags = XTENSA_OP_ILL, 4437 4882 }, { 4438 4883 .name = "wsr.configid1", 4439 - .translate = translate_wsr, 4440 - .test_ill = test_ill_wsr, 4441 - .par = (const uint32_t[]){CONFIGID1}, 4442 - .op_flags = XTENSA_OP_PRIVILEGED, 4884 + .op_flags = XTENSA_OP_ILL, 4443 4885 }, { 4444 4886 .name = "wsr.cpenable", 4445 - .translate = translate_wsr, 4446 - .test_ill = test_ill_wsr, 4447 - .par = (const uint32_t[]){CPENABLE}, 4887 + .translate = translate_wsr_mask, 4888 + .test_ill = test_ill_sr, 4889 + .par = (const uint32_t[]){ 4890 + CPENABLE, 4891 + XTENSA_OPTION_COPROCESSOR, 4892 + 0xff, 4893 + }, 4448 4894 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4449 4895 }, { 4450 4896 .name = "wsr.dbreaka0", 4451 - .translate = translate_wsr, 4452 - .test_ill = test_ill_wsr, 4453 - .par = (const uint32_t[]){DBREAKA}, 4897 + .translate = translate_wsr_dbreaka, 4898 + .test_ill = test_ill_dbreak, 4899 + .par = (const uint32_t[]){ 4900 + DBREAKA, 4901 + XTENSA_OPTION_DEBUG, 4902 + }, 4454 4903 .op_flags = XTENSA_OP_PRIVILEGED, 4455 4904 }, { 4456 4905 .name = "wsr.dbreaka1", 4457 - .translate = translate_wsr, 4458 - .test_ill = test_ill_wsr, 4459 - .par = (const uint32_t[]){DBREAKA + 1}, 4906 + .translate = translate_wsr_dbreaka, 4907 + .test_ill = test_ill_dbreak, 4908 + .par = (const uint32_t[]){ 4909 + DBREAKA + 1, 4910 + XTENSA_OPTION_DEBUG, 4911 + }, 4460 4912 .op_flags = XTENSA_OP_PRIVILEGED, 4461 4913 }, { 4462 4914 .name = "wsr.dbreakc0", 4463 - .translate = translate_wsr, 4464 - .test_ill = test_ill_wsr, 4465 - .par = (const uint32_t[]){DBREAKC}, 4915 + .translate = translate_wsr_dbreakc, 4916 + .test_ill = test_ill_dbreak, 4917 + .par = (const uint32_t[]){ 4918 + DBREAKC, 4919 + XTENSA_OPTION_DEBUG, 4920 + }, 4466 4921 .op_flags = XTENSA_OP_PRIVILEGED, 4467 4922 }, { 4468 4923 .name = "wsr.dbreakc1", 4469 - .translate = translate_wsr, 4470 - .test_ill = test_ill_wsr, 4471 - .par = (const uint32_t[]){DBREAKC + 1}, 4924 + .translate = translate_wsr_dbreakc, 4925 + .test_ill = test_ill_dbreak, 4926 + .par = (const uint32_t[]){ 4927 + DBREAKC + 1, 4928 + XTENSA_OPTION_DEBUG, 4929 + }, 4472 4930 .op_flags = XTENSA_OP_PRIVILEGED, 4473 4931 }, { 4474 4932 .name = "wsr.ddr", 4475 4933 .translate = translate_wsr, 4476 - .test_ill = test_ill_wsr, 4477 - .par = (const uint32_t[]){DDR}, 4934 + .test_ill = test_ill_sr, 4935 + .par = (const uint32_t[]){ 4936 + DDR, 4937 + XTENSA_OPTION_DEBUG, 4938 + }, 4478 4939 .op_flags = XTENSA_OP_PRIVILEGED, 4479 4940 }, { 4480 4941 .name = "wsr.debugcause", 4481 - .translate = translate_wsr, 4482 - .test_ill = test_ill_wsr, 4483 - .par = (const uint32_t[]){DEBUGCAUSE}, 4484 - .op_flags = XTENSA_OP_PRIVILEGED, 4942 + .op_flags = XTENSA_OP_ILL, 4485 4943 }, { 4486 4944 .name = "wsr.depc", 4487 4945 .translate = translate_wsr, 4488 - .test_ill = test_ill_wsr, 4489 - .par = (const uint32_t[]){DEPC}, 4946 + .test_ill = test_ill_sr, 4947 + .par = (const uint32_t[]){ 4948 + DEPC, 4949 + XTENSA_OPTION_EXCEPTION, 4950 + }, 4490 4951 .op_flags = XTENSA_OP_PRIVILEGED, 4491 4952 }, { 4492 4953 .name = "wsr.dtlbcfg", 4493 - .translate = translate_wsr, 4494 - .test_ill = test_ill_wsr, 4495 - .par = (const uint32_t[]){DTLBCFG}, 4954 + .translate = translate_wsr_mask, 4955 + .test_ill = test_ill_sr, 4956 + .par = (const uint32_t[]){ 4957 + DTLBCFG, 4958 + XTENSA_OPTION_MMU, 4959 + 0x01130000, 4960 + }, 4496 4961 .op_flags = XTENSA_OP_PRIVILEGED, 4497 4962 }, { 4498 4963 .name = "wsr.epc1", 4499 4964 .translate = translate_wsr, 4500 - .test_ill = test_ill_wsr, 4501 - .par = (const uint32_t[]){EPC1}, 4965 + .test_ill = test_ill_sr, 4966 + .par = (const uint32_t[]){ 4967 + EPC1, 4968 + XTENSA_OPTION_EXCEPTION, 4969 + }, 4502 4970 .op_flags = XTENSA_OP_PRIVILEGED, 4503 4971 }, { 4504 4972 .name = "wsr.epc2", 4505 4973 .translate = translate_wsr, 4506 - .test_ill = test_ill_wsr, 4507 - .par = (const uint32_t[]){EPC1 + 1}, 4974 + .test_ill = test_ill_hpi, 4975 + .par = (const uint32_t[]){ 4976 + EPC1 + 1, 4977 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4978 + }, 4508 4979 .op_flags = XTENSA_OP_PRIVILEGED, 4509 4980 }, { 4510 4981 .name = "wsr.epc3", 4511 4982 .translate = translate_wsr, 4512 - .test_ill = test_ill_wsr, 4513 - .par = (const uint32_t[]){EPC1 + 2}, 4983 + .test_ill = test_ill_hpi, 4984 + .par = (const uint32_t[]){ 4985 + EPC1 + 2, 4986 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4987 + }, 4514 4988 .op_flags = XTENSA_OP_PRIVILEGED, 4515 4989 }, { 4516 4990 .name = "wsr.epc4", 4517 4991 .translate = translate_wsr, 4518 - .test_ill = test_ill_wsr, 4519 - .par = (const uint32_t[]){EPC1 + 3}, 4992 + .test_ill = test_ill_hpi, 4993 + .par = (const uint32_t[]){ 4994 + EPC1 + 3, 4995 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 4996 + }, 4520 4997 .op_flags = XTENSA_OP_PRIVILEGED, 4521 4998 }, { 4522 4999 .name = "wsr.epc5", 4523 5000 .translate = translate_wsr, 4524 - .test_ill = test_ill_wsr, 4525 - .par = (const uint32_t[]){EPC1 + 4}, 5001 + .test_ill = test_ill_hpi, 5002 + .par = (const uint32_t[]){ 5003 + EPC1 + 4, 5004 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5005 + }, 4526 5006 .op_flags = XTENSA_OP_PRIVILEGED, 4527 5007 }, { 4528 5008 .name = "wsr.epc6", 4529 5009 .translate = translate_wsr, 4530 - .test_ill = test_ill_wsr, 4531 - .par = (const uint32_t[]){EPC1 + 5}, 5010 + .test_ill = test_ill_hpi, 5011 + .par = (const uint32_t[]){ 5012 + EPC1 + 5, 5013 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5014 + }, 4532 5015 .op_flags = XTENSA_OP_PRIVILEGED, 4533 5016 }, { 4534 5017 .name = "wsr.epc7", 4535 5018 .translate = translate_wsr, 4536 - .test_ill = test_ill_wsr, 4537 - .par = (const uint32_t[]){EPC1 + 6}, 5019 + .test_ill = test_ill_hpi, 5020 + .par = (const uint32_t[]){ 5021 + EPC1 + 6, 5022 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5023 + }, 4538 5024 .op_flags = XTENSA_OP_PRIVILEGED, 4539 5025 }, { 4540 5026 .name = "wsr.eps2", 4541 5027 .translate = translate_wsr, 4542 - .test_ill = test_ill_wsr, 4543 - .par = (const uint32_t[]){EPS2}, 5028 + .test_ill = test_ill_hpi, 5029 + .par = (const uint32_t[]){ 5030 + EPS2, 5031 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5032 + }, 4544 5033 .op_flags = XTENSA_OP_PRIVILEGED, 4545 5034 }, { 4546 5035 .name = "wsr.eps3", 4547 5036 .translate = translate_wsr, 4548 - .test_ill = test_ill_wsr, 4549 - .par = (const uint32_t[]){EPS2 + 1}, 5037 + .test_ill = test_ill_hpi, 5038 + .par = (const uint32_t[]){ 5039 + EPS2 + 1, 5040 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5041 + }, 4550 5042 .op_flags = XTENSA_OP_PRIVILEGED, 4551 5043 }, { 4552 5044 .name = "wsr.eps4", 4553 5045 .translate = translate_wsr, 4554 - .test_ill = test_ill_wsr, 4555 - .par = (const uint32_t[]){EPS2 + 2}, 5046 + .test_ill = test_ill_hpi, 5047 + .par = (const uint32_t[]){ 5048 + EPS2 + 2, 5049 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5050 + }, 4556 5051 .op_flags = XTENSA_OP_PRIVILEGED, 4557 5052 }, { 4558 5053 .name = "wsr.eps5", 4559 5054 .translate = translate_wsr, 4560 - .test_ill = test_ill_wsr, 4561 - .par = (const uint32_t[]){EPS2 + 3}, 5055 + .test_ill = test_ill_hpi, 5056 + .par = (const uint32_t[]){ 5057 + EPS2 + 3, 5058 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5059 + }, 4562 5060 .op_flags = XTENSA_OP_PRIVILEGED, 4563 5061 }, { 4564 5062 .name = "wsr.eps6", 4565 5063 .translate = translate_wsr, 4566 - .test_ill = test_ill_wsr, 4567 - .par = (const uint32_t[]){EPS2 + 4}, 5064 + .test_ill = test_ill_hpi, 5065 + .par = (const uint32_t[]){ 5066 + EPS2 + 4, 5067 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5068 + }, 4568 5069 .op_flags = XTENSA_OP_PRIVILEGED, 4569 5070 }, { 4570 5071 .name = "wsr.eps7", 4571 5072 .translate = translate_wsr, 4572 - .test_ill = test_ill_wsr, 4573 - .par = (const uint32_t[]){EPS2 + 5}, 5073 + .test_ill = test_ill_hpi, 5074 + .par = (const uint32_t[]){ 5075 + EPS2 + 5, 5076 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5077 + }, 5078 + .op_flags = XTENSA_OP_PRIVILEGED, 5079 + }, { 5080 + .name = "wsr.eraccess", 5081 + .translate = translate_wsr_mask, 5082 + .par = (const uint32_t[]){ 5083 + ERACCESS, 5084 + 0, 5085 + 0xffff, 5086 + }, 4574 5087 .op_flags = XTENSA_OP_PRIVILEGED, 4575 5088 }, { 4576 5089 .name = "wsr.exccause", 4577 5090 .translate = translate_wsr, 4578 - .test_ill = test_ill_wsr, 4579 - .par = (const uint32_t[]){EXCCAUSE}, 5091 + .test_ill = test_ill_sr, 5092 + .par = (const uint32_t[]){ 5093 + EXCCAUSE, 5094 + XTENSA_OPTION_EXCEPTION, 5095 + }, 4580 5096 .op_flags = XTENSA_OP_PRIVILEGED, 4581 5097 }, { 4582 5098 .name = "wsr.excsave1", 4583 5099 .translate = translate_wsr, 4584 - .test_ill = test_ill_wsr, 4585 - .par = (const uint32_t[]){EXCSAVE1}, 5100 + .test_ill = test_ill_sr, 5101 + .par = (const uint32_t[]){ 5102 + EXCSAVE1, 5103 + XTENSA_OPTION_EXCEPTION, 5104 + }, 4586 5105 .op_flags = XTENSA_OP_PRIVILEGED, 4587 5106 }, { 4588 5107 .name = "wsr.excsave2", 4589 5108 .translate = translate_wsr, 4590 - .test_ill = test_ill_wsr, 4591 - .par = (const uint32_t[]){EXCSAVE1 + 1}, 5109 + .test_ill = test_ill_hpi, 5110 + .par = (const uint32_t[]){ 5111 + EXCSAVE1 + 1, 5112 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5113 + }, 4592 5114 .op_flags = XTENSA_OP_PRIVILEGED, 4593 5115 }, { 4594 5116 .name = "wsr.excsave3", 4595 5117 .translate = translate_wsr, 4596 - .test_ill = test_ill_wsr, 4597 - .par = (const uint32_t[]){EXCSAVE1 + 2}, 5118 + .test_ill = test_ill_hpi, 5119 + .par = (const uint32_t[]){ 5120 + EXCSAVE1 + 2, 5121 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5122 + }, 4598 5123 .op_flags = XTENSA_OP_PRIVILEGED, 4599 5124 }, { 4600 5125 .name = "wsr.excsave4", 4601 5126 .translate = translate_wsr, 4602 - .test_ill = test_ill_wsr, 4603 - .par = (const uint32_t[]){EXCSAVE1 + 3}, 5127 + .test_ill = test_ill_hpi, 5128 + .par = (const uint32_t[]){ 5129 + EXCSAVE1 + 3, 5130 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5131 + }, 4604 5132 .op_flags = XTENSA_OP_PRIVILEGED, 4605 5133 }, { 4606 5134 .name = "wsr.excsave5", 4607 5135 .translate = translate_wsr, 4608 - .test_ill = test_ill_wsr, 4609 - .par = (const uint32_t[]){EXCSAVE1 + 4}, 5136 + .test_ill = test_ill_hpi, 5137 + .par = (const uint32_t[]){ 5138 + EXCSAVE1 + 4, 5139 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5140 + }, 4610 5141 .op_flags = XTENSA_OP_PRIVILEGED, 4611 5142 }, { 4612 5143 .name = "wsr.excsave6", 4613 5144 .translate = translate_wsr, 4614 - .test_ill = test_ill_wsr, 4615 - .par = (const uint32_t[]){EXCSAVE1 + 5}, 5145 + .test_ill = test_ill_hpi, 5146 + .par = (const uint32_t[]){ 5147 + EXCSAVE1 + 5, 5148 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5149 + }, 4616 5150 .op_flags = XTENSA_OP_PRIVILEGED, 4617 5151 }, { 4618 5152 .name = "wsr.excsave7", 4619 5153 .translate = translate_wsr, 4620 - .test_ill = test_ill_wsr, 4621 - .par = (const uint32_t[]){EXCSAVE1 + 6}, 5154 + .test_ill = test_ill_hpi, 5155 + .par = (const uint32_t[]){ 5156 + EXCSAVE1 + 6, 5157 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5158 + }, 4622 5159 .op_flags = XTENSA_OP_PRIVILEGED, 4623 5160 }, { 4624 5161 .name = "wsr.excvaddr", 4625 5162 .translate = translate_wsr, 4626 - .test_ill = test_ill_wsr, 4627 - .par = (const uint32_t[]){EXCVADDR}, 5163 + .test_ill = test_ill_sr, 5164 + .par = (const uint32_t[]){ 5165 + EXCVADDR, 5166 + XTENSA_OPTION_EXCEPTION, 5167 + }, 4628 5168 .op_flags = XTENSA_OP_PRIVILEGED, 4629 5169 }, { 4630 5170 .name = "wsr.ibreaka0", 4631 - .translate = translate_wsr, 4632 - .test_ill = test_ill_wsr, 4633 - .par = (const uint32_t[]){IBREAKA}, 5171 + .translate = translate_wsr_ibreaka, 5172 + .test_ill = test_ill_ibreak, 5173 + .par = (const uint32_t[]){ 5174 + IBREAKA, 5175 + XTENSA_OPTION_DEBUG, 5176 + }, 4634 5177 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4635 5178 }, { 4636 5179 .name = "wsr.ibreaka1", 4637 - .translate = translate_wsr, 4638 - .test_ill = test_ill_wsr, 4639 - .par = (const uint32_t[]){IBREAKA + 1}, 5180 + .translate = translate_wsr_ibreaka, 5181 + .test_ill = test_ill_ibreak, 5182 + .par = (const uint32_t[]){ 5183 + IBREAKA + 1, 5184 + XTENSA_OPTION_DEBUG, 5185 + }, 4640 5186 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4641 5187 }, { 4642 5188 .name = "wsr.ibreakenable", 4643 - .translate = translate_wsr, 4644 - .test_ill = test_ill_wsr, 4645 - .par = (const uint32_t[]){IBREAKENABLE}, 5189 + .translate = translate_wsr_ibreakenable, 5190 + .test_ill = test_ill_sr, 5191 + .par = (const uint32_t[]){ 5192 + IBREAKENABLE, 5193 + XTENSA_OPTION_DEBUG, 5194 + }, 4646 5195 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4647 5196 }, { 4648 5197 .name = "wsr.icount", 4649 - .translate = translate_wsr, 4650 - .test_ill = test_ill_wsr, 4651 - .par = (const uint32_t[]){ICOUNT}, 5198 + .translate = translate_wsr_icount, 5199 + .test_ill = test_ill_sr, 5200 + .par = (const uint32_t[]){ 5201 + ICOUNT, 5202 + XTENSA_OPTION_DEBUG, 5203 + }, 4652 5204 .op_flags = XTENSA_OP_PRIVILEGED, 4653 5205 }, { 4654 5206 .name = "wsr.icountlevel", 4655 - .translate = translate_wsr, 4656 - .test_ill = test_ill_wsr, 4657 - .par = (const uint32_t[]){ICOUNTLEVEL}, 5207 + .translate = translate_wsr_mask, 5208 + .test_ill = test_ill_sr, 5209 + .par = (const uint32_t[]){ 5210 + ICOUNTLEVEL, 5211 + XTENSA_OPTION_DEBUG, 5212 + 0xf, 5213 + }, 4658 5214 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4659 5215 }, { 4660 5216 .name = "wsr.intclear", 4661 - .translate = translate_wsr, 4662 - .test_ill = test_ill_wsr, 4663 - .par = (const uint32_t[]){INTCLEAR}, 5217 + .translate = translate_wsr_intclear, 5218 + .test_ill = test_ill_sr, 5219 + .par = (const uint32_t[]){ 5220 + INTCLEAR, 5221 + XTENSA_OPTION_INTERRUPT, 5222 + }, 4664 5223 .op_flags = 4665 5224 XTENSA_OP_PRIVILEGED | 4666 5225 XTENSA_OP_EXIT_TB_0 | ··· 4668 5227 }, { 4669 5228 .name = "wsr.intenable", 4670 5229 .translate = translate_wsr, 4671 - .test_ill = test_ill_wsr, 4672 - .par = (const uint32_t[]){INTENABLE}, 5230 + .test_ill = test_ill_sr, 5231 + .par = (const uint32_t[]){ 5232 + INTENABLE, 5233 + XTENSA_OPTION_INTERRUPT, 5234 + }, 4673 5235 .op_flags = 4674 5236 XTENSA_OP_PRIVILEGED | 4675 5237 XTENSA_OP_EXIT_TB_0 | ··· 4677 5239 }, { 4678 5240 .name = "wsr.interrupt", 4679 5241 .translate = translate_wsr, 4680 - .test_ill = test_ill_wsr, 4681 - .par = (const uint32_t[]){INTSET}, 5242 + .test_ill = test_ill_sr, 5243 + .par = (const uint32_t[]){ 5244 + INTSET, 5245 + XTENSA_OPTION_INTERRUPT, 5246 + }, 4682 5247 .op_flags = 4683 5248 XTENSA_OP_PRIVILEGED | 4684 5249 XTENSA_OP_EXIT_TB_0 | 4685 5250 XTENSA_OP_CHECK_INTERRUPTS, 4686 5251 }, { 4687 5252 .name = "wsr.intset", 4688 - .translate = translate_wsr, 4689 - .test_ill = test_ill_wsr, 4690 - .par = (const uint32_t[]){INTSET}, 5253 + .translate = translate_wsr_intset, 5254 + .test_ill = test_ill_sr, 5255 + .par = (const uint32_t[]){ 5256 + INTSET, 5257 + XTENSA_OPTION_INTERRUPT, 5258 + }, 4691 5259 .op_flags = 4692 5260 XTENSA_OP_PRIVILEGED | 4693 5261 XTENSA_OP_EXIT_TB_0 | 4694 5262 XTENSA_OP_CHECK_INTERRUPTS, 4695 5263 }, { 4696 5264 .name = "wsr.itlbcfg", 4697 - .translate = translate_wsr, 4698 - .test_ill = test_ill_wsr, 4699 - .par = (const uint32_t[]){ITLBCFG}, 5265 + .translate = translate_wsr_mask, 5266 + .test_ill = test_ill_sr, 5267 + .par = (const uint32_t[]){ 5268 + ITLBCFG, 5269 + XTENSA_OPTION_MMU, 5270 + 0x01130000, 5271 + }, 4700 5272 .op_flags = XTENSA_OP_PRIVILEGED, 4701 5273 }, { 4702 5274 .name = "wsr.lbeg", 4703 5275 .translate = translate_wsr, 4704 - .test_ill = test_ill_wsr, 4705 - .par = (const uint32_t[]){LBEG}, 5276 + .test_ill = test_ill_sr, 5277 + .par = (const uint32_t[]){ 5278 + LBEG, 5279 + XTENSA_OPTION_LOOP, 5280 + }, 4706 5281 .op_flags = XTENSA_OP_EXIT_TB_M1, 4707 5282 }, { 4708 5283 .name = "wsr.lcount", 4709 5284 .translate = translate_wsr, 4710 - .test_ill = test_ill_wsr, 4711 - .par = (const uint32_t[]){LCOUNT}, 5285 + .test_ill = test_ill_sr, 5286 + .par = (const uint32_t[]){ 5287 + LCOUNT, 5288 + XTENSA_OPTION_LOOP, 5289 + }, 4712 5290 }, { 4713 5291 .name = "wsr.lend", 4714 5292 .translate = translate_wsr, 4715 - .test_ill = test_ill_wsr, 4716 - .par = (const uint32_t[]){LEND}, 5293 + .test_ill = test_ill_sr, 5294 + .par = (const uint32_t[]){ 5295 + LEND, 5296 + XTENSA_OPTION_LOOP, 5297 + }, 4717 5298 .op_flags = XTENSA_OP_EXIT_TB_M1, 4718 5299 }, { 4719 5300 .name = "wsr.litbase", 4720 - .translate = translate_wsr, 4721 - .test_ill = test_ill_wsr, 4722 - .par = (const uint32_t[]){LITBASE}, 5301 + .translate = translate_wsr_mask, 5302 + .test_ill = test_ill_sr, 5303 + .par = (const uint32_t[]){ 5304 + LITBASE, 5305 + XTENSA_OPTION_EXTENDED_L32R, 5306 + 0xfffff001, 5307 + }, 4723 5308 .op_flags = XTENSA_OP_EXIT_TB_M1, 4724 5309 }, { 4725 5310 .name = "wsr.m0", 4726 5311 .translate = translate_wsr, 4727 - .test_ill = test_ill_wsr, 4728 - .par = (const uint32_t[]){MR}, 5312 + .test_ill = test_ill_sr, 5313 + .par = (const uint32_t[]){ 5314 + MR, 5315 + XTENSA_OPTION_MAC16, 5316 + }, 4729 5317 }, { 4730 5318 .name = "wsr.m1", 4731 5319 .translate = translate_wsr, 4732 - .test_ill = test_ill_wsr, 4733 - .par = (const uint32_t[]){MR + 1}, 5320 + .test_ill = test_ill_sr, 5321 + .par = (const uint32_t[]){ 5322 + MR + 1, 5323 + XTENSA_OPTION_MAC16, 5324 + }, 4734 5325 }, { 4735 5326 .name = "wsr.m2", 4736 5327 .translate = translate_wsr, 4737 - .test_ill = test_ill_wsr, 4738 - .par = (const uint32_t[]){MR + 2}, 5328 + .test_ill = test_ill_sr, 5329 + .par = (const uint32_t[]){ 5330 + MR + 2, 5331 + XTENSA_OPTION_MAC16, 5332 + }, 4739 5333 }, { 4740 5334 .name = "wsr.m3", 4741 5335 .translate = translate_wsr, 4742 - .test_ill = test_ill_wsr, 4743 - .par = (const uint32_t[]){MR + 3}, 5336 + .test_ill = test_ill_sr, 5337 + .par = (const uint32_t[]){ 5338 + MR + 3, 5339 + XTENSA_OPTION_MAC16, 5340 + }, 4744 5341 }, { 4745 5342 .name = "wsr.memctl", 4746 - .translate = translate_wsr, 4747 - .test_ill = test_ill_wsr, 5343 + .translate = translate_wsr_memctl, 4748 5344 .par = (const uint32_t[]){MEMCTL}, 4749 5345 .op_flags = XTENSA_OP_PRIVILEGED, 4750 5346 }, { 5347 + .name = "wsr.mecr", 5348 + .translate = translate_wsr, 5349 + .test_ill = test_ill_sr, 5350 + .par = (const uint32_t[]){ 5351 + MECR, 5352 + XTENSA_OPTION_MEMORY_ECC_PARITY, 5353 + }, 5354 + .op_flags = XTENSA_OP_PRIVILEGED, 5355 + }, { 5356 + .name = "wsr.mepc", 5357 + .translate = translate_wsr, 5358 + .test_ill = test_ill_sr, 5359 + .par = (const uint32_t[]){ 5360 + MEPC, 5361 + XTENSA_OPTION_MEMORY_ECC_PARITY, 5362 + }, 5363 + .op_flags = XTENSA_OP_PRIVILEGED, 5364 + }, { 5365 + .name = "wsr.meps", 5366 + .translate = translate_wsr, 5367 + .test_ill = test_ill_sr, 5368 + .par = (const uint32_t[]){ 5369 + MEPS, 5370 + XTENSA_OPTION_MEMORY_ECC_PARITY, 5371 + }, 5372 + .op_flags = XTENSA_OP_PRIVILEGED, 5373 + }, { 5374 + .name = "wsr.mesave", 5375 + .translate = translate_wsr, 5376 + .test_ill = test_ill_sr, 5377 + .par = (const uint32_t[]){ 5378 + MESAVE, 5379 + XTENSA_OPTION_MEMORY_ECC_PARITY, 5380 + }, 5381 + .op_flags = XTENSA_OP_PRIVILEGED, 5382 + }, { 5383 + .name = "wsr.mesr", 5384 + .translate = translate_wsr, 5385 + .test_ill = test_ill_sr, 5386 + .par = (const uint32_t[]){ 5387 + MESR, 5388 + XTENSA_OPTION_MEMORY_ECC_PARITY, 5389 + }, 5390 + .op_flags = XTENSA_OP_PRIVILEGED, 5391 + }, { 5392 + .name = "wsr.mevaddr", 5393 + .translate = translate_wsr, 5394 + .test_ill = test_ill_sr, 5395 + .par = (const uint32_t[]){ 5396 + MESR, 5397 + XTENSA_OPTION_MEMORY_ECC_PARITY, 5398 + }, 5399 + .op_flags = XTENSA_OP_PRIVILEGED, 5400 + }, { 4751 5401 .name = "wsr.misc0", 4752 5402 .translate = translate_wsr, 4753 - .test_ill = test_ill_wsr, 4754 - .par = (const uint32_t[]){MISC}, 5403 + .test_ill = test_ill_sr, 5404 + .par = (const uint32_t[]){ 5405 + MISC, 5406 + XTENSA_OPTION_MISC_SR, 5407 + }, 4755 5408 .op_flags = XTENSA_OP_PRIVILEGED, 4756 5409 }, { 4757 5410 .name = "wsr.misc1", 4758 5411 .translate = translate_wsr, 4759 - .test_ill = test_ill_wsr, 4760 - .par = (const uint32_t[]){MISC + 1}, 5412 + .test_ill = test_ill_sr, 5413 + .par = (const uint32_t[]){ 5414 + MISC + 1, 5415 + XTENSA_OPTION_MISC_SR, 5416 + }, 4761 5417 .op_flags = XTENSA_OP_PRIVILEGED, 4762 5418 }, { 4763 5419 .name = "wsr.misc2", 4764 5420 .translate = translate_wsr, 4765 - .test_ill = test_ill_wsr, 4766 - .par = (const uint32_t[]){MISC + 2}, 5421 + .test_ill = test_ill_sr, 5422 + .par = (const uint32_t[]){ 5423 + MISC + 2, 5424 + XTENSA_OPTION_MISC_SR, 5425 + }, 4767 5426 .op_flags = XTENSA_OP_PRIVILEGED, 4768 5427 }, { 4769 5428 .name = "wsr.misc3", 4770 5429 .translate = translate_wsr, 4771 - .test_ill = test_ill_wsr, 4772 - .par = (const uint32_t[]){MISC + 3}, 5430 + .test_ill = test_ill_sr, 5431 + .par = (const uint32_t[]){ 5432 + MISC + 3, 5433 + XTENSA_OPTION_MISC_SR, 5434 + }, 4773 5435 .op_flags = XTENSA_OP_PRIVILEGED, 4774 5436 }, { 4775 5437 .name = "wsr.mmid", 4776 5438 .translate = translate_wsr, 4777 - .test_ill = test_ill_wsr, 4778 - .par = (const uint32_t[]){MMID}, 5439 + .test_ill = test_ill_sr, 5440 + .par = (const uint32_t[]){ 5441 + MMID, 5442 + XTENSA_OPTION_TRACE_PORT, 5443 + }, 4779 5444 .op_flags = XTENSA_OP_PRIVILEGED, 4780 5445 }, { 5446 + .name = "wsr.mpuenb", 5447 + .translate = translate_wsr_mpuenb, 5448 + .test_ill = test_ill_sr, 5449 + .par = (const uint32_t[]){ 5450 + MPUENB, 5451 + XTENSA_OPTION_MPU, 5452 + }, 5453 + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5454 + }, { 4781 5455 .name = "wsr.prefctl", 4782 5456 .translate = translate_wsr, 4783 - .test_ill = test_ill_wsr, 4784 5457 .par = (const uint32_t[]){PREFCTL}, 4785 5458 }, { 4786 5459 .name = "wsr.prid", 4787 - .translate = translate_wsr, 4788 - .test_ill = test_ill_wsr, 4789 - .par = (const uint32_t[]){PRID}, 4790 - .op_flags = XTENSA_OP_PRIVILEGED, 5460 + .op_flags = XTENSA_OP_ILL, 4791 5461 }, { 4792 5462 .name = "wsr.ps", 4793 - .translate = translate_wsr, 4794 - .test_ill = test_ill_wsr, 4795 - .par = (const uint32_t[]){PS}, 5463 + .translate = translate_wsr_ps, 5464 + .test_ill = test_ill_sr, 5465 + .par = (const uint32_t[]){ 5466 + PS, 5467 + XTENSA_OPTION_EXCEPTION, 5468 + }, 4796 5469 .op_flags = 4797 5470 XTENSA_OP_PRIVILEGED | 4798 5471 XTENSA_OP_EXIT_TB_M1 | 4799 5472 XTENSA_OP_CHECK_INTERRUPTS, 4800 5473 }, { 4801 5474 .name = "wsr.ptevaddr", 4802 - .translate = translate_wsr, 4803 - .test_ill = test_ill_wsr, 4804 - .par = (const uint32_t[]){PTEVADDR}, 5475 + .translate = translate_wsr_mask, 5476 + .test_ill = test_ill_sr, 5477 + .par = (const uint32_t[]){ 5478 + PTEVADDR, 5479 + XTENSA_OPTION_MMU, 5480 + 0xffc00000, 5481 + }, 4805 5482 .op_flags = XTENSA_OP_PRIVILEGED, 4806 5483 }, { 4807 5484 .name = "wsr.rasid", 4808 - .translate = translate_wsr, 4809 - .test_ill = test_ill_wsr, 4810 - .par = (const uint32_t[]){RASID}, 5485 + .translate = translate_wsr_rasid, 5486 + .test_ill = test_ill_sr, 5487 + .par = (const uint32_t[]){ 5488 + RASID, 5489 + XTENSA_OPTION_MMU, 5490 + }, 4811 5491 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4812 5492 }, { 4813 5493 .name = "wsr.sar", 4814 - .translate = translate_wsr, 4815 - .test_ill = test_ill_wsr, 5494 + .translate = translate_wsr_sar, 4816 5495 .par = (const uint32_t[]){SAR}, 4817 5496 }, { 4818 5497 .name = "wsr.scompare1", 4819 5498 .translate = translate_wsr, 4820 - .test_ill = test_ill_wsr, 4821 - .par = (const uint32_t[]){SCOMPARE1}, 5499 + .test_ill = test_ill_sr, 5500 + .par = (const uint32_t[]){ 5501 + SCOMPARE1, 5502 + XTENSA_OPTION_CONDITIONAL_STORE, 5503 + }, 4822 5504 }, { 4823 5505 .name = "wsr.vecbase", 4824 5506 .translate = translate_wsr, 4825 - .test_ill = test_ill_wsr, 4826 - .par = (const uint32_t[]){VECBASE}, 5507 + .test_ill = test_ill_sr, 5508 + .par = (const uint32_t[]){ 5509 + VECBASE, 5510 + XTENSA_OPTION_RELOCATABLE_VECTOR, 5511 + }, 4827 5512 .op_flags = XTENSA_OP_PRIVILEGED, 4828 5513 }, { 4829 5514 .name = "wsr.windowbase", 4830 - .translate = translate_wsr, 4831 - .test_ill = test_ill_wsr, 4832 - .par = (const uint32_t[]){WINDOW_BASE}, 5515 + .translate = translate_wsr_windowbase, 5516 + .test_ill = test_ill_sr, 5517 + .par = (const uint32_t[]){ 5518 + WINDOW_BASE, 5519 + XTENSA_OPTION_WINDOWED_REGISTER, 5520 + }, 4833 5521 .op_flags = XTENSA_OP_PRIVILEGED | 4834 5522 XTENSA_OP_EXIT_TB_M1 | 4835 5523 XTENSA_OP_SYNC_REGISTER_WINDOW, 4836 5524 }, { 4837 5525 .name = "wsr.windowstart", 4838 - .translate = translate_wsr, 4839 - .test_ill = test_ill_wsr, 4840 - .par = (const uint32_t[]){WINDOW_START}, 5526 + .translate = translate_wsr_windowstart, 5527 + .test_ill = test_ill_sr, 5528 + .par = (const uint32_t[]){ 5529 + WINDOW_START, 5530 + XTENSA_OPTION_WINDOWED_REGISTER, 5531 + }, 4841 5532 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4842 5533 }, { 4843 5534 .name = "wur.expstate", ··· 4845 5536 .par = (const uint32_t[]){EXPSTATE}, 4846 5537 }, { 4847 5538 .name = "wur.fcr", 4848 - .translate = translate_wur, 5539 + .translate = translate_wur_fcr, 4849 5540 .par = (const uint32_t[]){FCR}, 4850 5541 .coprocessor = 0x1, 4851 5542 }, { 4852 5543 .name = "wur.fsr", 4853 - .translate = translate_wur, 5544 + .translate = translate_wur_fsr, 4854 5545 .par = (const uint32_t[]){FSR}, 4855 5546 .coprocessor = 0x1, 4856 5547 }, { ··· 4866 5557 .par = (const uint32_t[]){BOOLEAN_XOR}, 4867 5558 }, { 4868 5559 .name = "xsr.176", 4869 - .translate = translate_xsr, 4870 - .test_ill = test_ill_xsr, 4871 - .par = (const uint32_t[]){176}, 4872 - .op_flags = XTENSA_OP_PRIVILEGED, 5560 + .op_flags = XTENSA_OP_ILL, 4873 5561 }, { 4874 5562 .name = "xsr.208", 4875 - .translate = translate_xsr, 4876 - .test_ill = test_ill_xsr, 4877 - .par = (const uint32_t[]){208}, 4878 - .op_flags = XTENSA_OP_PRIVILEGED, 5563 + .op_flags = XTENSA_OP_ILL, 4879 5564 }, { 4880 5565 .name = "xsr.acchi", 4881 - .translate = translate_xsr, 4882 - .test_ill = test_ill_xsr, 4883 - .par = (const uint32_t[]){ACCHI}, 5566 + .translate = translate_xsr_acchi, 5567 + .test_ill = test_ill_sr, 5568 + .par = (const uint32_t[]){ 5569 + ACCHI, 5570 + XTENSA_OPTION_MAC16, 5571 + }, 4884 5572 }, { 4885 5573 .name = "xsr.acclo", 4886 5574 .translate = translate_xsr, 4887 - .test_ill = test_ill_xsr, 4888 - .par = (const uint32_t[]){ACCLO}, 5575 + .test_ill = test_ill_sr, 5576 + .par = (const uint32_t[]){ 5577 + ACCLO, 5578 + XTENSA_OPTION_MAC16, 5579 + }, 4889 5580 }, { 4890 5581 .name = "xsr.atomctl", 4891 - .translate = translate_xsr, 4892 - .test_ill = test_ill_xsr, 4893 - .par = (const uint32_t[]){ATOMCTL}, 5582 + .translate = translate_xsr_mask, 5583 + .test_ill = test_ill_sr, 5584 + .par = (const uint32_t[]){ 5585 + ATOMCTL, 5586 + XTENSA_OPTION_ATOMCTL, 5587 + 0x3f, 5588 + }, 4894 5589 .op_flags = XTENSA_OP_PRIVILEGED, 4895 5590 }, { 4896 5591 .name = "xsr.br", 4897 - .translate = translate_xsr, 4898 - .test_ill = test_ill_xsr, 4899 - .par = (const uint32_t[]){BR}, 5592 + .translate = translate_xsr_mask, 5593 + .test_ill = test_ill_sr, 5594 + .par = (const uint32_t[]){ 5595 + BR, 5596 + XTENSA_OPTION_BOOLEAN, 5597 + 0xffff, 5598 + }, 5599 + }, { 5600 + .name = "xsr.cacheadrdis", 5601 + .translate = translate_xsr_mask, 5602 + .test_ill = test_ill_sr, 5603 + .par = (const uint32_t[]){ 5604 + CACHEADRDIS, 5605 + XTENSA_OPTION_MPU, 5606 + 0xff, 5607 + }, 5608 + .op_flags = XTENSA_OP_PRIVILEGED, 4900 5609 }, { 4901 5610 .name = "xsr.cacheattr", 4902 5611 .translate = translate_xsr, 4903 - .test_ill = test_ill_xsr, 4904 - .par = (const uint32_t[]){CACHEATTR}, 5612 + .test_ill = test_ill_sr, 5613 + .par = (const uint32_t[]){ 5614 + CACHEATTR, 5615 + XTENSA_OPTION_CACHEATTR, 5616 + }, 4905 5617 .op_flags = XTENSA_OP_PRIVILEGED, 4906 5618 }, { 4907 5619 .name = "xsr.ccompare0", 4908 - .translate = translate_xsr, 4909 - .test_ill = test_ill_xsr, 4910 - .par = (const uint32_t[]){CCOMPARE}, 5620 + .translate = translate_xsr_ccompare, 5621 + .test_ill = test_ill_ccompare, 5622 + .par = (const uint32_t[]){ 5623 + CCOMPARE, 5624 + XTENSA_OPTION_TIMER_INTERRUPT, 5625 + }, 4911 5626 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4912 5627 }, { 4913 5628 .name = "xsr.ccompare1", 4914 - .translate = translate_xsr, 4915 - .test_ill = test_ill_xsr, 4916 - .par = (const uint32_t[]){CCOMPARE + 1}, 5629 + .translate = translate_xsr_ccompare, 5630 + .test_ill = test_ill_ccompare, 5631 + .par = (const uint32_t[]){ 5632 + CCOMPARE + 1, 5633 + XTENSA_OPTION_TIMER_INTERRUPT, 5634 + }, 4917 5635 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4918 5636 }, { 4919 5637 .name = "xsr.ccompare2", 4920 - .translate = translate_xsr, 4921 - .test_ill = test_ill_xsr, 4922 - .par = (const uint32_t[]){CCOMPARE + 2}, 5638 + .translate = translate_xsr_ccompare, 5639 + .test_ill = test_ill_ccompare, 5640 + .par = (const uint32_t[]){ 5641 + CCOMPARE + 2, 5642 + XTENSA_OPTION_TIMER_INTERRUPT, 5643 + }, 4923 5644 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4924 5645 }, { 4925 5646 .name = "xsr.ccount", 4926 - .translate = translate_xsr, 4927 - .test_ill = test_ill_xsr, 4928 - .par = (const uint32_t[]){CCOUNT}, 5647 + .translate = translate_xsr_ccount, 5648 + .test_ill = test_ill_sr, 5649 + .par = (const uint32_t[]){ 5650 + CCOUNT, 5651 + XTENSA_OPTION_TIMER_INTERRUPT, 5652 + }, 4929 5653 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 4930 5654 }, { 4931 5655 .name = "xsr.configid0", 4932 - .translate = translate_xsr, 4933 - .test_ill = test_ill_xsr, 4934 - .par = (const uint32_t[]){CONFIGID0}, 4935 - .op_flags = XTENSA_OP_PRIVILEGED, 5656 + .op_flags = XTENSA_OP_ILL, 4936 5657 }, { 4937 5658 .name = "xsr.configid1", 4938 - .translate = translate_xsr, 4939 - .test_ill = test_ill_xsr, 4940 - .par = (const uint32_t[]){CONFIGID1}, 4941 - .op_flags = XTENSA_OP_PRIVILEGED, 5659 + .op_flags = XTENSA_OP_ILL, 4942 5660 }, { 4943 5661 .name = "xsr.cpenable", 4944 - .translate = translate_xsr, 4945 - .test_ill = test_ill_xsr, 4946 - .par = (const uint32_t[]){CPENABLE}, 5662 + .translate = translate_xsr_mask, 5663 + .test_ill = test_ill_sr, 5664 + .par = (const uint32_t[]){ 5665 + CPENABLE, 5666 + XTENSA_OPTION_COPROCESSOR, 5667 + 0xff, 5668 + }, 4947 5669 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 4948 5670 }, { 4949 5671 .name = "xsr.dbreaka0", 4950 - .translate = translate_xsr, 4951 - .test_ill = test_ill_xsr, 4952 - .par = (const uint32_t[]){DBREAKA}, 5672 + .translate = translate_xsr_dbreaka, 5673 + .test_ill = test_ill_dbreak, 5674 + .par = (const uint32_t[]){ 5675 + DBREAKA, 5676 + XTENSA_OPTION_DEBUG, 5677 + }, 4953 5678 .op_flags = XTENSA_OP_PRIVILEGED, 4954 5679 }, { 4955 5680 .name = "xsr.dbreaka1", 4956 - .translate = translate_xsr, 4957 - .test_ill = test_ill_xsr, 4958 - .par = (const uint32_t[]){DBREAKA + 1}, 5681 + .translate = translate_xsr_dbreaka, 5682 + .test_ill = test_ill_dbreak, 5683 + .par = (const uint32_t[]){ 5684 + DBREAKA + 1, 5685 + XTENSA_OPTION_DEBUG, 5686 + }, 4959 5687 .op_flags = XTENSA_OP_PRIVILEGED, 4960 5688 }, { 4961 5689 .name = "xsr.dbreakc0", 4962 - .translate = translate_xsr, 4963 - .test_ill = test_ill_xsr, 4964 - .par = (const uint32_t[]){DBREAKC}, 5690 + .translate = translate_xsr_dbreakc, 5691 + .test_ill = test_ill_dbreak, 5692 + .par = (const uint32_t[]){ 5693 + DBREAKC, 5694 + XTENSA_OPTION_DEBUG, 5695 + }, 4965 5696 .op_flags = XTENSA_OP_PRIVILEGED, 4966 5697 }, { 4967 5698 .name = "xsr.dbreakc1", 4968 - .translate = translate_xsr, 4969 - .test_ill = test_ill_xsr, 4970 - .par = (const uint32_t[]){DBREAKC + 1}, 5699 + .translate = translate_xsr_dbreakc, 5700 + .test_ill = test_ill_dbreak, 5701 + .par = (const uint32_t[]){ 5702 + DBREAKC + 1, 5703 + XTENSA_OPTION_DEBUG, 5704 + }, 4971 5705 .op_flags = XTENSA_OP_PRIVILEGED, 4972 5706 }, { 4973 5707 .name = "xsr.ddr", 4974 5708 .translate = translate_xsr, 4975 - .test_ill = test_ill_xsr, 4976 - .par = (const uint32_t[]){DDR}, 5709 + .test_ill = test_ill_sr, 5710 + .par = (const uint32_t[]){ 5711 + DDR, 5712 + XTENSA_OPTION_DEBUG, 5713 + }, 4977 5714 .op_flags = XTENSA_OP_PRIVILEGED, 4978 5715 }, { 4979 5716 .name = "xsr.debugcause", 4980 - .translate = translate_xsr, 4981 - .test_ill = test_ill_xsr, 4982 - .par = (const uint32_t[]){DEBUGCAUSE}, 4983 - .op_flags = XTENSA_OP_PRIVILEGED, 5717 + .op_flags = XTENSA_OP_ILL, 4984 5718 }, { 4985 5719 .name = "xsr.depc", 4986 5720 .translate = translate_xsr, 4987 - .test_ill = test_ill_xsr, 4988 - .par = (const uint32_t[]){DEPC}, 5721 + .test_ill = test_ill_sr, 5722 + .par = (const uint32_t[]){ 5723 + DEPC, 5724 + XTENSA_OPTION_EXCEPTION, 5725 + }, 4989 5726 .op_flags = XTENSA_OP_PRIVILEGED, 4990 5727 }, { 4991 5728 .name = "xsr.dtlbcfg", 4992 - .translate = translate_xsr, 4993 - .test_ill = test_ill_xsr, 4994 - .par = (const uint32_t[]){DTLBCFG}, 5729 + .translate = translate_xsr_mask, 5730 + .test_ill = test_ill_sr, 5731 + .par = (const uint32_t[]){ 5732 + DTLBCFG, 5733 + XTENSA_OPTION_MMU, 5734 + 0x01130000, 5735 + }, 4995 5736 .op_flags = XTENSA_OP_PRIVILEGED, 4996 5737 }, { 4997 5738 .name = "xsr.epc1", 4998 5739 .translate = translate_xsr, 4999 - .test_ill = test_ill_xsr, 5000 - .par = (const uint32_t[]){EPC1}, 5740 + .test_ill = test_ill_sr, 5741 + .par = (const uint32_t[]){ 5742 + EPC1, 5743 + XTENSA_OPTION_EXCEPTION, 5744 + }, 5001 5745 .op_flags = XTENSA_OP_PRIVILEGED, 5002 5746 }, { 5003 5747 .name = "xsr.epc2", 5004 5748 .translate = translate_xsr, 5005 - .test_ill = test_ill_xsr, 5006 - .par = (const uint32_t[]){EPC1 + 1}, 5749 + .test_ill = test_ill_hpi, 5750 + .par = (const uint32_t[]){ 5751 + EPC1 + 1, 5752 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5753 + }, 5007 5754 .op_flags = XTENSA_OP_PRIVILEGED, 5008 5755 }, { 5009 5756 .name = "xsr.epc3", 5010 5757 .translate = translate_xsr, 5011 - .test_ill = test_ill_xsr, 5012 - .par = (const uint32_t[]){EPC1 + 2}, 5758 + .test_ill = test_ill_hpi, 5759 + .par = (const uint32_t[]){ 5760 + EPC1 + 2, 5761 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5762 + }, 5013 5763 .op_flags = XTENSA_OP_PRIVILEGED, 5014 5764 }, { 5015 5765 .name = "xsr.epc4", 5016 5766 .translate = translate_xsr, 5017 - .test_ill = test_ill_xsr, 5018 - .par = (const uint32_t[]){EPC1 + 3}, 5767 + .test_ill = test_ill_hpi, 5768 + .par = (const uint32_t[]){ 5769 + EPC1 + 3, 5770 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5771 + }, 5019 5772 .op_flags = XTENSA_OP_PRIVILEGED, 5020 5773 }, { 5021 5774 .name = "xsr.epc5", 5022 5775 .translate = translate_xsr, 5023 - .test_ill = test_ill_xsr, 5024 - .par = (const uint32_t[]){EPC1 + 4}, 5776 + .test_ill = test_ill_hpi, 5777 + .par = (const uint32_t[]){ 5778 + EPC1 + 4, 5779 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5780 + }, 5025 5781 .op_flags = XTENSA_OP_PRIVILEGED, 5026 5782 }, { 5027 5783 .name = "xsr.epc6", 5028 5784 .translate = translate_xsr, 5029 - .test_ill = test_ill_xsr, 5030 - .par = (const uint32_t[]){EPC1 + 5}, 5785 + .test_ill = test_ill_hpi, 5786 + .par = (const uint32_t[]){ 5787 + EPC1 + 5, 5788 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5789 + }, 5031 5790 .op_flags = XTENSA_OP_PRIVILEGED, 5032 5791 }, { 5033 5792 .name = "xsr.epc7", 5034 5793 .translate = translate_xsr, 5035 - .test_ill = test_ill_xsr, 5036 - .par = (const uint32_t[]){EPC1 + 6}, 5794 + .test_ill = test_ill_hpi, 5795 + .par = (const uint32_t[]){ 5796 + EPC1 + 6, 5797 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5798 + }, 5037 5799 .op_flags = XTENSA_OP_PRIVILEGED, 5038 5800 }, { 5039 5801 .name = "xsr.eps2", 5040 5802 .translate = translate_xsr, 5041 - .test_ill = test_ill_xsr, 5042 - .par = (const uint32_t[]){EPS2}, 5803 + .test_ill = test_ill_hpi, 5804 + .par = (const uint32_t[]){ 5805 + EPS2, 5806 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5807 + }, 5043 5808 .op_flags = XTENSA_OP_PRIVILEGED, 5044 5809 }, { 5045 5810 .name = "xsr.eps3", 5046 5811 .translate = translate_xsr, 5047 - .test_ill = test_ill_xsr, 5048 - .par = (const uint32_t[]){EPS2 + 1}, 5812 + .test_ill = test_ill_hpi, 5813 + .par = (const uint32_t[]){ 5814 + EPS2 + 1, 5815 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5816 + }, 5049 5817 .op_flags = XTENSA_OP_PRIVILEGED, 5050 5818 }, { 5051 5819 .name = "xsr.eps4", 5052 5820 .translate = translate_xsr, 5053 - .test_ill = test_ill_xsr, 5054 - .par = (const uint32_t[]){EPS2 + 2}, 5821 + .test_ill = test_ill_hpi, 5822 + .par = (const uint32_t[]){ 5823 + EPS2 + 2, 5824 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5825 + }, 5055 5826 .op_flags = XTENSA_OP_PRIVILEGED, 5056 5827 }, { 5057 5828 .name = "xsr.eps5", 5058 5829 .translate = translate_xsr, 5059 - .test_ill = test_ill_xsr, 5060 - .par = (const uint32_t[]){EPS2 + 3}, 5830 + .test_ill = test_ill_hpi, 5831 + .par = (const uint32_t[]){ 5832 + EPS2 + 3, 5833 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5834 + }, 5061 5835 .op_flags = XTENSA_OP_PRIVILEGED, 5062 5836 }, { 5063 5837 .name = "xsr.eps6", 5064 5838 .translate = translate_xsr, 5065 - .test_ill = test_ill_xsr, 5066 - .par = (const uint32_t[]){EPS2 + 4}, 5839 + .test_ill = test_ill_hpi, 5840 + .par = (const uint32_t[]){ 5841 + EPS2 + 4, 5842 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5843 + }, 5067 5844 .op_flags = XTENSA_OP_PRIVILEGED, 5068 5845 }, { 5069 5846 .name = "xsr.eps7", 5070 5847 .translate = translate_xsr, 5071 - .test_ill = test_ill_xsr, 5072 - .par = (const uint32_t[]){EPS2 + 5}, 5848 + .test_ill = test_ill_hpi, 5849 + .par = (const uint32_t[]){ 5850 + EPS2 + 5, 5851 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5852 + }, 5853 + .op_flags = XTENSA_OP_PRIVILEGED, 5854 + }, { 5855 + .name = "xsr.eraccess", 5856 + .translate = translate_xsr_mask, 5857 + .par = (const uint32_t[]){ 5858 + ERACCESS, 5859 + 0, 5860 + 0xffff, 5861 + }, 5073 5862 .op_flags = XTENSA_OP_PRIVILEGED, 5074 5863 }, { 5075 5864 .name = "xsr.exccause", 5076 5865 .translate = translate_xsr, 5077 - .test_ill = test_ill_xsr, 5078 - .par = (const uint32_t[]){EXCCAUSE}, 5866 + .test_ill = test_ill_sr, 5867 + .par = (const uint32_t[]){ 5868 + EXCCAUSE, 5869 + XTENSA_OPTION_EXCEPTION, 5870 + }, 5079 5871 .op_flags = XTENSA_OP_PRIVILEGED, 5080 5872 }, { 5081 5873 .name = "xsr.excsave1", 5082 5874 .translate = translate_xsr, 5083 - .test_ill = test_ill_xsr, 5084 - .par = (const uint32_t[]){EXCSAVE1}, 5875 + .test_ill = test_ill_sr, 5876 + .par = (const uint32_t[]){ 5877 + EXCSAVE1, 5878 + XTENSA_OPTION_EXCEPTION, 5879 + }, 5085 5880 .op_flags = XTENSA_OP_PRIVILEGED, 5086 5881 }, { 5087 5882 .name = "xsr.excsave2", 5088 5883 .translate = translate_xsr, 5089 - .test_ill = test_ill_xsr, 5090 - .par = (const uint32_t[]){EXCSAVE1 + 1}, 5884 + .test_ill = test_ill_hpi, 5885 + .par = (const uint32_t[]){ 5886 + EXCSAVE1 + 1, 5887 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5888 + }, 5091 5889 .op_flags = XTENSA_OP_PRIVILEGED, 5092 5890 }, { 5093 5891 .name = "xsr.excsave3", 5094 5892 .translate = translate_xsr, 5095 - .test_ill = test_ill_xsr, 5096 - .par = (const uint32_t[]){EXCSAVE1 + 2}, 5893 + .test_ill = test_ill_hpi, 5894 + .par = (const uint32_t[]){ 5895 + EXCSAVE1 + 2, 5896 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5897 + }, 5097 5898 .op_flags = XTENSA_OP_PRIVILEGED, 5098 5899 }, { 5099 5900 .name = "xsr.excsave4", 5100 5901 .translate = translate_xsr, 5101 - .test_ill = test_ill_xsr, 5102 - .par = (const uint32_t[]){EXCSAVE1 + 3}, 5902 + .test_ill = test_ill_hpi, 5903 + .par = (const uint32_t[]){ 5904 + EXCSAVE1 + 3, 5905 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5906 + }, 5103 5907 .op_flags = XTENSA_OP_PRIVILEGED, 5104 5908 }, { 5105 5909 .name = "xsr.excsave5", 5106 5910 .translate = translate_xsr, 5107 - .test_ill = test_ill_xsr, 5108 - .par = (const uint32_t[]){EXCSAVE1 + 4}, 5911 + .test_ill = test_ill_hpi, 5912 + .par = (const uint32_t[]){ 5913 + EXCSAVE1 + 4, 5914 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5915 + }, 5109 5916 .op_flags = XTENSA_OP_PRIVILEGED, 5110 5917 }, { 5111 5918 .name = "xsr.excsave6", 5112 5919 .translate = translate_xsr, 5113 - .test_ill = test_ill_xsr, 5114 - .par = (const uint32_t[]){EXCSAVE1 + 5}, 5920 + .test_ill = test_ill_hpi, 5921 + .par = (const uint32_t[]){ 5922 + EXCSAVE1 + 5, 5923 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5924 + }, 5115 5925 .op_flags = XTENSA_OP_PRIVILEGED, 5116 5926 }, { 5117 5927 .name = "xsr.excsave7", 5118 5928 .translate = translate_xsr, 5119 - .test_ill = test_ill_xsr, 5120 - .par = (const uint32_t[]){EXCSAVE1 + 6}, 5929 + .test_ill = test_ill_hpi, 5930 + .par = (const uint32_t[]){ 5931 + EXCSAVE1 + 6, 5932 + XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, 5933 + }, 5121 5934 .op_flags = XTENSA_OP_PRIVILEGED, 5122 5935 }, { 5123 5936 .name = "xsr.excvaddr", 5124 5937 .translate = translate_xsr, 5125 - .test_ill = test_ill_xsr, 5126 - .par = (const uint32_t[]){EXCVADDR}, 5938 + .test_ill = test_ill_sr, 5939 + .par = (const uint32_t[]){ 5940 + EXCVADDR, 5941 + XTENSA_OPTION_EXCEPTION, 5942 + }, 5127 5943 .op_flags = XTENSA_OP_PRIVILEGED, 5128 5944 }, { 5129 5945 .name = "xsr.ibreaka0", 5130 - .translate = translate_xsr, 5131 - .test_ill = test_ill_xsr, 5132 - .par = (const uint32_t[]){IBREAKA}, 5946 + .translate = translate_xsr_ibreaka, 5947 + .test_ill = test_ill_ibreak, 5948 + .par = (const uint32_t[]){ 5949 + IBREAKA, 5950 + XTENSA_OPTION_DEBUG, 5951 + }, 5133 5952 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 5134 5953 }, { 5135 5954 .name = "xsr.ibreaka1", 5136 - .translate = translate_xsr, 5137 - .test_ill = test_ill_xsr, 5138 - .par = (const uint32_t[]){IBREAKA + 1}, 5955 + .translate = translate_xsr_ibreaka, 5956 + .test_ill = test_ill_ibreak, 5957 + .par = (const uint32_t[]){ 5958 + IBREAKA + 1, 5959 + XTENSA_OPTION_DEBUG, 5960 + }, 5139 5961 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 5140 5962 }, { 5141 5963 .name = "xsr.ibreakenable", 5142 - .translate = translate_xsr, 5143 - .test_ill = test_ill_xsr, 5144 - .par = (const uint32_t[]){IBREAKENABLE}, 5964 + .translate = translate_xsr_ibreakenable, 5965 + .test_ill = test_ill_sr, 5966 + .par = (const uint32_t[]){ 5967 + IBREAKENABLE, 5968 + XTENSA_OPTION_DEBUG, 5969 + }, 5145 5970 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, 5146 5971 }, { 5147 5972 .name = "xsr.icount", 5148 - .translate = translate_xsr, 5149 - .test_ill = test_ill_xsr, 5150 - .par = (const uint32_t[]){ICOUNT}, 5973 + .translate = translate_xsr_icount, 5974 + .test_ill = test_ill_sr, 5975 + .par = (const uint32_t[]){ 5976 + ICOUNT, 5977 + XTENSA_OPTION_DEBUG, 5978 + }, 5151 5979 .op_flags = XTENSA_OP_PRIVILEGED, 5152 5980 }, { 5153 5981 .name = "xsr.icountlevel", 5154 - .translate = translate_xsr, 5155 - .test_ill = test_ill_xsr, 5156 - .par = (const uint32_t[]){ICOUNTLEVEL}, 5982 + .translate = translate_xsr_mask, 5983 + .test_ill = test_ill_sr, 5984 + .par = (const uint32_t[]){ 5985 + ICOUNTLEVEL, 5986 + XTENSA_OPTION_DEBUG, 5987 + 0xf, 5988 + }, 5157 5989 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5158 5990 }, { 5159 5991 .name = "xsr.intclear", 5160 - .translate = translate_xsr, 5161 - .test_ill = test_ill_xsr, 5162 - .par = (const uint32_t[]){INTCLEAR}, 5163 - .op_flags = 5164 - XTENSA_OP_PRIVILEGED | 5165 - XTENSA_OP_EXIT_TB_0 | 5166 - XTENSA_OP_CHECK_INTERRUPTS, 5992 + .op_flags = XTENSA_OP_ILL, 5167 5993 }, { 5168 5994 .name = "xsr.intenable", 5169 5995 .translate = translate_xsr, 5170 - .test_ill = test_ill_xsr, 5171 - .par = (const uint32_t[]){INTENABLE}, 5996 + .test_ill = test_ill_sr, 5997 + .par = (const uint32_t[]){ 5998 + INTENABLE, 5999 + XTENSA_OPTION_INTERRUPT, 6000 + }, 5172 6001 .op_flags = 5173 6002 XTENSA_OP_PRIVILEGED | 5174 6003 XTENSA_OP_EXIT_TB_0 | 5175 6004 XTENSA_OP_CHECK_INTERRUPTS, 5176 6005 }, { 5177 6006 .name = "xsr.interrupt", 5178 - .translate = translate_xsr, 5179 - .test_ill = test_ill_xsr, 5180 - .par = (const uint32_t[]){INTSET}, 5181 - .op_flags = 5182 - XTENSA_OP_PRIVILEGED | 5183 - XTENSA_OP_EXIT_TB_0 | 5184 - XTENSA_OP_CHECK_INTERRUPTS, 6007 + .op_flags = XTENSA_OP_ILL, 5185 6008 }, { 5186 6009 .name = "xsr.intset", 5187 - .translate = translate_xsr, 5188 - .test_ill = test_ill_xsr, 5189 - .par = (const uint32_t[]){INTSET}, 5190 - .op_flags = 5191 - XTENSA_OP_PRIVILEGED | 5192 - XTENSA_OP_EXIT_TB_0 | 5193 - XTENSA_OP_CHECK_INTERRUPTS, 6010 + .op_flags = XTENSA_OP_ILL, 5194 6011 }, { 5195 6012 .name = "xsr.itlbcfg", 5196 - .translate = translate_xsr, 5197 - .test_ill = test_ill_xsr, 5198 - .par = (const uint32_t[]){ITLBCFG}, 6013 + .translate = translate_xsr_mask, 6014 + .test_ill = test_ill_sr, 6015 + .par = (const uint32_t[]){ 6016 + ITLBCFG, 6017 + XTENSA_OPTION_MMU, 6018 + 0x01130000, 6019 + }, 5199 6020 .op_flags = XTENSA_OP_PRIVILEGED, 5200 6021 }, { 5201 6022 .name = "xsr.lbeg", 5202 6023 .translate = translate_xsr, 5203 - .test_ill = test_ill_xsr, 5204 - .par = (const uint32_t[]){LBEG}, 6024 + .test_ill = test_ill_sr, 6025 + .par = (const uint32_t[]){ 6026 + LBEG, 6027 + XTENSA_OPTION_LOOP, 6028 + }, 5205 6029 .op_flags = XTENSA_OP_EXIT_TB_M1, 5206 6030 }, { 5207 6031 .name = "xsr.lcount", 5208 6032 .translate = translate_xsr, 5209 - .test_ill = test_ill_xsr, 5210 - .par = (const uint32_t[]){LCOUNT}, 6033 + .test_ill = test_ill_sr, 6034 + .par = (const uint32_t[]){ 6035 + LCOUNT, 6036 + XTENSA_OPTION_LOOP, 6037 + }, 5211 6038 }, { 5212 6039 .name = "xsr.lend", 5213 6040 .translate = translate_xsr, 5214 - .test_ill = test_ill_xsr, 5215 - .par = (const uint32_t[]){LEND}, 6041 + .test_ill = test_ill_sr, 6042 + .par = (const uint32_t[]){ 6043 + LEND, 6044 + XTENSA_OPTION_LOOP, 6045 + }, 5216 6046 .op_flags = XTENSA_OP_EXIT_TB_M1, 5217 6047 }, { 5218 6048 .name = "xsr.litbase", 5219 - .translate = translate_xsr, 5220 - .test_ill = test_ill_xsr, 5221 - .par = (const uint32_t[]){LITBASE}, 6049 + .translate = translate_xsr_mask, 6050 + .test_ill = test_ill_sr, 6051 + .par = (const uint32_t[]){ 6052 + LITBASE, 6053 + XTENSA_OPTION_EXTENDED_L32R, 6054 + 0xfffff001, 6055 + }, 5222 6056 .op_flags = XTENSA_OP_EXIT_TB_M1, 5223 6057 }, { 5224 6058 .name = "xsr.m0", 5225 6059 .translate = translate_xsr, 5226 - .test_ill = test_ill_xsr, 5227 - .par = (const uint32_t[]){MR}, 6060 + .test_ill = test_ill_sr, 6061 + .par = (const uint32_t[]){ 6062 + MR, 6063 + XTENSA_OPTION_MAC16, 6064 + }, 5228 6065 }, { 5229 6066 .name = "xsr.m1", 5230 6067 .translate = translate_xsr, 5231 - .test_ill = test_ill_xsr, 5232 - .par = (const uint32_t[]){MR + 1}, 6068 + .test_ill = test_ill_sr, 6069 + .par = (const uint32_t[]){ 6070 + MR + 1, 6071 + XTENSA_OPTION_MAC16, 6072 + }, 5233 6073 }, { 5234 6074 .name = "xsr.m2", 5235 6075 .translate = translate_xsr, 5236 - .test_ill = test_ill_xsr, 5237 - .par = (const uint32_t[]){MR + 2}, 6076 + .test_ill = test_ill_sr, 6077 + .par = (const uint32_t[]){ 6078 + MR + 2, 6079 + XTENSA_OPTION_MAC16, 6080 + }, 5238 6081 }, { 5239 6082 .name = "xsr.m3", 5240 6083 .translate = translate_xsr, 5241 - .test_ill = test_ill_xsr, 5242 - .par = (const uint32_t[]){MR + 3}, 6084 + .test_ill = test_ill_sr, 6085 + .par = (const uint32_t[]){ 6086 + MR + 3, 6087 + XTENSA_OPTION_MAC16, 6088 + }, 5243 6089 }, { 5244 6090 .name = "xsr.memctl", 5245 - .translate = translate_xsr, 5246 - .test_ill = test_ill_xsr, 6091 + .translate = translate_xsr_memctl, 5247 6092 .par = (const uint32_t[]){MEMCTL}, 5248 6093 .op_flags = XTENSA_OP_PRIVILEGED, 5249 6094 }, { 6095 + .name = "xsr.mecr", 6096 + .translate = translate_xsr, 6097 + .test_ill = test_ill_sr, 6098 + .par = (const uint32_t[]){ 6099 + MECR, 6100 + XTENSA_OPTION_MEMORY_ECC_PARITY, 6101 + }, 6102 + .op_flags = XTENSA_OP_PRIVILEGED, 6103 + }, { 6104 + .name = "xsr.mepc", 6105 + .translate = translate_xsr, 6106 + .test_ill = test_ill_sr, 6107 + .par = (const uint32_t[]){ 6108 + MEPC, 6109 + XTENSA_OPTION_MEMORY_ECC_PARITY, 6110 + }, 6111 + .op_flags = XTENSA_OP_PRIVILEGED, 6112 + }, { 6113 + .name = "xsr.meps", 6114 + .translate = translate_xsr, 6115 + .test_ill = test_ill_sr, 6116 + .par = (const uint32_t[]){ 6117 + MEPS, 6118 + XTENSA_OPTION_MEMORY_ECC_PARITY, 6119 + }, 6120 + .op_flags = XTENSA_OP_PRIVILEGED, 6121 + }, { 6122 + .name = "xsr.mesave", 6123 + .translate = translate_xsr, 6124 + .test_ill = test_ill_sr, 6125 + .par = (const uint32_t[]){ 6126 + MESAVE, 6127 + XTENSA_OPTION_MEMORY_ECC_PARITY, 6128 + }, 6129 + .op_flags = XTENSA_OP_PRIVILEGED, 6130 + }, { 6131 + .name = "xsr.mesr", 6132 + .translate = translate_xsr, 6133 + .test_ill = test_ill_sr, 6134 + .par = (const uint32_t[]){ 6135 + MESR, 6136 + XTENSA_OPTION_MEMORY_ECC_PARITY, 6137 + }, 6138 + .op_flags = XTENSA_OP_PRIVILEGED, 6139 + }, { 6140 + .name = "xsr.mevaddr", 6141 + .translate = translate_xsr, 6142 + .test_ill = test_ill_sr, 6143 + .par = (const uint32_t[]){ 6144 + MESR, 6145 + XTENSA_OPTION_MEMORY_ECC_PARITY, 6146 + }, 6147 + .op_flags = XTENSA_OP_PRIVILEGED, 6148 + }, { 5250 6149 .name = "xsr.misc0", 5251 6150 .translate = translate_xsr, 5252 - .test_ill = test_ill_xsr, 5253 - .par = (const uint32_t[]){MISC}, 6151 + .test_ill = test_ill_sr, 6152 + .par = (const uint32_t[]){ 6153 + MISC, 6154 + XTENSA_OPTION_MISC_SR, 6155 + }, 5254 6156 .op_flags = XTENSA_OP_PRIVILEGED, 5255 6157 }, { 5256 6158 .name = "xsr.misc1", 5257 6159 .translate = translate_xsr, 5258 - .test_ill = test_ill_xsr, 5259 - .par = (const uint32_t[]){MISC + 1}, 6160 + .test_ill = test_ill_sr, 6161 + .par = (const uint32_t[]){ 6162 + MISC + 1, 6163 + XTENSA_OPTION_MISC_SR, 6164 + }, 5260 6165 .op_flags = XTENSA_OP_PRIVILEGED, 5261 6166 }, { 5262 6167 .name = "xsr.misc2", 5263 6168 .translate = translate_xsr, 5264 - .test_ill = test_ill_xsr, 5265 - .par = (const uint32_t[]){MISC + 2}, 6169 + .test_ill = test_ill_sr, 6170 + .par = (const uint32_t[]){ 6171 + MISC + 2, 6172 + XTENSA_OPTION_MISC_SR, 6173 + }, 5266 6174 .op_flags = XTENSA_OP_PRIVILEGED, 5267 6175 }, { 5268 6176 .name = "xsr.misc3", 5269 6177 .translate = translate_xsr, 5270 - .test_ill = test_ill_xsr, 5271 - .par = (const uint32_t[]){MISC + 3}, 6178 + .test_ill = test_ill_sr, 6179 + .par = (const uint32_t[]){ 6180 + MISC + 3, 6181 + XTENSA_OPTION_MISC_SR, 6182 + }, 5272 6183 .op_flags = XTENSA_OP_PRIVILEGED, 5273 6184 }, { 6185 + .name = "xsr.mpuenb", 6186 + .translate = translate_xsr_mpuenb, 6187 + .test_ill = test_ill_sr, 6188 + .par = (const uint32_t[]){ 6189 + MPUENB, 6190 + XTENSA_OPTION_MPU, 6191 + }, 6192 + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 6193 + }, { 5274 6194 .name = "xsr.prefctl", 5275 6195 .translate = translate_xsr, 5276 - .test_ill = test_ill_xsr, 5277 6196 .par = (const uint32_t[]){PREFCTL}, 5278 6197 }, { 5279 6198 .name = "xsr.prid", 5280 - .translate = translate_xsr, 5281 - .test_ill = test_ill_xsr, 5282 - .par = (const uint32_t[]){PRID}, 5283 - .op_flags = XTENSA_OP_PRIVILEGED, 6199 + .op_flags = XTENSA_OP_ILL, 5284 6200 }, { 5285 6201 .name = "xsr.ps", 5286 - .translate = translate_xsr, 5287 - .test_ill = test_ill_xsr, 5288 - .par = (const uint32_t[]){PS}, 6202 + .translate = translate_xsr_ps, 6203 + .test_ill = test_ill_sr, 6204 + .par = (const uint32_t[]){ 6205 + PS, 6206 + XTENSA_OPTION_EXCEPTION, 6207 + }, 5289 6208 .op_flags = 5290 6209 XTENSA_OP_PRIVILEGED | 5291 6210 XTENSA_OP_EXIT_TB_M1 | 5292 6211 XTENSA_OP_CHECK_INTERRUPTS, 5293 6212 }, { 5294 6213 .name = "xsr.ptevaddr", 5295 - .translate = translate_xsr, 5296 - .test_ill = test_ill_xsr, 5297 - .par = (const uint32_t[]){PTEVADDR}, 6214 + .translate = translate_xsr_mask, 6215 + .test_ill = test_ill_sr, 6216 + .par = (const uint32_t[]){ 6217 + PTEVADDR, 6218 + XTENSA_OPTION_MMU, 6219 + 0xffc00000, 6220 + }, 5298 6221 .op_flags = XTENSA_OP_PRIVILEGED, 5299 6222 }, { 5300 6223 .name = "xsr.rasid", 5301 - .translate = translate_xsr, 5302 - .test_ill = test_ill_xsr, 5303 - .par = (const uint32_t[]){RASID}, 6224 + .translate = translate_xsr_rasid, 6225 + .test_ill = test_ill_sr, 6226 + .par = (const uint32_t[]){ 6227 + RASID, 6228 + XTENSA_OPTION_MMU, 6229 + }, 5304 6230 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5305 6231 }, { 5306 6232 .name = "xsr.sar", 5307 - .translate = translate_xsr, 5308 - .test_ill = test_ill_xsr, 6233 + .translate = translate_xsr_sar, 5309 6234 .par = (const uint32_t[]){SAR}, 5310 6235 }, { 5311 6236 .name = "xsr.scompare1", 5312 6237 .translate = translate_xsr, 5313 - .test_ill = test_ill_xsr, 5314 - .par = (const uint32_t[]){SCOMPARE1}, 6238 + .test_ill = test_ill_sr, 6239 + .par = (const uint32_t[]){ 6240 + SCOMPARE1, 6241 + XTENSA_OPTION_CONDITIONAL_STORE, 6242 + }, 5315 6243 }, { 5316 6244 .name = "xsr.vecbase", 5317 6245 .translate = translate_xsr, 5318 - .test_ill = test_ill_xsr, 5319 - .par = (const uint32_t[]){VECBASE}, 6246 + .test_ill = test_ill_sr, 6247 + .par = (const uint32_t[]){ 6248 + VECBASE, 6249 + XTENSA_OPTION_RELOCATABLE_VECTOR, 6250 + }, 5320 6251 .op_flags = XTENSA_OP_PRIVILEGED, 5321 6252 }, { 5322 6253 .name = "xsr.windowbase", 5323 - .translate = translate_xsr, 5324 - .test_ill = test_ill_xsr, 5325 - .par = (const uint32_t[]){WINDOW_BASE}, 6254 + .translate = translate_xsr_windowbase, 6255 + .test_ill = test_ill_sr, 6256 + .par = (const uint32_t[]){ 6257 + WINDOW_BASE, 6258 + XTENSA_OPTION_WINDOWED_REGISTER, 6259 + }, 5326 6260 .op_flags = XTENSA_OP_PRIVILEGED | 5327 6261 XTENSA_OP_EXIT_TB_M1 | 5328 6262 XTENSA_OP_SYNC_REGISTER_WINDOW, 5329 6263 }, { 5330 6264 .name = "xsr.windowstart", 5331 - .translate = translate_xsr, 5332 - .test_ill = test_ill_xsr, 5333 - .par = (const uint32_t[]){WINDOW_START}, 6265 + .translate = translate_xsr_windowstart, 6266 + .test_ill = test_ill_sr, 6267 + .par = (const uint32_t[]){ 6268 + WINDOW_START, 6269 + XTENSA_OPTION_WINDOWED_REGISTER, 6270 + }, 5334 6271 .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, 5335 6272 }, 5336 6273 };

+48

tests/tcg/xtensa/test_exclusive.S

··· 1 + #include "macros.inc" 2 + 3 + test_suite exclusive 4 + 5 + #if XCHAL_HAVE_EXCLUSIVE 6 + 7 + test exclusive_nowrite 8 + movi a2, 0x29 9 + wsr a2, atomctl 10 + clrex 11 + movi a2, 1f 12 + movi a3, 1 13 + s32ex a3, a2 14 + getex a3 15 + assert eqi, a3, 0 16 + l32i a3, a2, 0 17 + assert eqi, a3, 3 18 + 19 + .data 20 + .align 4 21 + 1: 22 + .word 3 23 + .text 24 + test_end 25 + 26 + test exclusive_write 27 + movi a2, 0x29 28 + wsr a2, atomctl 29 + movi a2, 1f 30 + l32ex a3, a2 31 + assert eqi, a3, 3 32 + movi a3, 2 33 + s32ex a3, a2 34 + getex a3 35 + assert eqi, a3, 1 36 + l32i a3, a2, 0 37 + assert eqi, a3, 2 38 + 39 + .data 40 + .align 4 41 + 1: 42 + .word 3 43 + .text 44 + test_end 45 + 46 + #endif 47 + 48 + test_suite_end