jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
msf2: Add Smartfusion2 SPI controller
Modelled Microsemi's Smartfusion2 SPI controller.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170920201737.25723-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Subbaraya Sundeep
and committed by
Peter Maydell
268ee7de
0ee1e1f4
+463
+1
hw/ssi/Makefile.objs
+1
hw/ssi/Makefile.objs
+404
hw/ssi/mss-spi.c
+404
hw/ssi/mss-spi.c
···
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+
/*
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* Block model of SPI controller present in
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* Microsemi's SmartFusion2 and SmartFusion SoCs.
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*
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* Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/ssi/mss-spi.h"
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#include "qemu/log.h"
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#ifndef MSS_SPI_ERR_DEBUG
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#define MSS_SPI_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do { \
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if (MSS_SPI_ERR_DEBUG >= lvl) { \
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qemu_log("%s: " fmt "\n", __func__, ## args); \
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} \
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} while (0);
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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#define FIFO_CAPACITY 32
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#define R_SPI_CONTROL 0
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#define R_SPI_DFSIZE 1
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#define R_SPI_STATUS 2
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#define R_SPI_INTCLR 3
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#define R_SPI_RX 4
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#define R_SPI_TX 5
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#define R_SPI_CLKGEN 6
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#define R_SPI_SS 7
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#define R_SPI_MIS 8
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#define R_SPI_RIS 9
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+
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#define S_TXDONE (1 << 0)
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#define S_RXRDY (1 << 1)
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#define S_RXCHOVRF (1 << 2)
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#define S_RXFIFOFUL (1 << 4)
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#define S_RXFIFOFULNXT (1 << 5)
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#define S_RXFIFOEMP (1 << 6)
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#define S_RXFIFOEMPNXT (1 << 7)
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#define S_TXFIFOFUL (1 << 8)
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#define S_TXFIFOFULNXT (1 << 9)
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#define S_TXFIFOEMP (1 << 10)
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#define S_TXFIFOEMPNXT (1 << 11)
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#define S_FRAMESTART (1 << 12)
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#define S_SSEL (1 << 13)
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#define S_ACTIVE (1 << 14)
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#define C_ENABLE (1 << 0)
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#define C_MODE (1 << 1)
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#define C_INTRXDATA (1 << 4)
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#define C_INTTXDATA (1 << 5)
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#define C_INTRXOVRFLO (1 << 6)
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#define C_SPS (1 << 26)
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#define C_BIGFIFO (1 << 29)
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#define C_RESET (1 << 31)
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+
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#define FRAMESZ_MASK 0x1F
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#define FMCOUNT_MASK 0x00FFFF00
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#define FMCOUNT_SHIFT 8
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static void txfifo_reset(MSSSpiState *s)
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{
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fifo32_reset(&s->tx_fifo);
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+
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s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
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s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
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}
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static void rxfifo_reset(MSSSpiState *s)
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{
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fifo32_reset(&s->rx_fifo);
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s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
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s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
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}
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static void set_fifodepth(MSSSpiState *s)
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{
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unsigned int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
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if (size <= 8) {
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s->fifo_depth = 32;
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} else if (size <= 16) {
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s->fifo_depth = 16;
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} else if (size <= 32) {
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s->fifo_depth = 8;
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} else {
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s->fifo_depth = 4;
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}
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}
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static void update_mis(MSSSpiState *s)
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{
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uint32_t reg = s->regs[R_SPI_CONTROL];
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uint32_t tmp;
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/*
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* form the Control register interrupt enable bits
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* same as RIS, MIS and Interrupt clear registers for simplicity
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*/
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tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
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((reg & C_INTTXDATA) >> 5);
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s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
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}
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static void spi_update_irq(MSSSpiState *s)
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{
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int irq;
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update_mis(s);
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irq = !!(s->regs[R_SPI_MIS]);
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qemu_set_irq(s->irq, irq);
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}
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static void mss_spi_reset(DeviceState *d)
139
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{
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MSSSpiState *s = MSS_SPI(d);
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memset(s->regs, 0, sizeof s->regs);
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s->regs[R_SPI_CONTROL] = 0x80000102;
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s->regs[R_SPI_DFSIZE] = 0x4;
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s->regs[R_SPI_STATUS] = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;
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s->regs[R_SPI_CLKGEN] = 0x7;
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s->regs[R_SPI_RIS] = 0x0;
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s->fifo_depth = 4;
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s->frame_count = 1;
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s->enabled = false;
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rxfifo_reset(s);
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txfifo_reset(s);
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}
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static uint64_t
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spi_read(void *opaque, hwaddr addr, unsigned int size)
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{
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MSSSpiState *s = opaque;
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uint32_t ret = 0;
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addr >>= 2;
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switch (addr) {
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case R_SPI_RX:
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s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
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s->regs[R_SPI_STATUS] &= ~S_RXCHOVRF;
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ret = fifo32_pop(&s->rx_fifo);
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if (fifo32_is_empty(&s->rx_fifo)) {
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s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
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}
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break;
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+
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case R_SPI_MIS:
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update_mis(s);
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ret = s->regs[R_SPI_MIS];
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break;
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default:
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if (addr < ARRAY_SIZE(s->regs)) {
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ret = s->regs[addr];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
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addr * 4);
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return ret;
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}
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break;
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}
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DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32, addr * 4, ret);
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spi_update_irq(s);
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return ret;
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}
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static void assert_cs(MSSSpiState *s)
197
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{
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qemu_set_irq(s->cs_line, 0);
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}
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static void deassert_cs(MSSSpiState *s)
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{
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qemu_set_irq(s->cs_line, 1);
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}
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static void spi_flush_txfifo(MSSSpiState *s)
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{
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uint32_t tx;
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uint32_t rx;
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bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
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+
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/*
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* Chip Select(CS) is automatically controlled by this controller.
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* If SPS bit is set in Control register then CS is asserted
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* until all the frames set in frame count of Control register are
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* transferred. If SPS is not set then CS pulses between frames.
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* Note that Slave Select register specifies which of the CS line
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* has to be controlled automatically by controller. Bits SS[7:1] are for
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* masters in FPGA fabric since we model only Microcontroller subsystem
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* of Smartfusion2 we control only one CS(SS[0]) line.
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*/
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while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
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assert_cs(s);
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s->regs[R_SPI_STATUS] &= ~(S_TXDONE | S_RXRDY);
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tx = fifo32_pop(&s->tx_fifo);
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DB_PRINT("data tx:0x%" PRIx32, tx);
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rx = ssi_transfer(s->spi, tx);
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DB_PRINT("data rx:0x%" PRIx32, rx);
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if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
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s->regs[R_SPI_STATUS] |= S_RXCHOVRF;
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s->regs[R_SPI_RIS] |= S_RXCHOVRF;
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} else {
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fifo32_push(&s->rx_fifo, rx);
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s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
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if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
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s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
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} else if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
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s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
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}
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}
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s->frame_count--;
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if (!sps) {
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deassert_cs(s);
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}
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}
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if (!s->frame_count) {
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s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
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FMCOUNT_SHIFT;
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deassert_cs(s);
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s->regs[R_SPI_RIS] |= S_TXDONE | S_RXRDY;
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s->regs[R_SPI_STATUS] |= S_TXDONE | S_RXRDY;
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}
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}
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static void spi_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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MSSSpiState *s = opaque;
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uint32_t value = val64;
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DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32, addr, value);
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addr >>= 2;
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+
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switch (addr) {
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case R_SPI_TX:
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/* adding to already full FIFO */
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if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
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break;
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}
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s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
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fifo32_push(&s->tx_fifo, value);
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if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
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s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
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} else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
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s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
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}
281
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if (s->enabled) {
282
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spi_flush_txfifo(s);
283
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}
284
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break;
285
+
286
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case R_SPI_CONTROL:
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s->regs[R_SPI_CONTROL] = value;
288
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if (value & C_BIGFIFO) {
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set_fifodepth(s);
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} else {
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s->fifo_depth = 4;
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}
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s->enabled = value & C_ENABLE;
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s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
295
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if (value & C_RESET) {
296
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mss_spi_reset(DEVICE(s));
297
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}
298
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break;
299
+
300
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case R_SPI_DFSIZE:
301
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if (s->enabled) {
302
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break;
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}
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s->regs[R_SPI_DFSIZE] = value;
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break;
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+
307
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case R_SPI_INTCLR:
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s->regs[R_SPI_INTCLR] = value;
309
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if (value & S_TXDONE) {
310
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s->regs[R_SPI_RIS] &= ~S_TXDONE;
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}
312
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if (value & S_RXRDY) {
313
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s->regs[R_SPI_RIS] &= ~S_RXRDY;
314
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}
315
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if (value & S_RXCHOVRF) {
316
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s->regs[R_SPI_RIS] &= ~S_RXCHOVRF;
317
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}
318
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break;
319
+
320
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case R_SPI_MIS:
321
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case R_SPI_STATUS:
322
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case R_SPI_RIS:
323
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qemu_log_mask(LOG_GUEST_ERROR,
324
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"%s: Write to read only register 0x%" HWADDR_PRIx "\n",
325
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__func__, addr * 4);
326
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break;
327
+
328
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default:
329
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if (addr < ARRAY_SIZE(s->regs)) {
330
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s->regs[addr] = value;
331
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} else {
332
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qemu_log_mask(LOG_GUEST_ERROR,
333
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
334
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addr * 4);
335
+
}
336
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break;
337
+
}
338
+
339
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spi_update_irq(s);
340
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}
341
+
342
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static const MemoryRegionOps spi_ops = {
343
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.read = spi_read,
344
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.write = spi_write,
345
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.endianness = DEVICE_NATIVE_ENDIAN,
346
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.valid = {
347
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.min_access_size = 1,
348
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.max_access_size = 4
349
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}
350
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};
351
+
352
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static void mss_spi_realize(DeviceState *dev, Error **errp)
353
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{
354
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MSSSpiState *s = MSS_SPI(dev);
355
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
356
+
357
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s->spi = ssi_create_bus(dev, "spi");
358
+
359
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sysbus_init_irq(sbd, &s->irq);
360
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ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
361
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sysbus_init_irq(sbd, &s->cs_line);
362
+
363
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memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
364
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TYPE_MSS_SPI, R_SPI_MAX * 4);
365
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sysbus_init_mmio(sbd, &s->mmio);
366
+
367
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fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
368
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fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
369
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}
370
+
371
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static const VMStateDescription vmstate_mss_spi = {
372
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.name = TYPE_MSS_SPI,
373
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.version_id = 1,
374
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.minimum_version_id = 1,
375
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.fields = (VMStateField[]) {
376
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VMSTATE_FIFO32(tx_fifo, MSSSpiState),
377
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VMSTATE_FIFO32(rx_fifo, MSSSpiState),
378
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VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
379
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VMSTATE_END_OF_LIST()
380
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}
381
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};
382
+
383
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static void mss_spi_class_init(ObjectClass *klass, void *data)
384
+
{
385
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DeviceClass *dc = DEVICE_CLASS(klass);
386
+
387
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dc->realize = mss_spi_realize;
388
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dc->reset = mss_spi_reset;
389
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dc->vmsd = &vmstate_mss_spi;
390
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}
391
+
392
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static const TypeInfo mss_spi_info = {
393
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.name = TYPE_MSS_SPI,
394
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.parent = TYPE_SYS_BUS_DEVICE,
395
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.instance_size = sizeof(MSSSpiState),
396
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.class_init = mss_spi_class_init,
397
+
};
398
+
399
+
static void mss_spi_register_types(void)
400
+
{
401
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type_register_static(&mss_spi_info);
402
+
}
403
+
404
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type_init(mss_spi_register_types)
+58
include/hw/ssi/mss-spi.h
+58
include/hw/ssi/mss-spi.h
···
1
+
/*
2
+
* Microsemi SmartFusion2 SPI
3
+
*
4
+
* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
5
+
*
6
+
* Permission is hereby granted, free of charge, to any person obtaining a copy
7
+
* of this software and associated documentation files (the "Software"), to deal
8
+
* in the Software without restriction, including without limitation the rights
9
+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
+
* copies of the Software, and to permit persons to whom the Software is
11
+
* furnished to do so, subject to the following conditions:
12
+
*
13
+
* The above copyright notice and this permission notice shall be included in
14
+
* all copies or substantial portions of the Software.
15
+
*
16
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
+
* THE SOFTWARE.
23
+
*/
24
+
25
+
#ifndef HW_MSS_SPI_H
26
+
#define HW_MSS_SPI_H
27
+
28
+
#include "hw/sysbus.h"
29
+
#include "hw/ssi/ssi.h"
30
+
#include "qemu/fifo32.h"
31
+
32
+
#define TYPE_MSS_SPI "mss-spi"
33
+
#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
34
+
35
+
#define R_SPI_MAX 16
36
+
37
+
typedef struct MSSSpiState {
38
+
SysBusDevice parent_obj;
39
+
40
+
MemoryRegion mmio;
41
+
42
+
qemu_irq irq;
43
+
44
+
qemu_irq cs_line;
45
+
46
+
SSIBus *spi;
47
+
48
+
Fifo32 rx_fifo;
49
+
Fifo32 tx_fifo;
50
+
51
+
int fifo_depth;
52
+
uint32_t frame_count;
53
+
bool enabled;
54
+
55
+
uint32_t regs[R_SPI_MAX];
56
+
} MSSSpiState;
57
+
58
+
#endif /* HW_MSS_SPI_H */