jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
ppc/pnv: add a LPC Controller model for POWER10
Same a POWER9, only the MMIO window changes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191205184454.10722-6-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
authored by
Cédric Le Goater
and committed by
David Gibson
2661f6ab
8b50ce85
+53
-12
+22
-3
hw/ppc/pnv.c
+22
-3
hw/ppc/pnv.c
···
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pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
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}
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pnv_dt_lpc(chip, fdt, 0);
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pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
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}
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static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
···
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if (chip->ram_size) {
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pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
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}
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pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
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}
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static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
···
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static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
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{
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error_setg(errp, "No ISA bus!");
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return NULL;
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Pnv10Chip *chip10 = PNV10_CHIP(chip);
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return pnv_lpc_isa_create(&chip10->lpc, false, errp);
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}
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static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
···
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object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi),
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TYPE_PNV10_PSI, &error_abort, NULL);
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object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc),
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TYPE_PNV10_LPC, &error_abort, NULL);
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}
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static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
···
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}
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pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
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&PNV_PSI(&chip10->psi)->xscom_regs);
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+
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/* LPC */
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object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi",
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&error_abort);
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object_property_set_bool(OBJECT(&chip10->lpc), true, "realized",
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&local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
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&chip10->lpc.xscom_regs);
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chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
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(uint64_t) PNV10_LPCM_BASE(chip));
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}
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static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
+22
-8
hw/ppc/pnv_lpc.c
+22
-8
hw/ppc/pnv_lpc.c
···
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}
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/* POWER9 only */
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-
int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
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int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr,
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uint64_t lpcm_size)
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{
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const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
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const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
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char *name;
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int offset, lpcm_offset;
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uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
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uint32_t opb_ranges[8] = { 0,
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cpu_to_be32(lpcm_addr >> 32),
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cpu_to_be32((uint32_t)lpcm_addr),
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cpu_to_be32(PNV9_LPCM_SIZE / 2),
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cpu_to_be32(PNV9_LPCM_SIZE / 2),
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cpu_to_be32(lpcm_size / 2),
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cpu_to_be32(lpcm_size / 2),
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cpu_to_be32(lpcm_addr >> 32),
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cpu_to_be32(PNV9_LPCM_SIZE / 2),
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cpu_to_be32(PNV9_LPCM_SIZE / 2),
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cpu_to_be32(lpcm_size / 2),
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cpu_to_be32(lpcm_size / 2),
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};
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uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32),
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cpu_to_be32((uint32_t)lpcm_addr),
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cpu_to_be32(PNV9_LPCM_SIZE >> 32),
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cpu_to_be32((uint32_t)PNV9_LPCM_SIZE),
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cpu_to_be32(lpcm_size >> 32),
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cpu_to_be32((uint32_t)lpcm_size),
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};
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uint32_t lpc_ranges[12] = { 0, 0,
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cpu_to_be32(LPC_MEM_OPB_ADDR),
···
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.class_init = pnv_lpc_power9_class_init,
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};
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static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "PowerNV LPC Controller POWER10";
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}
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static const TypeInfo pnv_lpc_power10_info = {
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.name = TYPE_PNV10_LPC,
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.parent = TYPE_PNV9_LPC,
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.class_init = pnv_lpc_power10_class_init,
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};
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static void pnv_lpc_realize(DeviceState *dev, Error **errp)
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{
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PnvLpcController *lpc = PNV_LPC(dev);
···
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type_register_static(&pnv_lpc_info);
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type_register_static(&pnv_lpc_power8_info);
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type_register_static(&pnv_lpc_power9_info);
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type_register_static(&pnv_lpc_power10_info);
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}
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type_init(pnv_lpc_register_types)
+4
include/hw/ppc/pnv.h
+4
include/hw/ppc/pnv.h
···
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/*< public >*/
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Pnv9Psi psi;
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PnvLpcController lpc;
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} Pnv10Chip;
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typedef struct PnvChipClass {
···
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#define PNV10_XSCOM_SIZE 0x0000000400000000ull
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#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
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#define PNV10_LPCM_SIZE 0x0000000100000000ull
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#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
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#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
+5
-1
include/hw/ppc/pnv_lpc.h
+5
-1
include/hw/ppc/pnv_lpc.h
···
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#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
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#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
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#define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
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#define PNV10_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV10_LPC)
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typedef struct PnvLpcController {
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DeviceState parent;
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···
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struct PnvChip;
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ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
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int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
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int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset,
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uint64_t lpcm_addr, uint64_t lpcm_size);
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#endif /* PPC_PNV_LPC_H */