jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/rx: Register R5F562N7 and R5F562N8 MCUs
Make the current TYPE_RX62N_MCU an abstract class, and
generate TYPE_R5F562N7_MCU and TYPE_R5F562N8_MCU models.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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hw/rx/rx62n.c
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hw/rx/rx62n.c
···
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* (Rev.1.40 R01UH0033EJ0140)
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*
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* Copyright (c) 2019 Yoshinori Sato
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* Copyright (c) 2020 Philippe Mathieu-Daudé
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
···
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#define RX62N_TMR_IRQ 174
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#define RX62N_CMT_IRQ 28
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#define RX62N_SCI_IRQ 214
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#define RX62N_XTAL_MIN_HZ (8 * 1000 * 1000)
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#define RX62N_XTAL_MAX_HZ (14 * 1000 * 1000)
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#define RX62N_PCLK_MAX_HZ (50 * 1000 * 1000)
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typedef struct RX62NClass {
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/*< private >*/
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DeviceClass parent_class;
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/*< public >*/
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const char *name;
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uint64_t ram_size;
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uint64_t rom_flash_size;
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uint64_t data_flash_size;
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} RX62NClass;
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#define RX62N_MCU_CLASS(klass) \
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OBJECT_CLASS_CHECK(RX62NClass, (klass), TYPE_RX62N_MCU)
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#define RX62N_MCU_GET_CLASS(obj) \
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OBJECT_GET_CLASS(RX62NClass, (obj), TYPE_RX62N_MCU)
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/*
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* IRQ -> IPR mapping table
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object_initialize_child(OBJECT(s), "tmr[*]",
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&s->tmr[unit], TYPE_RENESAS_TMR);
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tmr = SYS_BUS_DEVICE(&s->tmr[unit]);
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qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK);
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qdev_prop_set_uint64(DEVICE(tmr), "input-freq", s->pclk_freq_hz);
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sysbus_realize(tmr, &error_abort);
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irqbase = RX62N_TMR_IRQ + TMR_NR_IRQ * unit;
···
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object_initialize_child(OBJECT(s), "cmt[*]",
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&s->cmt[unit], TYPE_RENESAS_CMT);
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cmt = SYS_BUS_DEVICE(&s->cmt[unit]);
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qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK);
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qdev_prop_set_uint64(DEVICE(cmt), "input-freq", s->pclk_freq_hz);
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sysbus_realize(cmt, &error_abort);
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irqbase = RX62N_CMT_IRQ + CMT_NR_IRQ * unit;
···
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&s->sci[unit], TYPE_RENESAS_SCI);
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sci = SYS_BUS_DEVICE(&s->sci[unit]);
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qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit));
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qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK);
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qdev_prop_set_uint64(DEVICE(sci), "input-freq", s->pclk_freq_hz);
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sysbus_realize(sci, &error_abort);
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irqbase = RX62N_SCI_IRQ + SCI_NR_IRQ * unit;
···
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static void rx62n_realize(DeviceState *dev, Error **errp)
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{
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RX62NState *s = RX62N_MCU(dev);
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RX62NClass *rxc = RX62N_MCU_GET_CLASS(dev);
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if (s->xtal_freq_hz == 0) {
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error_setg(errp, "\"xtal-frequency-hz\" property must be provided.");
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return;
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}
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/* XTAL range: 8-14 MHz */
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if (s->xtal_freq_hz < RX62N_XTAL_MIN_HZ
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|| s->xtal_freq_hz > RX62N_XTAL_MAX_HZ) {
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error_setg(errp, "\"xtal-frequency-hz\" property in incorrect range.");
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return;
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}
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/* Use a 4x fixed multiplier */
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s->pclk_freq_hz = 4 * s->xtal_freq_hz;
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/* PCLK range: 8-50 MHz */
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assert(s->pclk_freq_hz <= RX62N_PCLK_MAX_HZ);
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memory_region_init_ram(&s->iram, OBJECT(dev), "iram",
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RX62N_IRAM_SIZE, &error_abort);
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rxc->ram_size, &error_abort);
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memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram);
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memory_region_init_rom(&s->d_flash, OBJECT(dev), "flash-data",
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RX62N_DFLASH_SIZE, &error_abort);
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rxc->data_flash_size, &error_abort);
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memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash);
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memory_region_init_rom(&s->c_flash, OBJECT(dev), "flash-code",
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RX62N_CFLASH_SIZE, &error_abort);
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rxc->rom_flash_size, &error_abort);
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memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash);
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if (!s->kernel) {
···
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DEFINE_PROP_LINK("main-bus", RX62NState, sysmem, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false),
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DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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···
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device_class_set_props(dc, rx62n_properties);
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}
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static const TypeInfo rx62n_info = {
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.name = TYPE_RX62N_MCU,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(RX62NState),
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.class_init = rx62n_class_init,
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static void r5f562n7_class_init(ObjectClass *oc, void *data)
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{
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RX62NClass *rxc = RX62N_MCU_CLASS(oc);
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rxc->ram_size = 64 * KiB;
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rxc->rom_flash_size = 384 * KiB;
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rxc->data_flash_size = 32 * KiB;
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};
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static void rx62n_register_types(void)
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static void r5f562n8_class_init(ObjectClass *oc, void *data)
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{
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type_register_static(&rx62n_info);
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}
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RX62NClass *rxc = RX62N_MCU_CLASS(oc);
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type_init(rx62n_register_types)
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rxc->ram_size = 96 * KiB;
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rxc->rom_flash_size = 512 * KiB;
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rxc->data_flash_size = 32 * KiB;
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};
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static const TypeInfo rx62n_types[] = {
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{
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.name = TYPE_R5F562N7_MCU,
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.parent = TYPE_RX62N_MCU,
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.class_init = r5f562n7_class_init,
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}, {
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.name = TYPE_R5F562N8_MCU,
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.parent = TYPE_RX62N_MCU,
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.class_init = r5f562n8_class_init,
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}, {
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.name = TYPE_RX62N_MCU,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(RX62NState),
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.class_size = sizeof(RX62NClass),
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.class_init = rx62n_class_init,
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.abstract = true,
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}
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};
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DEFINE_TYPES(rx62n_types)
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include/hw/rx/rx62n.h
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include/hw/rx/rx62n.h
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#define TYPE_RX62N_MCU "rx62n-mcu"
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#define RX62N_MCU(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N_MCU)
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#define TYPE_R5F562N7_MCU "r5f562n7-mcu"
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#define TYPE_R5F562N8_MCU "r5f562n8-mcu"
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#define RX62N_NR_TMR 2
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#define RX62N_NR_CMT 2
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#define RX62N_NR_SCI 6
···
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MemoryRegion iomem3;
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MemoryRegion c_flash;
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qemu_irq irq[NR_IRQS];
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} RX62NState;
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/*
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* RX62N Internal Memory
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* It is the value of R5F562N8.
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* Please change the size for R5F562N7.
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*/
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#define RX62N_IRAM_SIZE (96 * KiB)
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#define RX62N_DFLASH_SIZE (32 * KiB)
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#define RX62N_CFLASH_SIZE (512 * KiB)
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#define RX62N_PCLK (48 * 1000 * 1000)
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/* Input Clock (XTAL) frequency */
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uint32_t xtal_freq_hz;
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/* Peripheral Module Clock frequency */
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uint32_t pclk_freq_hz;
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} RX62NState;
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#endif