jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
i.MX: Add i.MX6 System Reset Controller device.
This controller is also present in i.MX5X devices but they are not
yet emulated by QEMU.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Jean-Christophe DUBOIS
and committed by
Peter Maydell
19830574
825482ad
+338
+1
hw/misc/Makefile.objs
+1
hw/misc/Makefile.objs
···
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obj-$(CONFIG_IMX) += imx31_ccm.o
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obj-$(CONFIG_IMX) += imx25_ccm.o
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obj-$(CONFIG_IMX) += imx6_ccm.o
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obj-$(CONFIG_IMX) += imx6_src.o
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obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
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obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
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obj-$(CONFIG_MAINSTONE) += mst_fpga.o
+264
hw/misc/imx6_src.c
+264
hw/misc/imx6_src.c
···
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/*
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* IMX6 System Reset Controller
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*
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* Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/imx6_src.h"
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#include "sysemu/sysemu.h"
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#include "qemu/bitops.h"
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#include "arm-powerctl.h"
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#ifndef DEBUG_IMX6_SRC
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#define DEBUG_IMX6_SRC 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX6_SRC) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX6_SRC, \
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__func__, ##args); \
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} \
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} while (0)
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static char const *imx6_src_reg_name(uint32_t reg)
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{
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static char unknown[20];
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switch (reg) {
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case SRC_SCR:
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return "SRC_SCR";
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case SRC_SBMR1:
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return "SRC_SBMR1";
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case SRC_SRSR:
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return "SRC_SRSR";
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case SRC_SISR:
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return "SRC_SISR";
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case SRC_SIMR:
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return "SRC_SIMR";
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case SRC_SBMR2:
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return "SRC_SBMR2";
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case SRC_GPR1:
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return "SRC_GPR1";
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case SRC_GPR2:
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return "SRC_GPR2";
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case SRC_GPR3:
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return "SRC_GPR3";
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case SRC_GPR4:
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return "SRC_GPR4";
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case SRC_GPR5:
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return "SRC_GPR5";
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case SRC_GPR6:
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return "SRC_GPR6";
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case SRC_GPR7:
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return "SRC_GPR7";
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case SRC_GPR8:
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return "SRC_GPR8";
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case SRC_GPR9:
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return "SRC_GPR9";
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case SRC_GPR10:
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return "SRC_GPR10";
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default:
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sprintf(unknown, "%d ?", reg);
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return unknown;
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}
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}
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static const VMStateDescription vmstate_imx6_src = {
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.name = TYPE_IMX6_SRC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, IMX6SRCState, SRC_MAX),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx6_src_reset(DeviceState *dev)
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{
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IMX6SRCState *s = IMX6_SRC(dev);
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DPRINTF("\n");
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memset(s->regs, 0, sizeof(s->regs));
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/* Set reset values */
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s->regs[SRC_SCR] = 0x521;
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s->regs[SRC_SRSR] = 0x1;
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s->regs[SRC_SIMR] = 0x1F;
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}
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static uint64_t imx6_src_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t value = 0;
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IMX6SRCState *s = (IMX6SRCState *)opaque;
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uint32_t index = offset >> 2;
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if (index < SRC_MAX) {
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value = s->regs[index];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX6_SRC, __func__, offset);
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}
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DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx6_src_reg_name(index), value);
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return value;
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}
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static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMX6SRCState *s = (IMX6SRCState *)opaque;
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uint32_t index = offset >> 2;
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unsigned long change_mask;
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unsigned long current_value = value;
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if (index >= SRC_MAX) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX6_SRC, __func__, offset);
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return;
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}
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DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx6_src_reg_name(index),
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(uint32_t)current_value);
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change_mask = s->regs[index] ^ (uint32_t)current_value;
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switch (index) {
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case SRC_SCR:
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/*
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* On real hardware when the system reset controller starts a
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* secondary CPU it runs through some boot ROM code which reads
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* the SRC_GPRX registers controlling the start address and branches
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* to it.
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* Here we are taking a short cut and branching directly to the
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* requested address (we don't want to run the boot ROM code inside
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* QEMU)
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*/
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if (EXTRACT(change_mask, CORE3_ENABLE)) {
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if (EXTRACT(current_value, CORE3_ENABLE)) {
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/* CORE 3 is brought up */
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arm_set_cpu_on(3, s->regs[SRC_GPR7], s->regs[SRC_GPR8],
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3, false);
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} else {
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/* CORE 3 is shut down */
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arm_set_cpu_off(3);
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}
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/* We clear the reset bits as the processor changed state */
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clear_bit(CORE3_RST_SHIFT, ¤t_value);
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clear_bit(CORE3_RST_SHIFT, &change_mask);
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}
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if (EXTRACT(change_mask, CORE2_ENABLE)) {
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if (EXTRACT(current_value, CORE2_ENABLE)) {
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/* CORE 2 is brought up */
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arm_set_cpu_on(2, s->regs[SRC_GPR5], s->regs[SRC_GPR6],
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3, false);
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} else {
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/* CORE 3 is shut down */
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arm_set_cpu_off(2);
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}
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/* We clear the reset bits as the processor changed state */
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clear_bit(CORE2_RST_SHIFT, ¤t_value);
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clear_bit(CORE2_RST_SHIFT, &change_mask);
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}
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if (EXTRACT(change_mask, CORE1_ENABLE)) {
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if (EXTRACT(current_value, CORE1_ENABLE)) {
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/* CORE 1 is brought up */
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arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
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3, false);
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} else {
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/* CORE 3 is shut down */
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arm_set_cpu_off(1);
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}
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/* We clear the reset bits as the processor changed state */
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clear_bit(CORE1_RST_SHIFT, ¤t_value);
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clear_bit(CORE1_RST_SHIFT, &change_mask);
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}
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if (EXTRACT(change_mask, CORE0_RST)) {
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arm_reset_cpu(0);
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clear_bit(CORE0_RST_SHIFT, ¤t_value);
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}
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if (EXTRACT(change_mask, CORE1_RST)) {
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arm_reset_cpu(1);
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clear_bit(CORE1_RST_SHIFT, ¤t_value);
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}
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if (EXTRACT(change_mask, CORE2_RST)) {
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arm_reset_cpu(2);
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clear_bit(CORE2_RST_SHIFT, ¤t_value);
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}
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if (EXTRACT(change_mask, CORE3_RST)) {
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arm_reset_cpu(3);
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clear_bit(CORE3_RST_SHIFT, ¤t_value);
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}
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if (EXTRACT(change_mask, SW_IPU2_RST)) {
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/* We pretend the IPU2 is reset */
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clear_bit(SW_IPU2_RST_SHIFT, ¤t_value);
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}
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if (EXTRACT(change_mask, SW_IPU1_RST)) {
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/* We pretend the IPU1 is reset */
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clear_bit(SW_IPU1_RST_SHIFT, ¤t_value);
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}
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s->regs[index] = current_value;
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break;
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default:
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s->regs[index] = current_value;
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break;
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}
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}
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static const struct MemoryRegionOps imx6_src_ops = {
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.read = imx6_src_read,
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.write = imx6_src_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx6_src_realize(DeviceState *dev, Error **errp)
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{
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IMX6SRCState *s = IMX6_SRC(dev);
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memory_region_init_io(&s->iomem, OBJECT(dev), &imx6_src_ops, s,
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TYPE_IMX6_SRC, 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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}
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static void imx6_src_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx6_src_realize;
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dc->reset = imx6_src_reset;
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dc->vmsd = &vmstate_imx6_src;
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dc->desc = "i.MX6 System Reset Controller";
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}
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static const TypeInfo imx6_src_info = {
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.name = TYPE_IMX6_SRC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMX6SRCState),
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.class_init = imx6_src_class_init,
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};
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static void imx6_src_register_types(void)
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{
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type_register_static(&imx6_src_info);
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}
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type_init(imx6_src_register_types)
+73
include/hw/misc/imx6_src.h
+73
include/hw/misc/imx6_src.h
···
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/*
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* IMX6 System Reset Controller
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*
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* Copyright (C) 2012 NICTA
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef IMX6_SRC_H
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#define IMX6_SRC_H
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#include "hw/sysbus.h"
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#include "qemu/bitops.h"
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#define SRC_SCR 0
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#define SRC_SBMR1 1
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#define SRC_SRSR 2
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#define SRC_SISR 5
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#define SRC_SIMR 6
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#define SRC_SBMR2 7
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#define SRC_GPR1 8
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#define SRC_GPR2 9
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#define SRC_GPR3 10
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#define SRC_GPR4 11
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#define SRC_GPR5 12
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#define SRC_GPR6 13
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#define SRC_GPR7 14
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#define SRC_GPR8 15
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#define SRC_GPR9 16
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#define SRC_GPR10 17
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#define SRC_MAX 18
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/* SRC_SCR */
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#define CORE3_ENABLE_SHIFT 24
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#define CORE3_ENABLE_LENGTH 1
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#define CORE2_ENABLE_SHIFT 23
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#define CORE2_ENABLE_LENGTH 1
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#define CORE1_ENABLE_SHIFT 22
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#define CORE1_ENABLE_LENGTH 1
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#define CORE3_RST_SHIFT 16
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#define CORE3_RST_LENGTH 1
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#define CORE2_RST_SHIFT 15
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#define CORE2_RST_LENGTH 1
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#define CORE1_RST_SHIFT 14
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#define CORE1_RST_LENGTH 1
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#define CORE0_RST_SHIFT 13
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#define CORE0_RST_LENGTH 1
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#define SW_IPU1_RST_SHIFT 3
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#define SW_IPU1_RST_LENGTH 1
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#define SW_IPU2_RST_SHIFT 12
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#define SW_IPU2_RST_LENGTH 1
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#define WARM_RST_ENABLE_SHIFT 0
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#define WARM_RST_ENABLE_LENGTH 1
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#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
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#define TYPE_IMX6_SRC "imx6.src"
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#define IMX6_SRC(obj) OBJECT_CHECK(IMX6SRCState, (obj), TYPE_IMX6_SRC)
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typedef struct IMX6SRCState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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uint32_t regs[SRC_MAX];
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} IMX6SRCState;
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#endif /* IMX6_SRC_H */