qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

tcg/i386: Support vector absolute value

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

+16 -1
+1 -1
tcg/i386/tcg-target.h
··· 182 182 #define TCG_TARGET_HAS_orc_vec 0 183 183 #define TCG_TARGET_HAS_not_vec 0 184 184 #define TCG_TARGET_HAS_neg_vec 0 185 - #define TCG_TARGET_HAS_abs_vec 0 185 + #define TCG_TARGET_HAS_abs_vec 1 186 186 #define TCG_TARGET_HAS_shi_vec 1 187 187 #define TCG_TARGET_HAS_shs_vec 1 188 188 #define TCG_TARGET_HAS_shv_vec have_avx2
+15
tcg/i386/tcg-target.inc.c
··· 369 369 #define OPC_MOVSLQ (0x63 | P_REXW) 370 370 #define OPC_MOVZBL (0xb6 | P_EXT) 371 371 #define OPC_MOVZWL (0xb7 | P_EXT) 372 + #define OPC_PABSB (0x1c | P_EXT38 | P_DATA16) 373 + #define OPC_PABSW (0x1d | P_EXT38 | P_DATA16) 374 + #define OPC_PABSD (0x1e | P_EXT38 | P_DATA16) 372 375 #define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) 373 376 #define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) 374 377 #define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) ··· 2741 2744 static int const sars_insn[4] = { 2742 2745 OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 2743 2746 }; 2747 + static int const abs_insn[4] = { 2748 + /* TODO: AVX512 adds support for MO_64. */ 2749 + OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2 2750 + }; 2744 2751 2745 2752 TCGType type = vecl + TCG_TYPE_V64; 2746 2753 int insn, sub; ··· 2829 2836 insn = OPC_PUNPCKLDQ; 2830 2837 goto gen_simd; 2831 2838 #endif 2839 + case INDEX_op_abs_vec: 2840 + insn = abs_insn[vece]; 2841 + a2 = a1; 2842 + a1 = 0; 2843 + goto gen_simd; 2832 2844 gen_simd: 2833 2845 tcg_debug_assert(insn != OPC_UD2); 2834 2846 if (type == TCG_TYPE_V256) { ··· 3206 3218 case INDEX_op_dup2_vec: 3207 3219 #endif 3208 3220 return &x_x_x; 3221 + case INDEX_op_abs_vec: 3209 3222 case INDEX_op_dup_vec: 3210 3223 case INDEX_op_shli_vec: 3211 3224 case INDEX_op_shri_vec: ··· 3283 3296 case INDEX_op_umin_vec: 3284 3297 case INDEX_op_umax_vec: 3285 3298 return vece <= MO_32 ? 1 : -1; 3299 + case INDEX_op_abs_vec: 3300 + return vece <= MO_32; 3286 3301 3287 3302 default: 3288 3303 return 0;