jcs.org / qemu
qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio
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hw/misc/iotkit-secctl: Support 4 internal MPCs

The SSE-200 has 4 banks of SRAM, each with its own internal
Memory Protection Controller. The interrupt status for these
extra MPCs appears in the same security controller SECMPCINTSTATUS
register as the MPC for the IoTKit's single SRAM bank. Enhance the
iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE
variant in use does not have all 4 MPCs then the unused inputs will
simply result in the SECMPCINTSTATUS bits being zero as required.)

The hardcoded constant "1"s in armsse.c indicate the actual number
of SRAM MPCs the IoTKit has, and will be replaced in the following
commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-9-peter.maydell@linaro.org

Peter Maydell 0a78d7eb 6eee5d24

+9 -8
+3 -3
hw/arm/armsse.c
··· 138 138 sizeof(s->mpc_irq_orgate), TYPE_OR_IRQ, 139 139 &error_abort, NULL); 140 140 141 - for (i = 0; i < ARRAY_SIZE(s->mpc_irq_splitter); i++) { 141 + for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) { 142 142 char *name = g_strdup_printf("mpc-irq-splitter-%d", i); 143 143 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 144 144 ··· 363 363 364 364 /* We must OR together lines from the MPC splitters to go to the NVIC */ 365 365 object_property_set_int(OBJECT(&s->mpc_irq_orgate), 366 - IOTS_NUM_EXP_MPC + IOTS_NUM_MPC, "num-lines", &err); 366 + IOTS_NUM_EXP_MPC + 1, "num-lines", &err); 367 367 if (err) { 368 368 error_propagate(errp, err); 369 369 return; ··· 636 636 } 637 637 638 638 /* Wire up the splitters for the MPC IRQs */ 639 - for (i = 0; i < IOTS_NUM_EXP_MPC + IOTS_NUM_MPC; i++) { 639 + for (i = 0; i < IOTS_NUM_EXP_MPC + 1; i++) { 640 640 SplitIRQ *splitter = &s->mpc_irq_splitter[i]; 641 641 DeviceState *dev_splitter = DEVICE(splitter); 642 642
+3 -2
hw/misc/iotkit-secctl.c
··· 600 600 { 601 601 IoTKitSecCtl *s = IOTKIT_SECCTL(opaque); 602 602 603 - s->mpcintstatus = deposit32(s->mpcintstatus, 0, 1, !!level); 603 + s->mpcintstatus = deposit32(s->mpcintstatus, n, 1, !!level); 604 604 } 605 605 606 606 static void iotkit_secctl_mpcexp_status(void *opaque, int n, int level) ··· 686 686 qdev_init_gpio_out_named(dev, &s->sec_resp_cfg, "sec_resp_cfg", 1); 687 687 qdev_init_gpio_out_named(dev, &s->nsc_cfg_irq, "nsc_cfg", 1); 688 688 689 - qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 1); 689 + qdev_init_gpio_in_named(dev, iotkit_secctl_mpc_status, "mpc_status", 690 + IOTS_NUM_MPC); 690 691 qdev_init_gpio_in_named(dev, iotkit_secctl_mpcexp_status, 691 692 "mpcexp_status", IOTS_NUM_EXP_MPC); 692 693
+3 -3
include/hw/misc/iotkit-secctl.h
··· 40 40 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable 41 41 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear 42 42 * + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status 43 - * Controlling the MPC in the IoTKit: 44 - * + named GPIO input mpc_status 43 + * Controlling the (up to) 4 MPCs in the IoTKit/SSE: 44 + * + named GPIO inputs mpc_status[0..3] 45 45 * Controlling each of the 16 expansion MPCs which a system using the IoTKit 46 46 * might provide: 47 47 * + named GPIO inputs mpcexp_status[0..15] ··· 67 67 #define IOTS_NUM_APB_EXP_PPC 4 68 68 #define IOTS_NUM_AHB_EXP_PPC 4 69 69 #define IOTS_NUM_EXP_MPC 16 70 - #define IOTS_NUM_MPC 1 70 + #define IOTS_NUM_MPC 4 71 71 #define IOTS_NUM_EXP_MSC 16 72 72 73 73 typedef struct IoTKitSecCtl IoTKitSecCtl;