jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
hw/usb: Add basic i.MX USB Phy support
Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
and i.MX7 SoCs.
The only support really needed - at least to boot Linux - is support
for soft reset, which needs to reset various registers to their initial
value. Otherwise, just record register values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
authored by
Guenter Roeck
and committed by
Peter Maydell
0701a5ef
a98135f7
+288
+2
MAINTAINERS
+2
MAINTAINERS
+1
hw/arm/Kconfig
+1
hw/arm/Kconfig
+5
hw/usb/Kconfig
+5
hw/usb/Kconfig
+2
hw/usb/Makefile.objs
+2
hw/usb/Makefile.objs
+225
hw/usb/imx-usb-phy.c
+225
hw/usb/imx-usb-phy.c
···
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/*
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* i.MX USB PHY
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*
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* Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* We need to implement basic reset control in the PHY control register.
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* For everything else, it is sufficient to set whatever is written.
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*/
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#include "qemu/osdep.h"
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#include "hw/usb/imx-usb-phy.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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+
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static const VMStateDescription vmstate_imx_usbphy = {
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.name = TYPE_IMX_USBPHY,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_usbphy_softreset(IMXUSBPHYState *s)
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{
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s->usbphy[USBPHY_PWD] = 0x001e1c00;
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s->usbphy[USBPHY_TX] = 0x10060607;
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s->usbphy[USBPHY_RX] = 0x00000000;
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s->usbphy[USBPHY_CTRL] = 0xc0200000;
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}
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static void imx_usbphy_reset(DeviceState *dev)
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{
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IMXUSBPHYState *s = IMX_USBPHY(dev);
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s->usbphy[USBPHY_STATUS] = 0x00000000;
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s->usbphy[USBPHY_DEBUG] = 0x7f180000;
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s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
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s->usbphy[USBPHY_DEBUG1] = 0x00001000;
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s->usbphy[USBPHY_VERSION] = 0x04020000;
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+
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imx_usbphy_softreset(s);
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}
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static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
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{
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IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
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uint32_t index = offset >> 2;
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uint32_t value;
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switch (index) {
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case USBPHY_PWD_SET:
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case USBPHY_TX_SET:
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case USBPHY_RX_SET:
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case USBPHY_CTRL_SET:
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case USBPHY_DEBUG_SET:
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case USBPHY_DEBUG1_SET:
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/*
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* All REG_NAME_SET register access are in fact targeting the
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* REG_NAME register.
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*/
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value = s->usbphy[index - 1];
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break;
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case USBPHY_PWD_CLR:
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case USBPHY_TX_CLR:
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case USBPHY_RX_CLR:
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case USBPHY_CTRL_CLR:
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case USBPHY_DEBUG_CLR:
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case USBPHY_DEBUG1_CLR:
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/*
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* All REG_NAME_CLR register access are in fact targeting the
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* REG_NAME register.
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*/
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value = s->usbphy[index - 2];
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break;
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case USBPHY_PWD_TOG:
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case USBPHY_TX_TOG:
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case USBPHY_RX_TOG:
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case USBPHY_CTRL_TOG:
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case USBPHY_DEBUG_TOG:
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case USBPHY_DEBUG1_TOG:
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/*
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* All REG_NAME_TOG register access are in fact targeting the
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* REG_NAME register.
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*/
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value = s->usbphy[index - 3];
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break;
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default:
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value = s->usbphy[index];
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break;
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}
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return (uint64_t)value;
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}
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static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
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uint32_t index = offset >> 2;
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switch (index) {
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case USBPHY_CTRL:
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s->usbphy[index] = value;
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if (value & USBPHY_CTRL_SFTRST) {
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imx_usbphy_softreset(s);
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}
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break;
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case USBPHY_PWD:
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case USBPHY_TX:
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case USBPHY_RX:
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case USBPHY_STATUS:
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case USBPHY_DEBUG:
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case USBPHY_DEBUG1:
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s->usbphy[index] = value;
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break;
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case USBPHY_CTRL_SET:
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s->usbphy[index - 1] |= value;
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if (value & USBPHY_CTRL_SFTRST) {
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imx_usbphy_softreset(s);
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}
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break;
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case USBPHY_PWD_SET:
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case USBPHY_TX_SET:
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case USBPHY_RX_SET:
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case USBPHY_DEBUG_SET:
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case USBPHY_DEBUG1_SET:
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/*
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* All REG_NAME_SET register access are in fact targeting the
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* REG_NAME register. So we change the value of the REG_NAME
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* register, setting bits passed in the value.
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*/
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s->usbphy[index - 1] |= value;
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break;
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case USBPHY_PWD_CLR:
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case USBPHY_TX_CLR:
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case USBPHY_RX_CLR:
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case USBPHY_CTRL_CLR:
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case USBPHY_DEBUG_CLR:
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case USBPHY_DEBUG1_CLR:
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/*
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* All REG_NAME_CLR register access are in fact targeting the
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* REG_NAME register. So we change the value of the REG_NAME
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* register, unsetting bits passed in the value.
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*/
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s->usbphy[index - 2] &= ~value;
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break;
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case USBPHY_CTRL_TOG:
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s->usbphy[index - 3] ^= value;
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if ((value & USBPHY_CTRL_SFTRST) &&
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(s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
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imx_usbphy_softreset(s);
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}
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break;
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case USBPHY_PWD_TOG:
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case USBPHY_TX_TOG:
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case USBPHY_RX_TOG:
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case USBPHY_DEBUG_TOG:
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case USBPHY_DEBUG1_TOG:
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/*
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* All REG_NAME_TOG register access are in fact targeting the
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* REG_NAME register. So we change the value of the REG_NAME
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* register, toggling bits passed in the value.
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*/
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s->usbphy[index - 3] ^= value;
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break;
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default:
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/* Other registers are read-only */
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break;
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}
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}
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static const struct MemoryRegionOps imx_usbphy_ops = {
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.read = imx_usbphy_read,
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.write = imx_usbphy_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx_usbphy_realize(DeviceState *dev, Error **errp)
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{
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IMXUSBPHYState *s = IMX_USBPHY(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
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"imx-usbphy", 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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}
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static void imx_usbphy_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = imx_usbphy_reset;
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dc->vmsd = &vmstate_imx_usbphy;
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dc->desc = "i.MX USB PHY Module";
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dc->realize = imx_usbphy_realize;
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}
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static const TypeInfo imx_usbphy_info = {
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.name = TYPE_IMX_USBPHY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXUSBPHYState),
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.class_init = imx_usbphy_class_init,
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};
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static void imx_usbphy_register_types(void)
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{
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type_register_static(&imx_usbphy_info);
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}
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type_init(imx_usbphy_register_types)
+53
include/hw/usb/imx-usb-phy.h
+53
include/hw/usb/imx-usb-phy.h
···
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#ifndef IMX_USB_PHY_H
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#define IMX_USB_PHY_H
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#include "hw/sysbus.h"
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#include "qemu/bitops.h"
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enum IMXUsbPhyRegisters {
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USBPHY_PWD,
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USBPHY_PWD_SET,
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USBPHY_PWD_CLR,
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USBPHY_PWD_TOG,
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USBPHY_TX,
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USBPHY_TX_SET,
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USBPHY_TX_CLR,
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USBPHY_TX_TOG,
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USBPHY_RX,
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USBPHY_RX_SET,
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USBPHY_RX_CLR,
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USBPHY_RX_TOG,
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USBPHY_CTRL,
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USBPHY_CTRL_SET,
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USBPHY_CTRL_CLR,
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USBPHY_CTRL_TOG,
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USBPHY_STATUS,
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USBPHY_DEBUG = 0x14,
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USBPHY_DEBUG_SET,
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USBPHY_DEBUG_CLR,
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USBPHY_DEBUG_TOG,
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USBPHY_DEBUG0_STATUS,
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USBPHY_DEBUG1 = 0x1c,
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USBPHY_DEBUG1_SET,
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USBPHY_DEBUG1_CLR,
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USBPHY_DEBUG1_TOG,
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USBPHY_VERSION,
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USBPHY_MAX
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};
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#define USBPHY_CTRL_SFTRST BIT(31)
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#define TYPE_IMX_USBPHY "imx.usbphy"
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#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
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typedef struct IMXUSBPHYState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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uint32_t usbphy[USBPHY_MAX];
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} IMXUSBPHYState;
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#endif /* IMX_USB_PHY_H */