qemu with hax to log dma reads & writes jcs.org/2018/11/12/vfio

sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1

I'm converting from qdev_set_parent_bus()/realize to qdev_realize();
recent commit "qdev: Convert uses of qdev_set_parent_bus() with
Coccinelle" explains why.

sysbus_init_child_obj() is a wrapper around
object_initialize_child_with_props() and qdev_set_parent_bus(). It
passes no properties.

Convert sysbus_init_child_obj()/realize to object_initialize_child()/
qdev_realize().

Coccinelle script:

@@
expression parent, name, size, type, errp;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, &child, size, type);
+ sysbus_init_child_XXX(parent, name, &child, size, type);
...
- object_property_set_bool(OBJECT(&child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(&child), errp);

@@
expression parent, name, size, type, errp;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
...
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);

@@
expression parent, name, size, type;
expression child;
expression dev;
expression expr;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
...
dev = DEVICE(child);
... when != dev = expr;
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);

@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)

@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-48-armbru@redhat.com>

+96 -132
+2 -3
hw/arm/bcm2835_peripherals.c
··· 27 27 UnimplementedDeviceState *uds, 28 28 const char *name, hwaddr ofs, hwaddr size) 29 29 { 30 - sysbus_init_child_obj(OBJECT(ps), name, uds, sizeof(*uds), 31 - TYPE_UNIMPLEMENTED_DEVICE); 30 + object_initialize_child(OBJECT(ps), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 32 31 qdev_prop_set_string(DEVICE(uds), "name", name); 33 32 qdev_prop_set_uint64(DEVICE(uds), "size", size); 34 - object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 33 + sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 35 34 memory_region_add_subregion_overlap(&ps->peri_mr, ofs, 36 35 sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0), -1000); 37 36 }
+3 -4
hw/arm/exynos4_boards.c
··· 128 128 exynos4_boards_init_ram(s, get_system_memory(), 129 129 exynos4_board_ram_size[board_type]); 130 130 131 - sysbus_init_child_obj(OBJECT(machine), "soc", 132 - &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); 133 - object_property_set_bool(OBJECT(&s->soc), true, "realized", 134 - &error_fatal); 131 + object_initialize_child(OBJECT(machine), "soc", &s->soc, 132 + TYPE_EXYNOS4210_SOC); 133 + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 135 134 136 135 return s; 137 136 }
+22 -28
hw/arm/mps2-tz.c
··· 174 174 */ 175 175 UnimplementedDeviceState *uds = opaque; 176 176 177 - sysbus_init_child_obj(OBJECT(mms), name, uds, sizeof(*uds), 178 - TYPE_UNIMPLEMENTED_DEVICE); 177 + object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 179 178 qdev_prop_set_string(DEVICE(uds), "name", name); 180 179 qdev_prop_set_uint64(DEVICE(uds), "size", size); 181 - object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 180 + sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 182 181 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 183 182 } 184 183 ··· 193 192 SysBusDevice *s; 194 193 DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); 195 194 196 - sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(*uart), 197 - TYPE_CMSDK_APB_UART); 195 + object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); 198 196 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 199 197 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); 200 - object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); 198 + sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 201 199 s = SYS_BUS_DEVICE(uart); 202 200 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); 203 201 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); ··· 214 212 DeviceState *sccdev; 215 213 MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); 216 214 217 - sysbus_init_child_obj(OBJECT(mms), "scc", scc, sizeof(*scc), 218 - TYPE_MPS2_SCC); 215 + object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); 219 216 sccdev = DEVICE(scc); 220 217 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 221 218 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 222 219 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 223 - object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); 220 + sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); 224 221 return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); 225 222 } 226 223 ··· 229 226 { 230 227 MPS2FPGAIO *fpgaio = opaque; 231 228 232 - sysbus_init_child_obj(OBJECT(mms), "fpgaio", fpgaio, sizeof(*fpgaio), 233 - TYPE_MPS2_FPGAIO); 234 - object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); 229 + object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); 230 + sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); 235 231 return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); 236 232 } 237 233 ··· 267 263 268 264 memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); 269 265 270 - sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(*mpc), 271 - TYPE_TZ_MPC); 266 + object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 272 267 object_property_set_link(OBJECT(mpc), OBJECT(ssram), 273 268 "downstream", &error_fatal); 274 - object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); 269 + sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 275 270 /* Map the upstream end of the MPC into system memory */ 276 271 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 277 272 memory_region_add_subregion(get_system_memory(), rambase[i], upstream); ··· 310 305 * the MSC connects to the IoTKit AHB Slave Expansion port, so the 311 306 * DMA devices can see all devices and memory that the CPU does. 312 307 */ 313 - sysbus_init_child_obj(OBJECT(mms), mscname, msc, sizeof(*msc), TYPE_TZ_MSC); 308 + object_initialize_child(OBJECT(mms), mscname, msc, TYPE_TZ_MSC); 314 309 msc_downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(&mms->iotkit), 0); 315 310 object_property_set_link(OBJECT(msc), OBJECT(msc_downstream), 316 311 "downstream", &error_fatal); 317 312 object_property_set_link(OBJECT(msc), OBJECT(mms), 318 313 "idau", &error_fatal); 319 - object_property_set_bool(OBJECT(msc), true, "realized", &error_fatal); 314 + sysbus_realize(SYS_BUS_DEVICE(msc), &error_fatal); 320 315 321 316 qdev_connect_gpio_out_named(DEVICE(msc), "irq", 0, 322 317 qdev_get_gpio_in_named(iotkitdev, ··· 333 328 "cfg_sec_resp", 0)); 334 329 msc_upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(msc), 0); 335 330 336 - sysbus_init_child_obj(OBJECT(mms), name, dma, sizeof(*dma), TYPE_PL081); 331 + object_initialize_child(OBJECT(mms), name, dma, TYPE_PL081); 337 332 object_property_set_link(OBJECT(dma), OBJECT(msc_upstream), 338 333 "downstream", &error_fatal); 339 - object_property_set_bool(OBJECT(dma), true, "realized", &error_fatal); 334 + sysbus_realize(SYS_BUS_DEVICE(dma), &error_fatal); 340 335 341 336 s = SYS_BUS_DEVICE(dma); 342 337 /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ ··· 363 358 int i = spi - &mms->spi[0]; 364 359 SysBusDevice *s; 365 360 366 - sysbus_init_child_obj(OBJECT(mms), name, spi, sizeof(*spi), TYPE_PL022); 367 - object_property_set_bool(OBJECT(spi), true, "realized", &error_fatal); 361 + object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); 362 + sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); 368 363 s = SYS_BUS_DEVICE(spi); 369 364 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); 370 365 return sysbus_mmio_get_region(s, 0); ··· 393 388 exit(EXIT_FAILURE); 394 389 } 395 390 396 - sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 397 - sizeof(mms->iotkit), mmc->armsse_type); 391 + object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, 392 + mmc->armsse_type); 398 393 iotkitdev = DEVICE(&mms->iotkit); 399 394 object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), 400 395 "memory", &error_abort); 401 396 qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); 402 397 qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ); 403 - object_property_set_bool(OBJECT(&mms->iotkit), true, "realized", 404 - &error_fatal); 398 + sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); 405 399 406 400 /* 407 401 * The AN521 needs us to create splitters to feed the IRQ inputs ··· 549 543 int port; 550 544 char *gpioname; 551 545 552 - sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, 553 - sizeof(*ppc), TYPE_TZ_PPC); 546 + object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 547 + TYPE_TZ_PPC); 554 548 ppcdev = DEVICE(ppc); 555 549 556 550 for (port = 0; port < TZ_NUM_PORTS; port++) { ··· 569 563 g_free(portname); 570 564 } 571 565 572 - object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); 566 + sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 573 567 574 568 for (port = 0; port < TZ_NUM_PORTS; port++) { 575 569 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
+7 -12
hw/arm/mps2.c
··· 180 180 g_assert_not_reached(); 181 181 } 182 182 183 - sysbus_init_child_obj(OBJECT(mms), "armv7m", &mms->armv7m, 184 - sizeof(mms->armv7m), TYPE_ARMV7M); 183 + object_initialize_child(OBJECT(mms), "armv7m", &mms->armv7m, TYPE_ARMV7M); 185 184 armv7m = DEVICE(&mms->armv7m); 186 185 switch (mmc->fpga_type) { 187 186 case FPGA_AN385: ··· 197 196 qdev_prop_set_bit(armv7m, "enable-bitband", true); 198 197 object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), 199 198 "memory", &error_abort); 200 - object_property_set_bool(OBJECT(&mms->armv7m), true, "realized", 201 - &error_fatal); 199 + sysbus_realize(SYS_BUS_DEVICE(&mms->armv7m), &error_fatal); 202 200 203 201 create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); 204 202 create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); ··· 305 303 cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); 306 304 cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); 307 305 308 - sysbus_init_child_obj(OBJECT(mms), "dualtimer", &mms->dualtimer, 309 - sizeof(mms->dualtimer), TYPE_CMSDK_APB_DUALTIMER); 306 + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, 307 + TYPE_CMSDK_APB_DUALTIMER); 310 308 qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); 311 - object_property_set_bool(OBJECT(&mms->dualtimer), true, "realized", 312 - &error_fatal); 309 + sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); 313 310 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, 314 311 qdev_get_gpio_in(armv7m, 10)); 315 312 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); 316 313 317 - sysbus_init_child_obj(OBJECT(mms), "scc", &mms->scc, 318 - sizeof(mms->scc), TYPE_MPS2_SCC); 314 + object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); 319 315 sccdev = DEVICE(&mms->scc); 320 316 qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); 321 317 qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); 322 318 qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); 323 - object_property_set_bool(OBJECT(&mms->scc), true, "realized", 324 - &error_fatal); 319 + sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); 325 320 sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); 326 321 327 322 /* In hardware this is a LAN9220; the LAN9118 is software compatible
+17 -20
hw/arm/musca.c
··· 142 142 */ 143 143 UnimplementedDeviceState *uds = opaque; 144 144 145 - sysbus_init_child_obj(OBJECT(mms), name, uds, sizeof(*uds), 146 - TYPE_UNIMPLEMENTED_DEVICE); 145 + object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE); 147 146 qdev_prop_set_string(DEVICE(uds), "name", name); 148 147 qdev_prop_set_uint64(DEVICE(uds), "size", size); 149 - object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 148 + sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 150 149 return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 151 150 } 152 151 ··· 245 244 case MPC_CRYPTOISLAND: 246 245 /* We don't implement the CryptoIsland yet */ 247 246 uds = &mms->cryptoisland; 248 - sysbus_init_child_obj(OBJECT(mms), name, uds, sizeof(*uds), 249 - TYPE_UNIMPLEMENTED_DEVICE); 247 + object_initialize_child(OBJECT(mms), name, uds, 248 + TYPE_UNIMPLEMENTED_DEVICE); 250 249 qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name); 251 250 qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size); 252 - object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); 251 + sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal); 253 252 downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); 254 253 break; 255 254 default: 256 255 g_assert_not_reached(); 257 256 } 258 257 259 - sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(*mpc), 260 - TYPE_TZ_MPC); 258 + object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); 261 259 object_property_set_link(OBJECT(mpc), OBJECT(downstream), 262 260 "downstream", &error_fatal); 263 - object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); 261 + sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); 264 262 /* Map the upstream end of the MPC into system memory */ 265 263 upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); 266 264 memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream); ··· 279 277 { 280 278 PL031State *rtc = opaque; 281 279 282 - sysbus_init_child_obj(OBJECT(mms), name, rtc, sizeof(*rtc), TYPE_PL031); 283 - object_property_set_bool(OBJECT(rtc), true, "realized", &error_fatal); 280 + object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031); 281 + sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal); 284 282 sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39)); 285 283 return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0); 286 284 } ··· 293 291 int irqbase = 7 + i * 6; 294 292 SysBusDevice *s; 295 293 296 - sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(*uart), TYPE_PL011); 294 + object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011); 297 295 qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); 298 - object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); 296 + sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); 299 297 s = SYS_BUS_DEVICE(uart); 300 298 sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */ 301 299 sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */ ··· 373 371 exit(1); 374 372 } 375 373 376 - sysbus_init_child_obj(OBJECT(machine), "sse-200", &mms->sse, 377 - sizeof(mms->sse), TYPE_SSE200); 374 + object_initialize_child(OBJECT(machine), "sse-200", &mms->sse, 375 + TYPE_SSE200); 378 376 ssedev = DEVICE(&mms->sse); 379 377 object_property_set_link(OBJECT(&mms->sse), OBJECT(system_memory), 380 378 "memory", &error_fatal); ··· 390 388 qdev_prop_set_bit(ssedev, "CPU0_FPU", true); 391 389 qdev_prop_set_bit(ssedev, "CPU0_DSP", true); 392 390 } 393 - object_property_set_bool(OBJECT(&mms->sse), true, "realized", 394 - &error_fatal); 391 + sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal); 395 392 396 393 /* 397 394 * We need to create splitters to feed the IRQ inputs ··· 531 528 int port; 532 529 char *gpioname; 533 530 534 - sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, 535 - sizeof(*ppc), TYPE_TZ_PPC); 531 + object_initialize_child(OBJECT(machine), ppcinfo->name, ppc, 532 + TYPE_TZ_PPC); 536 533 ppcdev = DEVICE(ppc); 537 534 538 535 for (port = 0; port < TZ_NUM_PORTS; port++) { ··· 551 548 g_free(portname); 552 549 } 553 550 554 - object_property_set_bool(OBJECT(ppc), true, "realized", &error_fatal); 551 + sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal); 555 552 556 553 for (port = 0; port < TZ_NUM_PORTS; port++) { 557 554 const PPCPortInfo *pinfo = &ppcinfo->ports[port];
+3 -3
hw/arm/xlnx-versal-virt.c
··· 500 500 psci_conduit = QEMU_PSCI_CONDUIT_SMC; 501 501 } 502 502 503 - sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc, 504 - sizeof(s->soc), TYPE_XLNX_VERSAL); 503 + object_initialize_child(OBJECT(machine), "xlnx-versal", &s->soc, 504 + TYPE_XLNX_VERSAL); 505 505 object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), 506 506 "ddr", &error_abort); 507 507 object_property_set_int(OBJECT(&s->soc), psci_conduit, 508 508 "psci-conduit", &error_abort); 509 - object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); 509 + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); 510 510 511 511 fdt_create(s); 512 512 create_virtio_regions(s);
+15 -21
hw/arm/xlnx-versal.c
··· 62 62 int nr_apu_cpus = ARRAY_SIZE(s->fpd.apu.cpu); 63 63 int i; 64 64 65 - sysbus_init_child_obj(OBJECT(s), "apu-gic", 66 - &s->fpd.apu.gic, sizeof(s->fpd.apu.gic), 67 - gicv3_class_name()); 65 + object_initialize_child(OBJECT(s), "apu-gic", &s->fpd.apu.gic, 66 + gicv3_class_name()); 68 67 gicbusdev = SYS_BUS_DEVICE(&s->fpd.apu.gic); 69 68 gicdev = DEVICE(&s->fpd.apu.gic); 70 69 qdev_prop_set_uint32(gicdev, "revision", 3); ··· 74 73 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", 2); 75 74 qdev_prop_set_bit(gicdev, "has-security-extensions", true); 76 75 77 - object_property_set_bool(OBJECT(&s->fpd.apu.gic), true, "realized", 78 - &error_fatal); 76 + sysbus_realize(SYS_BUS_DEVICE(&s->fpd.apu.gic), &error_fatal); 79 77 80 78 for (i = 0; i < ARRAY_SIZE(addrs); i++) { 81 79 MemoryRegion *mr; ··· 133 131 DeviceState *dev; 134 132 MemoryRegion *mr; 135 133 136 - sysbus_init_child_obj(OBJECT(s), name, 137 - &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]), 138 - TYPE_PL011); 134 + object_initialize_child(OBJECT(s), name, &s->lpd.iou.uart[i], 135 + TYPE_PL011); 139 136 dev = DEVICE(&s->lpd.iou.uart[i]); 140 137 qdev_prop_set_chr(dev, "chardev", serial_hd(i)); 141 - qdev_init_nofail(dev); 138 + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 142 139 143 140 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 144 141 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); ··· 160 157 DeviceState *dev; 161 158 MemoryRegion *mr; 162 159 163 - sysbus_init_child_obj(OBJECT(s), name, 164 - &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]), 165 - TYPE_CADENCE_GEM); 160 + object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], 161 + TYPE_CADENCE_GEM); 166 162 dev = DEVICE(&s->lpd.iou.gem[i]); 167 163 if (nd->used) { 168 164 qemu_check_nic_model(nd, "cadence_gem"); ··· 174 170 object_property_set_link(OBJECT(dev), 175 171 OBJECT(&s->mr_ps), "dma", 176 172 &error_abort); 177 - qdev_init_nofail(dev); 173 + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 178 174 179 175 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 180 176 memory_region_add_subregion(&s->mr_ps, addrs[i], mr); ··· 193 189 DeviceState *dev; 194 190 MemoryRegion *mr; 195 191 196 - sysbus_init_child_obj(OBJECT(s), name, 197 - &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]), 198 - TYPE_XLNX_ZDMA); 192 + object_initialize_child(OBJECT(s), name, &s->lpd.iou.adma[i], 193 + TYPE_XLNX_ZDMA); 199 194 dev = DEVICE(&s->lpd.iou.adma[i]); 200 195 object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort); 201 - qdev_init_nofail(dev); 196 + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 202 197 203 198 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 204 199 memory_region_add_subregion(&s->mr_ps, ··· 218 213 DeviceState *dev; 219 214 MemoryRegion *mr; 220 215 221 - sysbus_init_child_obj(OBJECT(s), "sd[*]", 222 - &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]), 223 - TYPE_SYSBUS_SDHCI); 216 + object_initialize_child(OBJECT(s), "sd[*]", &s->pmc.iou.sd[i], 217 + TYPE_SYSBUS_SDHCI); 224 218 dev = DEVICE(&s->pmc.iou.sd[i]); 225 219 226 220 object_property_set_uint(OBJECT(dev), ··· 228 222 object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg", 229 223 &error_fatal); 230 224 object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal); 231 - qdev_init_nofail(dev); 225 + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); 232 226 233 227 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 234 228 memory_region_add_subregion(&s->mr_ps,
+3 -5
hw/intc/armv7m_nvic.c
··· 2655 2655 * as we didn't know then if the CPU had the security extensions; 2656 2656 * so we have to do it here. 2657 2657 */ 2658 - sysbus_init_child_obj(OBJECT(dev), "systick-reg-s", 2659 - &s->systick[M_REG_S], 2660 - sizeof(s->systick[M_REG_S]), TYPE_SYSTICK); 2658 + object_initialize_child(OBJECT(dev), "systick-reg-s", 2659 + &s->systick[M_REG_S], TYPE_SYSTICK); 2661 2660 2662 - object_property_set_bool(OBJECT(&s->systick[M_REG_S]), true, 2663 - "realized", &err); 2661 + sysbus_realize(SYS_BUS_DEVICE(&s->systick[M_REG_S]), &err); 2664 2662 if (err != NULL) { 2665 2663 error_propagate(errp, err); 2666 2664 return;
+2 -4
hw/mips/boston.c
··· 454 454 455 455 is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64); 456 456 457 - sysbus_init_child_obj(OBJECT(machine), "cps", &s->cps, sizeof(s->cps), 458 - TYPE_MIPS_CPS); 457 + object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); 459 458 object_property_set_str(OBJECT(&s->cps), machine->cpu_type, "cpu-type", 460 459 &error_fatal); 461 460 object_property_set_int(OBJECT(&s->cps), machine->smp.cpus, "num-vp", 462 461 &error_fatal); 463 - object_property_set_bool(OBJECT(&s->cps), true, "realized", 464 - &error_fatal); 462 + sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 465 463 466 464 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 467 465
+8 -12
hw/mips/cps.c
··· 99 99 100 100 /* Inter-Thread Communication Unit */ 101 101 if (itu_present) { 102 - sysbus_init_child_obj(OBJECT(dev), "itu", &s->itu, sizeof(s->itu), 103 - TYPE_MIPS_ITU); 102 + object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU); 104 103 object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); 105 104 object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); 106 105 object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", ··· 108 107 if (saar_present) { 109 108 s->itu.saar = &env->CP0_SAAR; 110 109 } 111 - object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); 110 + sysbus_realize(SYS_BUS_DEVICE(&s->itu), &err); 112 111 if (err != NULL) { 113 112 error_propagate(errp, err); 114 113 return; ··· 119 118 } 120 119 121 120 /* Cluster Power Controller */ 122 - sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc), 123 - TYPE_MIPS_CPC); 121 + object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); 124 122 object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); 125 123 object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); 126 - object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); 124 + sysbus_realize(SYS_BUS_DEVICE(&s->cpc), &err); 127 125 if (err != NULL) { 128 126 error_propagate(errp, err); 129 127 return; ··· 133 131 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); 134 132 135 133 /* Global Interrupt Controller */ 136 - sysbus_init_child_obj(OBJECT(dev), "gic", &s->gic, sizeof(s->gic), 137 - TYPE_MIPS_GIC); 134 + object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); 138 135 object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); 139 136 object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); 140 - object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); 137 + sysbus_realize(SYS_BUS_DEVICE(&s->gic), &err); 141 138 if (err != NULL) { 142 139 error_propagate(errp, err); 143 140 return; ··· 149 146 /* Global Configuration Registers */ 150 147 gcr_base = env->CP0_CMGCRBase << 4; 151 148 152 - sysbus_init_child_obj(OBJECT(dev), "gcr", &s->gcr, sizeof(s->gcr), 153 - TYPE_MIPS_GCR); 149 + object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); 154 150 object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); 155 151 object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); 156 152 object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); 157 153 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err); 158 154 object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); 159 - object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); 155 + sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err); 160 156 if (err != NULL) { 161 157 error_propagate(errp, err); 162 158 return;
+2 -4
hw/mips/malta.c
··· 1183 1183 static void create_cps(MachineState *ms, MaltaState *s, 1184 1184 qemu_irq *cbus_irq, qemu_irq *i8259_irq) 1185 1185 { 1186 - sysbus_init_child_obj(OBJECT(s), "cps", &s->cps, sizeof(s->cps), 1187 - TYPE_MIPS_CPS); 1186 + object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); 1188 1187 object_property_set_str(OBJECT(&s->cps), ms->cpu_type, "cpu-type", 1189 1188 &error_fatal); 1190 1189 object_property_set_int(OBJECT(&s->cps), ms->smp.cpus, "num-vp", 1191 1190 &error_fatal); 1192 - object_property_set_bool(OBJECT(&s->cps), true, "realized", 1193 - &error_fatal); 1191 + sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); 1194 1192 1195 1193 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); 1196 1194
+6 -8
hw/misc/mac_via.c
··· 876 876 int ret; 877 877 878 878 /* Init VIAs 1 and 2 */ 879 - sysbus_init_child_obj(OBJECT(dev), "via1", &m->mos6522_via1, 880 - sizeof(m->mos6522_via1), TYPE_MOS6522_Q800_VIA1); 879 + object_initialize_child(OBJECT(dev), "via1", &m->mos6522_via1, 880 + TYPE_MOS6522_Q800_VIA1); 881 881 882 - sysbus_init_child_obj(OBJECT(dev), "via2", &m->mos6522_via2, 883 - sizeof(m->mos6522_via2), TYPE_MOS6522_Q800_VIA2); 882 + object_initialize_child(OBJECT(dev), "via2", &m->mos6522_via2, 883 + TYPE_MOS6522_Q800_VIA2); 884 884 885 885 /* Pass through mos6522 output IRQs */ 886 886 ms = MOS6522(&m->mos6522_via1); ··· 890 890 object_property_add_alias(OBJECT(dev), "irq[1]", OBJECT(ms), 891 891 SYSBUS_DEVICE_GPIO_IRQ "[0]"); 892 892 893 - object_property_set_bool(OBJECT(&m->mos6522_via1), true, "realized", 894 - &error_abort); 895 - object_property_set_bool(OBJECT(&m->mos6522_via2), true, "realized", 896 - &error_abort); 893 + sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via1), &error_abort); 894 + sysbus_realize(SYS_BUS_DEVICE(&m->mos6522_via2), &error_abort); 897 895 898 896 /* Pass through mos6522 input IRQs */ 899 897 qdev_pass_gpios(DEVICE(&m->mos6522_via1), dev, "via1-irq");
+3 -4
hw/riscv/spike.c
··· 169 169 unsigned int smp_cpus = machine->smp.cpus; 170 170 171 171 /* Initialize SOC */ 172 - sysbus_init_child_obj(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 173 - TYPE_RISCV_HART_ARRAY); 172 + object_initialize_child(OBJECT(machine), "soc", &s->soc, 173 + TYPE_RISCV_HART_ARRAY); 174 174 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 175 175 &error_abort); 176 176 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 177 177 &error_abort); 178 - object_property_set_bool(OBJECT(&s->soc), true, "realized", 179 - &error_abort); 178 + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); 180 179 181 180 /* register system main memory (actual RAM) */ 182 181 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
+3 -4
hw/riscv/virt.c
··· 485 485 unsigned int smp_cpus = machine->smp.cpus; 486 486 487 487 /* Initialize SOC */ 488 - sysbus_init_child_obj(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), 489 - TYPE_RISCV_HART_ARRAY); 488 + object_initialize_child(OBJECT(machine), "soc", &s->soc, 489 + TYPE_RISCV_HART_ARRAY); 490 490 object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", 491 491 &error_abort); 492 492 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 493 493 &error_abort); 494 - object_property_set_bool(OBJECT(&s->soc), true, "realized", 495 - &error_abort); 494 + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort); 496 495 497 496 /* register system main memory (actual RAM) */ 498 497 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",