jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \
29 a1, a2, a3, a4, a5, a6) { \
30 .targno = (no), \
31 .flags = (fl), \
32 .type = (typ), \
33 .group = (grp), \
34 .size = (sz), \
35},
36#define XTREG_END { .targno = -1 },
37
38#ifndef XCHAL_HAVE_DEPBITS
39#define XCHAL_HAVE_DEPBITS 0
40#endif
41
42#ifndef XCHAL_HAVE_DIV32
43#define XCHAL_HAVE_DIV32 0
44#endif
45
46#ifndef XCHAL_UNALIGNED_LOAD_HW
47#define XCHAL_UNALIGNED_LOAD_HW 0
48#endif
49
50#ifndef XCHAL_HAVE_VECBASE
51#define XCHAL_HAVE_VECBASE 0
52#define XCHAL_VECBASE_RESET_VADDR 0
53#endif
54
55#ifndef XCHAL_RESET_VECTOR0_VADDR
56#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
57#endif
58
59#ifndef XCHAL_RESET_VECTOR1_VADDR
60#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
61#endif
62
63#ifndef XCHAL_HW_VERSION
64#define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \
65 + XCHAL_HW_VERSION_MINOR)
66#endif
67
68#ifndef XCHAL_LOOP_BUFFER_SIZE
69#define XCHAL_LOOP_BUFFER_SIZE 0
70#endif
71
72#ifndef XCHAL_HAVE_EXTERN_REGS
73#define XCHAL_HAVE_EXTERN_REGS 0
74#endif
75
76#ifndef XCHAL_HAVE_MPU
77#define XCHAL_HAVE_MPU 0
78#endif
79
80#ifndef XCHAL_HAVE_EXCLUSIVE
81#define XCHAL_HAVE_EXCLUSIVE 0
82#endif
83
84#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
85
86#define XTENSA_OPTIONS ( \
87 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
88 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
89 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
90 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
91 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
92 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
93 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
94 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
95 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
96 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
97 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
98 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
99 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
100 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
101 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
102 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
103 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
104 XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
105 XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
106 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
107 /* Interrupts and exceptions */ \
108 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
109 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
110 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
111 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
112 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
113 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
114 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
115 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
116 /* Local memory, TODO */ \
117 XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
118 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
119 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
120 XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
121 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
122 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
123 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
124 XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
125 XTENSA_OPTION_MEMORY_ECC_PARITY) | \
126 /* Memory protection and translation */ \
127 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
128 XTENSA_OPTION_REGION_PROTECTION) | \
129 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
130 XTENSA_OPTION_REGION_TRANSLATION) | \
131 XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \
132 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
133 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
134 /* Other, TODO */ \
135 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
136 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
137 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
138 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
139 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
140 XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
141
142#ifndef XCHAL_WINDOW_OF4_VECOFS
143#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
144#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
145#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
146#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
147#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
148#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
149#endif
150
151#if XCHAL_HAVE_WINDOWED
152#define WINDOW_VECTORS \
153 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
154 XCHAL_WINDOW_VECTORS_VADDR, \
155 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
156 XCHAL_WINDOW_VECTORS_VADDR, \
157 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
158 XCHAL_WINDOW_VECTORS_VADDR, \
159 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
160 XCHAL_WINDOW_VECTORS_VADDR, \
161 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
162 XCHAL_WINDOW_VECTORS_VADDR, \
163 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
164 XCHAL_WINDOW_VECTORS_VADDR,
165#else
166#define WINDOW_VECTORS
167#endif
168
169#define EXCEPTION_VECTORS { \
170 [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
171 [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
172 WINDOW_VECTORS \
173 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
174 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
175 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
176 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
177 }
178
179#define INTERRUPT_VECTORS { \
180 0, \
181 0, \
182 XCHAL_INTLEVEL2_VECTOR_VADDR, \
183 XCHAL_INTLEVEL3_VECTOR_VADDR, \
184 XCHAL_INTLEVEL4_VECTOR_VADDR, \
185 XCHAL_INTLEVEL5_VECTOR_VADDR, \
186 XCHAL_INTLEVEL6_VECTOR_VADDR, \
187 XCHAL_INTLEVEL7_VECTOR_VADDR, \
188 }
189
190#define LEVEL_MASKS { \
191 [1] = XCHAL_INTLEVEL1_MASK, \
192 [2] = XCHAL_INTLEVEL2_MASK, \
193 [3] = XCHAL_INTLEVEL3_MASK, \
194 [4] = XCHAL_INTLEVEL4_MASK, \
195 [5] = XCHAL_INTLEVEL5_MASK, \
196 [6] = XCHAL_INTLEVEL6_MASK, \
197 [7] = XCHAL_INTLEVEL7_MASK, \
198 }
199
200#define INTTYPE_MASKS { \
201 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
202 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
203 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
204 }
205
206#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
207#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
208#define XTHAL_INTTYPE_NMI INTTYPE_NMI
209#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
210#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
211#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
212#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
213#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
214#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
215#define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE
216#define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR
217#define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR
218
219
220#define INTERRUPT(i) { \
221 .level = XCHAL_INT ## i ## _LEVEL, \
222 .inttype = XCHAL_INT ## i ## _TYPE, \
223 }
224
225#define INTERRUPTS { \
226 [0] = INTERRUPT(0), \
227 [1] = INTERRUPT(1), \
228 [2] = INTERRUPT(2), \
229 [3] = INTERRUPT(3), \
230 [4] = INTERRUPT(4), \
231 [5] = INTERRUPT(5), \
232 [6] = INTERRUPT(6), \
233 [7] = INTERRUPT(7), \
234 [8] = INTERRUPT(8), \
235 [9] = INTERRUPT(9), \
236 [10] = INTERRUPT(10), \
237 [11] = INTERRUPT(11), \
238 [12] = INTERRUPT(12), \
239 [13] = INTERRUPT(13), \
240 [14] = INTERRUPT(14), \
241 [15] = INTERRUPT(15), \
242 [16] = INTERRUPT(16), \
243 [17] = INTERRUPT(17), \
244 [18] = INTERRUPT(18), \
245 [19] = INTERRUPT(19), \
246 [20] = INTERRUPT(20), \
247 [21] = INTERRUPT(21), \
248 [22] = INTERRUPT(22), \
249 [23] = INTERRUPT(23), \
250 [24] = INTERRUPT(24), \
251 [25] = INTERRUPT(25), \
252 [26] = INTERRUPT(26), \
253 [27] = INTERRUPT(27), \
254 [28] = INTERRUPT(28), \
255 [29] = INTERRUPT(29), \
256 [30] = INTERRUPT(30), \
257 [31] = INTERRUPT(31), \
258 }
259
260#define TIMERINTS { \
261 [0] = XCHAL_TIMER0_INTERRUPT, \
262 [1] = XCHAL_TIMER1_INTERRUPT, \
263 [2] = XCHAL_TIMER2_INTERRUPT, \
264 }
265
266#define EXTINTS { \
267 [0] = XCHAL_EXTINT0_NUM, \
268 [1] = XCHAL_EXTINT1_NUM, \
269 [2] = XCHAL_EXTINT2_NUM, \
270 [3] = XCHAL_EXTINT3_NUM, \
271 [4] = XCHAL_EXTINT4_NUM, \
272 [5] = XCHAL_EXTINT5_NUM, \
273 [6] = XCHAL_EXTINT6_NUM, \
274 [7] = XCHAL_EXTINT7_NUM, \
275 [8] = XCHAL_EXTINT8_NUM, \
276 [9] = XCHAL_EXTINT9_NUM, \
277 [10] = XCHAL_EXTINT10_NUM, \
278 [11] = XCHAL_EXTINT11_NUM, \
279 [12] = XCHAL_EXTINT12_NUM, \
280 [13] = XCHAL_EXTINT13_NUM, \
281 [14] = XCHAL_EXTINT14_NUM, \
282 [15] = XCHAL_EXTINT15_NUM, \
283 [16] = XCHAL_EXTINT16_NUM, \
284 [17] = XCHAL_EXTINT17_NUM, \
285 [18] = XCHAL_EXTINT18_NUM, \
286 [19] = XCHAL_EXTINT19_NUM, \
287 [20] = XCHAL_EXTINT20_NUM, \
288 [21] = XCHAL_EXTINT21_NUM, \
289 [22] = XCHAL_EXTINT22_NUM, \
290 [23] = XCHAL_EXTINT23_NUM, \
291 [24] = XCHAL_EXTINT24_NUM, \
292 [25] = XCHAL_EXTINT25_NUM, \
293 [26] = XCHAL_EXTINT26_NUM, \
294 [27] = XCHAL_EXTINT27_NUM, \
295 [28] = XCHAL_EXTINT28_NUM, \
296 [29] = XCHAL_EXTINT29_NUM, \
297 [30] = XCHAL_EXTINT30_NUM, \
298 [31] = XCHAL_EXTINT31_NUM, \
299 }
300
301#define EXCEPTIONS_SECTION \
302 .excm_level = XCHAL_EXCM_LEVEL, \
303 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
304 .exception_vector = EXCEPTION_VECTORS
305
306#define INTERRUPTS_SECTION \
307 .ninterrupt = XCHAL_NUM_INTERRUPTS, \
308 .nlevel = XCHAL_NUM_INTLEVELS, \
309 .interrupt_vector = INTERRUPT_VECTORS, \
310 .level_mask = LEVEL_MASKS, \
311 .inttype_mask = INTTYPE_MASKS, \
312 .interrupt = INTERRUPTS, \
313 .nccompare = XCHAL_NUM_TIMERS, \
314 .timerint = TIMERINTS, \
315 .nextint = XCHAL_NUM_EXTINTERRUPTS, \
316 .extint = EXTINTS
317
318#if XCHAL_HAVE_PTP_MMU
319
320#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
321 .nways = ways, \
322 .way_size = { \
323 (refill_way_size), (refill_way_size), \
324 (refill_way_size), (refill_way_size), \
325 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
326 }, \
327 .varway56 = (way56), \
328 .nrefillentries = (refill_way_size) * 4, \
329 }
330
331#define ITLB(varway56) \
332 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
333
334#define DTLB(varway56) \
335 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
336
337#define TLB_SECTION \
338 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
339 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
340
341#ifndef XCHAL_SYSROM0_PADDR
342#define XCHAL_SYSROM0_PADDR 0xfe000000
343#define XCHAL_SYSROM0_SIZE 0x02000000
344#endif
345
346#ifndef XCHAL_SYSRAM0_PADDR
347#define XCHAL_SYSRAM0_PADDR 0x00000000
348#define XCHAL_SYSRAM0_SIZE 0x08000000
349#endif
350
351#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
352
353#define TLB_TEMPLATE { \
354 .nways = 1, \
355 .way_size = { \
356 8, \
357 } \
358 }
359
360#define TLB_SECTION \
361 .itlb = TLB_TEMPLATE, \
362 .dtlb = TLB_TEMPLATE
363
364#ifndef XCHAL_SYSROM0_PADDR
365#define XCHAL_SYSROM0_PADDR 0x50000000
366#define XCHAL_SYSROM0_SIZE 0x04000000
367#endif
368
369#ifndef XCHAL_SYSRAM0_PADDR
370#define XCHAL_SYSRAM0_PADDR 0x60000000
371#define XCHAL_SYSRAM0_SIZE 0x04000000
372#endif
373
374#elif XCHAL_HAVE_MPU
375
376#ifndef XTENSA_MPU_BG_MAP
377#ifdef XCHAL_MPU_BACKGROUND_MAP
378#define XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) \
379 { .vaddr = (vaddr_start), .attr = ((rights) << 8) | ((memtype) << 12), },
380
381#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
382 XCHAL_MPU_BACKGROUND_MAP(0) \
383}
384
385#define XTENSA_MPU_BG_MAP_ENTRIES XCHAL_MPU_BACKGROUND_ENTRIES
386#else
387#define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
388 { .vaddr = 0, .attr = 0x00006700, }, \
389}
390
391#define XTENSA_MPU_BG_MAP_ENTRIES 1
392#endif
393#endif
394
395#define TLB_SECTION \
396 .mpu_align = XCHAL_MPU_ALIGN, \
397 .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \
398 .n_mpu_bg_segments = XTENSA_MPU_BG_MAP_ENTRIES, \
399 .mpu_bg = XTENSA_MPU_BG_MAP
400
401#ifndef XCHAL_SYSROM0_PADDR
402#define XCHAL_SYSROM0_PADDR 0x50000000
403#define XCHAL_SYSROM0_SIZE 0x04000000
404#endif
405
406#ifndef XCHAL_SYSRAM0_PADDR
407#define XCHAL_SYSRAM0_PADDR 0x60000000
408#define XCHAL_SYSRAM0_SIZE 0x04000000
409#endif
410
411#else
412
413#ifndef XCHAL_SYSROM0_PADDR
414#define XCHAL_SYSROM0_PADDR 0x50000000
415#define XCHAL_SYSROM0_SIZE 0x04000000
416#endif
417
418#ifndef XCHAL_SYSRAM0_PADDR
419#define XCHAL_SYSRAM0_PADDR 0x60000000
420#define XCHAL_SYSRAM0_SIZE 0x04000000
421#endif
422
423#endif
424
425#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
426#define REGISTER_CORE(core) \
427 static void __attribute__((constructor)) register_core(void) \
428 { \
429 static XtensaConfigList node = { \
430 .config = &core, \
431 }; \
432 xtensa_register_core(&node); \
433 }
434#else
435#define REGISTER_CORE(core)
436#endif
437
438#define DEBUG_SECTION \
439 .debug_level = XCHAL_DEBUGLEVEL, \
440 .nibreak = XCHAL_NUM_IBREAK, \
441 .ndbreak = XCHAL_NUM_DBREAK
442
443#define CACHE_SECTION \
444 .icache_ways = XCHAL_ICACHE_WAYS, \
445 .dcache_ways = XCHAL_DCACHE_WAYS, \
446 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
447 .memctl_mask = \
448 (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
449 (XCHAL_DCACHE_SIZE ? \
450 MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
451 MEMCTL_ISNP | MEMCTL_DSNP | \
452 (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
453
454#define MEM_LOCATION(name, n) \
455 { \
456 .addr = XCHAL_ ## name ## n ## _PADDR, \
457 .size = XCHAL_ ## name ## n ## _SIZE, \
458 }
459
460#define MEM_SECTIONS(name) \
461 MEM_LOCATION(name, 0), \
462 MEM_LOCATION(name, 1), \
463 MEM_LOCATION(name, 2), \
464 MEM_LOCATION(name, 3)
465
466#define MEM_SECTION(name) \
467 .num = XCHAL_NUM_ ## name, \
468 .location = { \
469 MEM_SECTIONS(name) \
470 }
471
472#define SYSMEM_SECTION(name) \
473 .num = 1, \
474 .location = { \
475 { \
476 .addr = XCHAL_ ## name ## 0_PADDR, \
477 .size = XCHAL_ ## name ## 0_SIZE, \
478 } \
479 }
480
481#define LOCAL_MEMORIES_SECTION \
482 .instrom = { \
483 MEM_SECTION(INSTROM) \
484 }, \
485 .instram = { \
486 MEM_SECTION(INSTRAM) \
487 }, \
488 .datarom = { \
489 MEM_SECTION(DATAROM) \
490 }, \
491 .dataram = { \
492 MEM_SECTION(DATARAM) \
493 }, \
494 .sysrom = { \
495 SYSMEM_SECTION(SYSROM) \
496 }, \
497 .sysram = { \
498 SYSMEM_SECTION(SYSRAM) \
499 }
500
501#define CONFIG_SECTION \
502 .hw_version = XCHAL_HW_VERSION, \
503 .configid = { \
504 XCHAL_HW_CONFIGID0, \
505 XCHAL_HW_CONFIGID1, \
506 }
507
508#define DEFAULT_SECTIONS \
509 .options = XTENSA_OPTIONS, \
510 .nareg = XCHAL_NUM_AREGS, \
511 .ndepc = (XCHAL_XEA_VERSION >= 2), \
512 .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
513 .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
514 EXCEPTIONS_SECTION, \
515 INTERRUPTS_SECTION, \
516 TLB_SECTION, \
517 DEBUG_SECTION, \
518 CACHE_SECTION, \
519 LOCAL_MEMORIES_SECTION, \
520 CONFIG_SECTION
521
522
523#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
524#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
525#endif
526#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
527#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
528#endif
529#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
530#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
531#endif
532#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
533#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
534#endif
535#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
536#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
537#endif
538#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
539#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
540#endif
541
542
543#if XCHAL_NUM_INTERRUPTS <= 0
544#define XCHAL_INT0_LEVEL 0
545#define XCHAL_INT0_TYPE 0
546#endif
547#if XCHAL_NUM_INTERRUPTS <= 1
548#define XCHAL_INT1_LEVEL 0
549#define XCHAL_INT1_TYPE 0
550#endif
551#if XCHAL_NUM_INTERRUPTS <= 2
552#define XCHAL_INT2_LEVEL 0
553#define XCHAL_INT2_TYPE 0
554#endif
555#if XCHAL_NUM_INTERRUPTS <= 3
556#define XCHAL_INT3_LEVEL 0
557#define XCHAL_INT3_TYPE 0
558#endif
559#if XCHAL_NUM_INTERRUPTS <= 4
560#define XCHAL_INT4_LEVEL 0
561#define XCHAL_INT4_TYPE 0
562#endif
563#if XCHAL_NUM_INTERRUPTS <= 5
564#define XCHAL_INT5_LEVEL 0
565#define XCHAL_INT5_TYPE 0
566#endif
567#if XCHAL_NUM_INTERRUPTS <= 6
568#define XCHAL_INT6_LEVEL 0
569#define XCHAL_INT6_TYPE 0
570#endif
571#if XCHAL_NUM_INTERRUPTS <= 7
572#define XCHAL_INT7_LEVEL 0
573#define XCHAL_INT7_TYPE 0
574#endif
575#if XCHAL_NUM_INTERRUPTS <= 8
576#define XCHAL_INT8_LEVEL 0
577#define XCHAL_INT8_TYPE 0
578#endif
579#if XCHAL_NUM_INTERRUPTS <= 9
580#define XCHAL_INT9_LEVEL 0
581#define XCHAL_INT9_TYPE 0
582#endif
583#if XCHAL_NUM_INTERRUPTS <= 10
584#define XCHAL_INT10_LEVEL 0
585#define XCHAL_INT10_TYPE 0
586#endif
587#if XCHAL_NUM_INTERRUPTS <= 11
588#define XCHAL_INT11_LEVEL 0
589#define XCHAL_INT11_TYPE 0
590#endif
591#if XCHAL_NUM_INTERRUPTS <= 12
592#define XCHAL_INT12_LEVEL 0
593#define XCHAL_INT12_TYPE 0
594#endif
595#if XCHAL_NUM_INTERRUPTS <= 13
596#define XCHAL_INT13_LEVEL 0
597#define XCHAL_INT13_TYPE 0
598#endif
599#if XCHAL_NUM_INTERRUPTS <= 14
600#define XCHAL_INT14_LEVEL 0
601#define XCHAL_INT14_TYPE 0
602#endif
603#if XCHAL_NUM_INTERRUPTS <= 15
604#define XCHAL_INT15_LEVEL 0
605#define XCHAL_INT15_TYPE 0
606#endif
607#if XCHAL_NUM_INTERRUPTS <= 16
608#define XCHAL_INT16_LEVEL 0
609#define XCHAL_INT16_TYPE 0
610#endif
611#if XCHAL_NUM_INTERRUPTS <= 17
612#define XCHAL_INT17_LEVEL 0
613#define XCHAL_INT17_TYPE 0
614#endif
615#if XCHAL_NUM_INTERRUPTS <= 18
616#define XCHAL_INT18_LEVEL 0
617#define XCHAL_INT18_TYPE 0
618#endif
619#if XCHAL_NUM_INTERRUPTS <= 19
620#define XCHAL_INT19_LEVEL 0
621#define XCHAL_INT19_TYPE 0
622#endif
623#if XCHAL_NUM_INTERRUPTS <= 20
624#define XCHAL_INT20_LEVEL 0
625#define XCHAL_INT20_TYPE 0
626#endif
627#if XCHAL_NUM_INTERRUPTS <= 21
628#define XCHAL_INT21_LEVEL 0
629#define XCHAL_INT21_TYPE 0
630#endif
631#if XCHAL_NUM_INTERRUPTS <= 22
632#define XCHAL_INT22_LEVEL 0
633#define XCHAL_INT22_TYPE 0
634#endif
635#if XCHAL_NUM_INTERRUPTS <= 23
636#define XCHAL_INT23_LEVEL 0
637#define XCHAL_INT23_TYPE 0
638#endif
639#if XCHAL_NUM_INTERRUPTS <= 24
640#define XCHAL_INT24_LEVEL 0
641#define XCHAL_INT24_TYPE 0
642#endif
643#if XCHAL_NUM_INTERRUPTS <= 25
644#define XCHAL_INT25_LEVEL 0
645#define XCHAL_INT25_TYPE 0
646#endif
647#if XCHAL_NUM_INTERRUPTS <= 26
648#define XCHAL_INT26_LEVEL 0
649#define XCHAL_INT26_TYPE 0
650#endif
651#if XCHAL_NUM_INTERRUPTS <= 27
652#define XCHAL_INT27_LEVEL 0
653#define XCHAL_INT27_TYPE 0
654#endif
655#if XCHAL_NUM_INTERRUPTS <= 28
656#define XCHAL_INT28_LEVEL 0
657#define XCHAL_INT28_TYPE 0
658#endif
659#if XCHAL_NUM_INTERRUPTS <= 29
660#define XCHAL_INT29_LEVEL 0
661#define XCHAL_INT29_TYPE 0
662#endif
663#if XCHAL_NUM_INTERRUPTS <= 30
664#define XCHAL_INT30_LEVEL 0
665#define XCHAL_INT30_TYPE 0
666#endif
667#if XCHAL_NUM_INTERRUPTS <= 31
668#define XCHAL_INT31_LEVEL 0
669#define XCHAL_INT31_TYPE 0
670#endif
671
672
673#if XCHAL_NUM_EXTINTERRUPTS <= 0
674#define XCHAL_EXTINT0_NUM 0
675#endif
676#if XCHAL_NUM_EXTINTERRUPTS <= 1
677#define XCHAL_EXTINT1_NUM 0
678#endif
679#if XCHAL_NUM_EXTINTERRUPTS <= 2
680#define XCHAL_EXTINT2_NUM 0
681#endif
682#if XCHAL_NUM_EXTINTERRUPTS <= 3
683#define XCHAL_EXTINT3_NUM 0
684#endif
685#if XCHAL_NUM_EXTINTERRUPTS <= 4
686#define XCHAL_EXTINT4_NUM 0
687#endif
688#if XCHAL_NUM_EXTINTERRUPTS <= 5
689#define XCHAL_EXTINT5_NUM 0
690#endif
691#if XCHAL_NUM_EXTINTERRUPTS <= 6
692#define XCHAL_EXTINT6_NUM 0
693#endif
694#if XCHAL_NUM_EXTINTERRUPTS <= 7
695#define XCHAL_EXTINT7_NUM 0
696#endif
697#if XCHAL_NUM_EXTINTERRUPTS <= 8
698#define XCHAL_EXTINT8_NUM 0
699#endif
700#if XCHAL_NUM_EXTINTERRUPTS <= 9
701#define XCHAL_EXTINT9_NUM 0
702#endif
703#if XCHAL_NUM_EXTINTERRUPTS <= 10
704#define XCHAL_EXTINT10_NUM 0
705#endif
706#if XCHAL_NUM_EXTINTERRUPTS <= 11
707#define XCHAL_EXTINT11_NUM 0
708#endif
709#if XCHAL_NUM_EXTINTERRUPTS <= 12
710#define XCHAL_EXTINT12_NUM 0
711#endif
712#if XCHAL_NUM_EXTINTERRUPTS <= 13
713#define XCHAL_EXTINT13_NUM 0
714#endif
715#if XCHAL_NUM_EXTINTERRUPTS <= 14
716#define XCHAL_EXTINT14_NUM 0
717#endif
718#if XCHAL_NUM_EXTINTERRUPTS <= 15
719#define XCHAL_EXTINT15_NUM 0
720#endif
721#if XCHAL_NUM_EXTINTERRUPTS <= 16
722#define XCHAL_EXTINT16_NUM 0
723#endif
724#if XCHAL_NUM_EXTINTERRUPTS <= 17
725#define XCHAL_EXTINT17_NUM 0
726#endif
727#if XCHAL_NUM_EXTINTERRUPTS <= 18
728#define XCHAL_EXTINT18_NUM 0
729#endif
730#if XCHAL_NUM_EXTINTERRUPTS <= 19
731#define XCHAL_EXTINT19_NUM 0
732#endif
733#if XCHAL_NUM_EXTINTERRUPTS <= 20
734#define XCHAL_EXTINT20_NUM 0
735#endif
736#if XCHAL_NUM_EXTINTERRUPTS <= 21
737#define XCHAL_EXTINT21_NUM 0
738#endif
739#if XCHAL_NUM_EXTINTERRUPTS <= 22
740#define XCHAL_EXTINT22_NUM 0
741#endif
742#if XCHAL_NUM_EXTINTERRUPTS <= 23
743#define XCHAL_EXTINT23_NUM 0
744#endif
745#if XCHAL_NUM_EXTINTERRUPTS <= 24
746#define XCHAL_EXTINT24_NUM 0
747#endif
748#if XCHAL_NUM_EXTINTERRUPTS <= 25
749#define XCHAL_EXTINT25_NUM 0
750#endif
751#if XCHAL_NUM_EXTINTERRUPTS <= 26
752#define XCHAL_EXTINT26_NUM 0
753#endif
754#if XCHAL_NUM_EXTINTERRUPTS <= 27
755#define XCHAL_EXTINT27_NUM 0
756#endif
757#if XCHAL_NUM_EXTINTERRUPTS <= 28
758#define XCHAL_EXTINT28_NUM 0
759#endif
760#if XCHAL_NUM_EXTINTERRUPTS <= 29
761#define XCHAL_EXTINT29_NUM 0
762#endif
763#if XCHAL_NUM_EXTINTERRUPTS <= 30
764#define XCHAL_EXTINT30_NUM 0
765#endif
766#if XCHAL_NUM_EXTINTERRUPTS <= 31
767#define XCHAL_EXTINT31_NUM 0
768#endif
769
770
771#define XTHAL_TIMER_UNCONFIGURED 0
772
773#if XCHAL_NUM_INSTROM < 1
774#define XCHAL_INSTROM0_PADDR 0
775#define XCHAL_INSTROM0_SIZE 0
776#endif
777#if XCHAL_NUM_INSTROM < 2
778#define XCHAL_INSTROM1_PADDR 0
779#define XCHAL_INSTROM1_SIZE 0
780#endif
781#if XCHAL_NUM_INSTROM < 3
782#define XCHAL_INSTROM2_PADDR 0
783#define XCHAL_INSTROM2_SIZE 0
784#endif
785#if XCHAL_NUM_INSTROM < 4
786#define XCHAL_INSTROM3_PADDR 0
787#define XCHAL_INSTROM3_SIZE 0
788#endif
789#if XCHAL_NUM_INSTROM > MAX_NMEMORY
790#error XCHAL_NUM_INSTROM > MAX_NMEMORY
791#endif
792
793#if XCHAL_NUM_INSTRAM < 1
794#define XCHAL_INSTRAM0_PADDR 0
795#define XCHAL_INSTRAM0_SIZE 0
796#endif
797#if XCHAL_NUM_INSTRAM < 2
798#define XCHAL_INSTRAM1_PADDR 0
799#define XCHAL_INSTRAM1_SIZE 0
800#endif
801#if XCHAL_NUM_INSTRAM < 3
802#define XCHAL_INSTRAM2_PADDR 0
803#define XCHAL_INSTRAM2_SIZE 0
804#endif
805#if XCHAL_NUM_INSTRAM < 4
806#define XCHAL_INSTRAM3_PADDR 0
807#define XCHAL_INSTRAM3_SIZE 0
808#endif
809#if XCHAL_NUM_INSTRAM > MAX_NMEMORY
810#error XCHAL_NUM_INSTRAM > MAX_NMEMORY
811#endif
812
813#if XCHAL_NUM_DATAROM < 1
814#define XCHAL_DATAROM0_PADDR 0
815#define XCHAL_DATAROM0_SIZE 0
816#endif
817#if XCHAL_NUM_DATAROM < 2
818#define XCHAL_DATAROM1_PADDR 0
819#define XCHAL_DATAROM1_SIZE 0
820#endif
821#if XCHAL_NUM_DATAROM < 3
822#define XCHAL_DATAROM2_PADDR 0
823#define XCHAL_DATAROM2_SIZE 0
824#endif
825#if XCHAL_NUM_DATAROM < 4
826#define XCHAL_DATAROM3_PADDR 0
827#define XCHAL_DATAROM3_SIZE 0
828#endif
829#if XCHAL_NUM_DATAROM > MAX_NMEMORY
830#error XCHAL_NUM_DATAROM > MAX_NMEMORY
831#endif
832
833#if XCHAL_NUM_DATARAM < 1
834#define XCHAL_DATARAM0_PADDR 0
835#define XCHAL_DATARAM0_SIZE 0
836#endif
837#if XCHAL_NUM_DATARAM < 2
838#define XCHAL_DATARAM1_PADDR 0
839#define XCHAL_DATARAM1_SIZE 0
840#endif
841#if XCHAL_NUM_DATARAM < 3
842#define XCHAL_DATARAM2_PADDR 0
843#define XCHAL_DATARAM2_SIZE 0
844#endif
845#if XCHAL_NUM_DATARAM < 4
846#define XCHAL_DATARAM3_PADDR 0
847#define XCHAL_DATARAM3_SIZE 0
848#endif
849#if XCHAL_NUM_DATARAM > MAX_NMEMORY
850#error XCHAL_NUM_DATARAM > MAX_NMEMORY
851#endif