jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * IMX6 System Reset Controller
3 *
4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
11#ifndef IMX6_SRC_H
12#define IMX6_SRC_H
13
14#include "hw/sysbus.h"
15#include "qemu/bitops.h"
16
17#define SRC_SCR 0
18#define SRC_SBMR1 1
19#define SRC_SRSR 2
20#define SRC_SISR 5
21#define SRC_SIMR 6
22#define SRC_SBMR2 7
23#define SRC_GPR1 8
24#define SRC_GPR2 9
25#define SRC_GPR3 10
26#define SRC_GPR4 11
27#define SRC_GPR5 12
28#define SRC_GPR6 13
29#define SRC_GPR7 14
30#define SRC_GPR8 15
31#define SRC_GPR9 16
32#define SRC_GPR10 17
33#define SRC_MAX 18
34
35/* SRC_SCR */
36#define CORE3_ENABLE_SHIFT 24
37#define CORE3_ENABLE_LENGTH 1
38#define CORE2_ENABLE_SHIFT 23
39#define CORE2_ENABLE_LENGTH 1
40#define CORE1_ENABLE_SHIFT 22
41#define CORE1_ENABLE_LENGTH 1
42#define CORE3_RST_SHIFT 16
43#define CORE3_RST_LENGTH 1
44#define CORE2_RST_SHIFT 15
45#define CORE2_RST_LENGTH 1
46#define CORE1_RST_SHIFT 14
47#define CORE1_RST_LENGTH 1
48#define CORE0_RST_SHIFT 13
49#define CORE0_RST_LENGTH 1
50#define SW_IPU1_RST_SHIFT 3
51#define SW_IPU1_RST_LENGTH 1
52#define SW_IPU2_RST_SHIFT 12
53#define SW_IPU2_RST_LENGTH 1
54#define WARM_RST_ENABLE_SHIFT 0
55#define WARM_RST_ENABLE_LENGTH 1
56
57#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
58
59#define TYPE_IMX6_SRC "imx6.src"
60#define IMX6_SRC(obj) OBJECT_CHECK(IMX6SRCState, (obj), TYPE_IMX6_SRC)
61
62typedef struct IMX6SRCState {
63 /* <private> */
64 SysBusDevice parent_obj;
65
66 /* <public> */
67 MemoryRegion iomem;
68
69 uint32_t regs[SRC_MAX];
70
71} IMX6SRCState;
72
73#endif /* IMX6_SRC_H */