jcs.org
Control intel backlight on FreeBSD (and OpenBSD)
openbsd
update intel_chipset.h from intel-gpu-tools
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intel_chipset.h
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intel_chipset.h
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#ifndef _INTEL_CHIPSET_H
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#define _INTEL_CHIPSET_H
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/* Exclude chipset #defines, they just add noise */
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#ifndef __GTK_DOC_IGNORE__
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I830_M 0x3577
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_I854_G 0x358e
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
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#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
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#define BDW_SPARE 0x2
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#define BDW_ULT 0x6
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#define BDW_HALO 0xb
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#define BDW_SERVER 0xa
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#define BDW_WORKSTATION 0xd
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#define BDW_ULX 0xe
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#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
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#define PCI_CHIP_VALLEYVIEW_1 0x0f31
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#define PCI_CHIP_VALLEYVIEW_2 0x0f32
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#define PCI_CHIP_VALLEYVIEW_3 0x0f33
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#define PCI_CHIP_CHERRYVIEW_0 0x22b0
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#define PCI_CHIP_CHERRYVIEW_1 0x22b1
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#define PCI_CHIP_CHERRYVIEW_2 0x22b2
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#define PCI_CHIP_CHERRYVIEW_3 0x22b3
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#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
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#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
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#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926
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#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921
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#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E
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#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
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#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
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#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
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#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
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#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B
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#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B
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#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A
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#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A
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#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
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#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
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#define PCI_CHIP_BROXTON_0 0x0A84
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#define PCI_CHIP_BROXTON_1 0x1A84
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#define PCI_CHIP_BROXTON_2 0x5A84
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#endif /* __GTK_DOC_IGNORE__ */
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#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I915_GM || \
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(devid) == PCI_CHIP_I945_GM || \
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#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
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(devid) == PCI_CHIP_845_G || \
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(devid) == PCI_CHIP_I854_G || \
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(devid) == PCI_CHIP_I855_GM || \
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(devid) == PCI_CHIP_I865_G)
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IS_HSW_GT2(devid) || \
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IS_HSW_GT3(devid))
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#define IS_BROADWELL(devid) ((((devid) & 0xff00) != 0x1600) ? 0 : \
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((((devid) & 0x00f0) >> 4) > 3) ? 0 : \
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(((devid) & 0x000f) == BDW_SPARE) ? 1 : \
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(((devid) & 0x000f) == BDW_ULT) ? 1 : \
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(((devid) & 0x000f) == BDW_HALO) ? 1 : \
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(((devid) & 0x000f) == BDW_SERVER) ? 1 : \
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(((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
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(((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
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#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
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(devid) == PCI_CHIP_CHERRYVIEW_1 || \
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(devid) == PCI_CHIP_CHERRYVIEW_2 || \
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(devid) == PCI_CHIP_CHERRYVIEW_3)
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#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
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IS_CHERRYVIEW(devid))
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#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
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#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
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(devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
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(devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
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#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \
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(devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
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(devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
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#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
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IS_SKL_GT2(devid) || \
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IS_SKL_GT3(devid))
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#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
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(devid) == PCI_CHIP_BROXTON_1 || \
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(devid) == PCI_CHIP_BROXTON_2)
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#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid))
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#define IS_965(devid) (IS_GEN4(devid) || \
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IS_GEN5(devid) || \
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IS_GEN6(devid) || \
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IS_GEN7(devid))
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IS_GEN7(devid) || \
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IS_GEN8(devid) || \
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IS_GEN9(devid))
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#define IS_9XX(devid) (IS_GEN3(devid) || \
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IS_GEN4(devid) || \
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IS_GEN5(devid) || \
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IS_GEN6(devid) || \
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IS_GEN7(devid) || \
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IS_GEN8(devid) || \
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IS_GEN9(devid))
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#define IS_INTEL(devid) (IS_GEN2(devid) || \
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IS_GEN3(devid) || \
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IS_GEN4(devid) || \
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IS_GEN5(devid) || \
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IS_GEN6(devid) || \
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IS_GEN7(devid))
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IS_GEN7(devid) || \
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IS_GEN8(devid) || \
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IS_GEN9(devid))
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#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
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IS_GEN6(devid) || \
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IS_IVYBRIDGE(devid) || IS_HASWELL(devid))
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IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
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IS_BROADWELL(devid) || \
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IS_SKYLAKE(devid))
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#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
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IS_GEN7(devid))
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IS_GEN7(devid) || \
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IS_GEN8(devid) || \
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IS_GEN9(devid))
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#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
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IS_GEN6(devid) || \
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IS_GEN7(devid))
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IS_GEN7(devid) || \
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IS_GEN8(devid) || \
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IS_GEN9(devid))
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#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
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(devid) == PCI_CHIP_I965_G_1 || \