jcs.org
Control intel backlight on FreeBSD (and OpenBSD)
openbsd
Initial commit
+5312
+108
COPYING
+108
COPYING
···
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Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Copyright 2003,2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Copyright © 2006-2011 Intel Corporation
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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IN THE SOFTWARE.
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Copyright © 2010 Red Hat, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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Copyright © 2011 Daniel Vetter
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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IN THE SOFTWARE.
+13
Makefile
+13
Makefile
···
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SRC=intel_reg_map.c intel_mmio.c intel_backlight.c intel_drm.c intel_pci.c
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all: intel_backlight
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intel_backlight: $(SRC)
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clang -o intel_backlight -I/usr/local/include -I/usr/local/include/libdrm -L/usr/local/lib -ldrm_intel -lpciaccess $(SRC)
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strip intel_backlight
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install: intel_backlight
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install -m4555 intel_backlight /usr/local/bin
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clean:
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rm -f intel_backlight
+21
README
+21
README
···
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This allows to control the backlight level on certain Intel(R) GPUs,
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including i915.
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This has been taken from intel-gpu-tools which can be found
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here: http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/
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Originally ported to FreeBSD by "emmex" of the FreeBSD forums.
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Build:
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pkg install libpciaccess libdrm
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make
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make install
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(this installs intel_backlight setuid root, so any user can execute it).
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Usage:
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$ intel_backlight
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current backlight value: 30% (281/937)
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$ intel_backlight 50
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current backlight value: 15% (141/937)
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set backlight to 50% (469/937)
+111
intel_backlight.c
+111
intel_backlight.c
···
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/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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* Maurizio Vairani <maurizio.vairani@cloverinformatica.it>
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include "intel_gpu_tools.h"
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#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(array[0]))
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/* XXX PCH only today */
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static uint32_t reg_read(uint32_t reg)
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{
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return *(volatile uint32_t *)((volatile char*)mmio + reg);
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}
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static void reg_write(uint32_t reg, uint32_t val)
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{
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*(volatile uint32_t *)((volatile char*)mmio + reg) = val;
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}
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static int brightness_levels[] = {1, 2, 4, 6, 9, 12, 16, 20, 25, 30, 36, 43,
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51, 60, 70, 80, 90, 100};
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static int brightness_incr(int curr)
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{
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int i;
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for (i = 0; i < NUM_ELEMENTS(brightness_levels) - 1; ++i)
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if (curr < brightness_levels[i])
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break;
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return brightness_levels[i];
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}
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static int brightness_decr(int curr)
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{
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int i;
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for (i = NUM_ELEMENTS(brightness_levels) - 1; i > 0; --i)
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if (brightness_levels[i] < curr)
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break;
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return brightness_levels[i];
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}
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int main(int argc, char** argv)
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{
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uint32_t current, max, min;
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int result;
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intel_get_mmio(intel_get_pci_device());
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current = reg_read(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
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max = reg_read(BLC_PWM_PCH_CTL2) >> 16;
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min = 0.5 + 0.5 * max / 100.0; // 0.5%
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/*
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printf ("min: %d, NUM_ELEMENTS(brightness_levels): %d\n", min,
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NUM_ELEMENTS(brightness_levels));
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*/
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result = 0.5 + current * 100.0 / max;
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printf ("current backlight value: %d%% (%d/%d)\n", result, current, max);
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if (argc > 1) {
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uint32_t v;
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if (0 == strcmp(argv[1], "incr"))
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v = 0.5 + brightness_incr(result) * max / 100.0;
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else if (0 == strcmp(argv[1], "decr"))
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v = 0.5 + brightness_decr(result) * max / 100.0;
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else
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v = 0.5 + atoi (argv[1]) * max / 100.0;
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/*
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printf("v: %d\n", v);
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*/
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if (v < min)
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v = min;
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else if (v > max)
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v = max;
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reg_write(BLC_PWM_CPU_CTL,
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(reg_read(BLC_PWM_CPU_CTL) &~ BACKLIGHT_DUTY_CYCLE_MASK) | v);
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(void) reg_read(BLC_PWM_CPU_CTL);
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result = 0.5 + v * 100.0 / max;
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printf ("set backlight to %d%% (%d/%d)\n", result, v, max);
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}
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return result;
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}
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+332
intel_chipset.h
+332
intel_chipset.h
···
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/*
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* Copyright © 2007 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifndef _INTEL_CHIPSET_H
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#define _INTEL_CHIPSET_H
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I815 0x1132
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#define PCI_CHIP_I830_M 0x3577
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_I915_G 0x2582
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#define PCI_CHIP_E7221_G 0x258A
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#define PCI_CHIP_I915_GM 0x2592
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#define PCI_CHIP_I945_G 0x2772
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#define PCI_CHIP_I945_GM 0x27A2
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#define PCI_CHIP_I945_GME 0x27AE
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#define PCI_CHIP_Q35_G 0x29B2
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#define PCI_CHIP_G33_G 0x29C2
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#define PCI_CHIP_Q33_G 0x29D2
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#define PCI_CHIP_IGD_GM 0xA011
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#define PCI_CHIP_IGD_G 0xA001
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#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
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#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
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#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
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#define PCI_CHIP_I965_G 0x29A2
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#define PCI_CHIP_I965_Q 0x2992
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#define PCI_CHIP_I965_G_1 0x2982
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#define PCI_CHIP_I946_GZ 0x2972
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#define PCI_CHIP_I965_GM 0x2A02
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#define PCI_CHIP_I965_GME 0x2A12
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#define PCI_CHIP_GM45_GM 0x2A42
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#define PCI_CHIP_IGD_E_G 0x2E02
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#define PCI_CHIP_Q45_G 0x2E12
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#define PCI_CHIP_G45_G 0x2E22
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#define PCI_CHIP_G41_G 0x2E32
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#define PCI_CHIP_ILD_G 0x0042
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#define PCI_CHIP_ILM_G 0x0046
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
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#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
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#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
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#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
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#define PCI_CHIP_HASWELL_GT2 0x0412
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#define PCI_CHIP_HASWELL_GT3 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT3 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
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#define PCI_CHIP_HASWELL_S_GT2 0x041A
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#define PCI_CHIP_HASWELL_S_GT3 0x042A
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#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
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#define PCI_CHIP_HASWELL_B_GT2 0x041B
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#define PCI_CHIP_HASWELL_B_GT3 0x042B
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#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
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#define PCI_CHIP_HASWELL_E_GT2 0x041E
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#define PCI_CHIP_HASWELL_E_GT3 0x042E
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#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
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#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
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#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
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#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
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#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
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#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
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#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
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#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
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#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
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#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
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#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
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#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
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#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
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#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
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#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
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#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
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#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
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#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
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#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
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#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
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#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
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#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
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#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
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#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
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#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
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#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
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#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
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#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
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#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
150
+
#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
151
+
152
+
#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
153
+
#define PCI_CHIP_VALLEYVIEW_1 0x0f31
154
+
#define PCI_CHIP_VALLEYVIEW_2 0x0f32
155
+
#define PCI_CHIP_VALLEYVIEW_3 0x0f33
156
+
157
+
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
158
+
(devid) == PCI_CHIP_I915_GM || \
159
+
(devid) == PCI_CHIP_I945_GM || \
160
+
(devid) == PCI_CHIP_I945_GME || \
161
+
(devid) == PCI_CHIP_I965_GM || \
162
+
(devid) == PCI_CHIP_I965_GME || \
163
+
(devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
164
+
(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
165
+
(devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
166
+
167
+
#define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
168
+
(devid) == PCI_CHIP_Q45_G || \
169
+
(devid) == PCI_CHIP_G45_G || \
170
+
(devid) == PCI_CHIP_G41_G)
171
+
#define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
172
+
#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
173
+
174
+
#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
175
+
#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
176
+
177
+
#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
178
+
(devid) == PCI_CHIP_E7221_G || \
179
+
(devid) == PCI_CHIP_I915_GM)
180
+
181
+
#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
182
+
(devid) == PCI_CHIP_I945_GME)
183
+
184
+
#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
185
+
(devid) == PCI_CHIP_I945_GM || \
186
+
(devid) == PCI_CHIP_I945_GME || \
187
+
IS_G33(devid))
188
+
189
+
#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
190
+
(devid) == PCI_CHIP_Q33_G || \
191
+
(devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
192
+
193
+
#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
194
+
(devid) == PCI_CHIP_845_G || \
195
+
(devid) == PCI_CHIP_I855_GM || \
196
+
(devid) == PCI_CHIP_I865_G)
197
+
198
+
#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
199
+
200
+
#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
201
+
(devid) == PCI_CHIP_I965_Q || \
202
+
(devid) == PCI_CHIP_I965_G_1 || \
203
+
(devid) == PCI_CHIP_I965_GM || \
204
+
(devid) == PCI_CHIP_I965_GME || \
205
+
(devid) == PCI_CHIP_I946_GZ || \
206
+
IS_G4X(devid))
207
+
208
+
#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
209
+
210
+
#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
211
+
(devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
212
+
(devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
213
+
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
214
+
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
215
+
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
216
+
(devid) == PCI_CHIP_SANDYBRIDGE_S)
217
+
218
+
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
219
+
IS_HASWELL(devid) || \
220
+
IS_VALLEYVIEW(devid))
221
+
222
+
#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
223
+
(devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
224
+
(devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
225
+
(devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
226
+
(devid) == PCI_CHIP_IVYBRIDGE_S || \
227
+
(devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
228
+
229
+
#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
230
+
(devid) == PCI_CHIP_VALLEYVIEW_1 || \
231
+
(devid) == PCI_CHIP_VALLEYVIEW_2 || \
232
+
(devid) == PCI_CHIP_VALLEYVIEW_3)
233
+
234
+
#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
235
+
(devid) == PCI_CHIP_HASWELL_M_GT1 || \
236
+
(devid) == PCI_CHIP_HASWELL_S_GT1 || \
237
+
(devid) == PCI_CHIP_HASWELL_B_GT1 || \
238
+
(devid) == PCI_CHIP_HASWELL_E_GT1 || \
239
+
(devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
240
+
(devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
241
+
(devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
242
+
(devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
243
+
(devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
244
+
(devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
245
+
(devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
246
+
(devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
247
+
(devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
248
+
(devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
249
+
(devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
250
+
(devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
251
+
(devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
252
+
(devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
253
+
(devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
254
+
#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
255
+
(devid) == PCI_CHIP_HASWELL_M_GT2 || \
256
+
(devid) == PCI_CHIP_HASWELL_S_GT2 || \
257
+
(devid) == PCI_CHIP_HASWELL_B_GT2 || \
258
+
(devid) == PCI_CHIP_HASWELL_E_GT2 || \
259
+
(devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
260
+
(devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
261
+
(devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
262
+
(devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
263
+
(devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
264
+
(devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
265
+
(devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
266
+
(devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
267
+
(devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
268
+
(devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
269
+
(devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
270
+
(devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
271
+
(devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
272
+
(devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
273
+
(devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
274
+
#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
275
+
(devid) == PCI_CHIP_HASWELL_M_GT3 || \
276
+
(devid) == PCI_CHIP_HASWELL_S_GT3 || \
277
+
(devid) == PCI_CHIP_HASWELL_B_GT3 || \
278
+
(devid) == PCI_CHIP_HASWELL_E_GT3 || \
279
+
(devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
280
+
(devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
281
+
(devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
282
+
(devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
283
+
(devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
284
+
(devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
285
+
(devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
286
+
(devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
287
+
(devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
288
+
(devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
289
+
(devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
290
+
(devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
291
+
(devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
292
+
(devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
293
+
(devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
294
+
295
+
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
296
+
IS_HSW_GT2(devid) || \
297
+
IS_HSW_GT3(devid))
298
+
299
+
#define IS_965(devid) (IS_GEN4(devid) || \
300
+
IS_GEN5(devid) || \
301
+
IS_GEN6(devid) || \
302
+
IS_GEN7(devid))
303
+
304
+
#define IS_INTEL(devid) (IS_GEN2(devid) || \
305
+
IS_GEN3(devid) || \
306
+
IS_GEN4(devid) || \
307
+
IS_GEN5(devid) || \
308
+
IS_GEN6(devid) || \
309
+
IS_GEN7(devid))
310
+
311
+
#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
312
+
IS_GEN6(devid) || \
313
+
IS_IVYBRIDGE(devid) || IS_HASWELL(devid))
314
+
315
+
#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
316
+
IS_GEN7(devid))
317
+
318
+
#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
319
+
IS_GEN6(devid) || \
320
+
IS_GEN7(devid))
321
+
322
+
#define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
323
+
(devid) == PCI_CHIP_I965_G_1 || \
324
+
(devid) == PCI_CHIP_I965_Q || \
325
+
(devid) == PCI_CHIP_I965_G)
326
+
327
+
#define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
328
+
(devid) == PCI_CHIP_I965_GME)
329
+
330
+
#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
331
+
332
+
#endif /* _INTEL_CHIPSET_H */
+198
intel_drm.c
+198
intel_drm.c
···
1
+
/*
2
+
* Copyright © 2008 Intel Corporation
3
+
* Copyright (c) 2012, Oracle and/or its affiliates. All rights reserved.
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the "Software"),
7
+
* to deal in the Software without restriction, including without limitation
8
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9
+
* and/or sell copies of the Software, and to permit persons to whom the
10
+
* Software is furnished to do so, subject to the following conditions:
11
+
*
12
+
* The above copyright notice and this permission notice (including the next
13
+
* paragraph) shall be included in all copies or substantial portions of the
14
+
* Software.
15
+
*
16
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22
+
* DEALINGS IN THE SOFTWARE.
23
+
*
24
+
* Authors:
25
+
* Eric Anholt <eric@anholt.net>
26
+
*
27
+
*/
28
+
29
+
#ifdef HAVE_CONFIG_H
30
+
#include "config.h"
31
+
#endif
32
+
33
+
#include <unistd.h>
34
+
#include <stdlib.h>
35
+
#include <stdio.h>
36
+
#include <string.h>
37
+
#include <errno.h>
38
+
#include <err.h>
39
+
#include <assert.h>
40
+
#include <sys/ioctl.h>
41
+
#include <fcntl.h>
42
+
#include <sys/stat.h>
43
+
#include <sys/mman.h>
44
+
#ifdef HAVE_STRUCT_SYSINFO_TOTALRAM
45
+
#include <sys/sysinfo.h>
46
+
#elif defined(HAVE_SWAPCTL) /* Solaris */
47
+
#include <sys/swap.h>
48
+
#endif
49
+
50
+
#include "intel_gpu_tools.h"
51
+
#include "i915_drm.h"
52
+
53
+
uint32_t
54
+
intel_get_drm_devid(int fd)
55
+
{
56
+
int ret;
57
+
struct drm_i915_getparam gp;
58
+
uint32_t devid;
59
+
char *override;
60
+
61
+
override = getenv("INTEL_DEVID_OVERRIDE");
62
+
if (override) {
63
+
devid = strtod(override, NULL);
64
+
} else {
65
+
gp.param = I915_PARAM_CHIPSET_ID;
66
+
gp.value = (int *)&devid;
67
+
68
+
ret = ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
69
+
assert(ret == 0);
70
+
}
71
+
72
+
return devid;
73
+
}
74
+
75
+
int intel_gen(uint32_t devid)
76
+
{
77
+
if (IS_GEN2(devid))
78
+
return 2;
79
+
if (IS_GEN3(devid))
80
+
return 3;
81
+
if (IS_GEN4(devid))
82
+
return 4;
83
+
if (IS_GEN5(devid))
84
+
return 5;
85
+
if (IS_GEN6(devid))
86
+
return 6;
87
+
if (IS_GEN7(devid))
88
+
return 7;
89
+
90
+
return -1;
91
+
}
92
+
93
+
uint64_t
94
+
intel_get_total_ram_mb(void)
95
+
{
96
+
uint64_t retval;
97
+
98
+
#ifdef HAVE_STRUCT_SYSINFO_TOTALRAM /* Linux */
99
+
struct sysinfo sysinf;
100
+
int ret;
101
+
102
+
ret = sysinfo(&sysinf);
103
+
assert(ret == 0);
104
+
105
+
retval = sysinf.totalram;
106
+
retval *= sysinf.mem_unit;
107
+
#elif defined(_SC_PAGESIZE) && defined(_SC_PHYS_PAGES) /* Solaris */
108
+
long pagesize, npages;
109
+
110
+
pagesize = sysconf(_SC_PAGESIZE);
111
+
npages = sysconf(_SC_PHYS_PAGES);
112
+
113
+
retval = (uint64_t) pagesize * npages;
114
+
#else
115
+
#error "Unknown how to get RAM size for this OS"
116
+
#endif
117
+
118
+
return retval / (1024*1024);
119
+
}
120
+
121
+
uint64_t
122
+
intel_get_total_swap_mb(void)
123
+
{
124
+
uint64_t retval;
125
+
126
+
#ifdef HAVE_STRUCT_SYSINFO_TOTALRAM /* Linux */
127
+
struct sysinfo sysinf;
128
+
int ret;
129
+
130
+
ret = sysinfo(&sysinf);
131
+
assert(ret == 0);
132
+
133
+
retval = sysinf.totalswap;
134
+
retval *= sysinf.mem_unit;
135
+
#elif defined(HAVE_SWAPCTL) /* Solaris */
136
+
long pagesize = sysconf(_SC_PAGESIZE);
137
+
uint64_t totalpages = 0;
138
+
swaptbl_t *swt;
139
+
char *buf;
140
+
int n, i;
141
+
142
+
if ((n = swapctl(SC_GETNSWP, NULL)) == -1) {
143
+
perror("swapctl: GETNSWP");
144
+
return 0;
145
+
}
146
+
if (n == 0) {
147
+
/* no error, but no swap devices either */
148
+
return 0;
149
+
}
150
+
151
+
swt = malloc(sizeof(struct swaptable) + (n * sizeof(swapent_t)));
152
+
buf = malloc(n * MAXPATHLEN);
153
+
if (!swt || !buf) {
154
+
perror("malloc");
155
+
} else {
156
+
swt->swt_n = n;
157
+
for (i = 0 ; i < n; i++) {
158
+
swt->swt_ent[i].ste_path = buf + (i * MAXPATHLEN);
159
+
}
160
+
161
+
if ((n = swapctl(SC_LIST, swt)) == -1) {
162
+
perror("swapctl: LIST");
163
+
} else {
164
+
for (i = 0; i < swt->swt_n; i++) {
165
+
totalpages += swt->swt_ent[i].ste_pages;
166
+
}
167
+
}
168
+
}
169
+
free(swt);
170
+
free(buf);
171
+
172
+
retval = (uint64_t) pagesize * totalpages;
173
+
#else
174
+
#warning "Unknown how to get swap size for this OS"
175
+
return 0;
176
+
#endif
177
+
178
+
return retval / (1024*1024);
179
+
}
180
+
181
+
182
+
/*
183
+
* When testing a port to a new platform, create a standalone test binary
184
+
* by running:
185
+
* cc -o porttest intel_drm.c -I.. -DSTANDALONE_TEST `pkg-config --cflags libdrm`
186
+
* and then running the resulting porttest program.
187
+
*/
188
+
#ifdef STANDALONE_TEST
189
+
void *mmio;
190
+
191
+
int main(int argc, char **argv)
192
+
{
193
+
printf("Total RAM: %" PRIu64 " Mb\n", intel_get_total_ram_mb());
194
+
printf("Total Swap: %" PRIu64 " Mb\n", intel_get_total_swap_mb());
195
+
196
+
return 0;
197
+
}
198
+
#endif /* STANDALONE_TEST */
+115
intel_gpu_tools.h
+115
intel_gpu_tools.h
···
1
+
/*
2
+
* Copyright © 2009 Intel Corporation
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice (including the next
12
+
* paragraph) shall be included in all copies or substantial portions of the
13
+
* Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21
+
* DEALINGS IN THE SOFTWARE.
22
+
*
23
+
* Authors:
24
+
* Eric Anholt <eric@anholt.net>
25
+
*
26
+
*/
27
+
28
+
#ifndef INTEL_GPU_TOOLS_H
29
+
#define INTEL_GPU_TOOLS_H
30
+
31
+
#include <stdint.h>
32
+
#include <sys/types.h>
33
+
#include <pciaccess.h>
34
+
35
+
#include "intel_chipset.h"
36
+
#include "intel_reg.h"
37
+
38
+
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))
39
+
40
+
extern void *mmio;
41
+
void intel_get_mmio(struct pci_device *pci_dev);
42
+
43
+
/* New style register access API */
44
+
int intel_register_access_init(struct pci_device *pci_dev, int safe);
45
+
void intel_register_access_fini(void);
46
+
uint32_t intel_register_read(uint32_t reg);
47
+
void intel_register_write(uint32_t reg, uint32_t val);
48
+
int intel_register_access_needs_fakewake(void);
49
+
50
+
/* Following functions are relevant only for SoCs like Valleyview */
51
+
uint32_t intel_dpio_reg_read(uint32_t reg);
52
+
void intel_dpio_reg_write(uint32_t reg, uint32_t val);
53
+
54
+
int intel_punit_read(uint8_t addr, uint32_t *val);
55
+
int intel_punit_write(uint8_t addr, uint32_t val);
56
+
int intel_nc_read(uint8_t addr, uint32_t *val);
57
+
int intel_nc_write(uint8_t addr, uint32_t val);
58
+
59
+
#define INTEL_RANGE_RSVD (0<<0) /* Shouldn't be read or written */
60
+
#define INTEL_RANGE_READ (1<<0)
61
+
#define INTEL_RANGE_WRITE (1<<1)
62
+
#define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE)
63
+
#define INTEL_RANGE_END (1<<31)
64
+
65
+
struct intel_register_range {
66
+
uint32_t base;
67
+
uint32_t size;
68
+
uint32_t flags;
69
+
};
70
+
71
+
struct intel_register_map {
72
+
struct intel_register_range *map;
73
+
uint32_t top;
74
+
uint32_t alignment_mask;
75
+
};
76
+
struct intel_register_map intel_get_register_map(uint32_t devid);
77
+
struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, int mode);
78
+
79
+
80
+
static inline uint32_t
81
+
INREG(uint32_t reg)
82
+
{
83
+
return *(volatile uint32_t *)((volatile char *)mmio + reg);
84
+
}
85
+
86
+
static inline void
87
+
OUTREG(uint32_t reg, uint32_t val)
88
+
{
89
+
*(volatile uint32_t *)((volatile char *)mmio + reg) = val;
90
+
}
91
+
92
+
struct pci_device *intel_get_pci_device(void);
93
+
94
+
uint32_t intel_get_drm_devid(int fd);
95
+
int intel_gen(uint32_t devid);
96
+
uint64_t intel_get_total_ram_mb(void);
97
+
uint64_t intel_get_total_swap_mb(void);
98
+
99
+
void intel_map_file(char *);
100
+
101
+
enum pch_type {
102
+
PCH_NONE,
103
+
PCH_IBX,
104
+
PCH_CPT,
105
+
PCH_LPT,
106
+
};
107
+
108
+
extern enum pch_type pch;
109
+
void intel_check_pch(void);
110
+
111
+
#define HAS_IBX (pch == PCH_IBX)
112
+
#define HAS_CPT (pch == PCH_CPT)
113
+
#define HAS_LPT (pch == PCH_LPT)
114
+
115
+
#endif /* INTEL_GPU_TOOLS_H */
+294
intel_mmio.c
+294
intel_mmio.c
···
1
+
/*
2
+
* Copyright © 2008 Intel Corporation
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice (including the next
12
+
* paragraph) shall be included in all copies or substantial portions of the
13
+
* Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21
+
* DEALINGS IN THE SOFTWARE.
22
+
*
23
+
* Authors:
24
+
* Eric Anholt <eric@anholt.net>
25
+
* Ben Widawsky <ben@bwidawsk.net>
26
+
*
27
+
*/
28
+
29
+
#include <unistd.h>
30
+
#include <fcntl.h>
31
+
#include <stdio.h>
32
+
#include <stdarg.h>
33
+
#include <stdlib.h>
34
+
#include <stdint.h>
35
+
#include <stdbool.h>
36
+
#include <string.h>
37
+
#include <errno.h>
38
+
#include <err.h>
39
+
#include <assert.h>
40
+
#include <sys/ioctl.h>
41
+
#include <sys/stat.h>
42
+
#include <sys/mman.h>
43
+
44
+
#include "intel_gpu_tools.h"
45
+
46
+
#define FAKEKEY 0x2468ace0
47
+
48
+
void *mmio;
49
+
50
+
static struct _mmio_data {
51
+
int inited;
52
+
bool safe;
53
+
char debugfs_path[FILENAME_MAX];
54
+
char debugfs_forcewake_path[FILENAME_MAX];
55
+
uint32_t i915_devid;
56
+
struct intel_register_map map;
57
+
int key;
58
+
} mmio_data;
59
+
60
+
void
61
+
intel_map_file(char *file)
62
+
{
63
+
int fd;
64
+
struct stat st;
65
+
66
+
fd = open(file, O_RDWR);
67
+
if (fd == -1) {
68
+
fprintf(stderr, "Couldn't open %s: %s\n", file,
69
+
strerror(errno));
70
+
exit(1);
71
+
}
72
+
fstat(fd, &st);
73
+
mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
74
+
if (mmio == MAP_FAILED) {
75
+
fprintf(stderr, "Couldn't mmap %s: %s\n", file,
76
+
strerror(errno));
77
+
exit(1);
78
+
}
79
+
close(fd);
80
+
}
81
+
82
+
void
83
+
intel_get_mmio(struct pci_device *pci_dev)
84
+
{
85
+
uint32_t devid, gen;
86
+
int mmio_bar, mmio_size;
87
+
int error;
88
+
89
+
devid = pci_dev->device_id;
90
+
if (IS_GEN2(devid))
91
+
mmio_bar = 1;
92
+
else
93
+
mmio_bar = 0;
94
+
95
+
gen = intel_gen(devid);
96
+
if (gen < 3)
97
+
mmio_size = 512*1024;
98
+
else if (gen < 5)
99
+
mmio_size = 512*1024;
100
+
else
101
+
mmio_size = 2*1024*1024;
102
+
103
+
error = pci_device_map_range (pci_dev,
104
+
pci_dev->regions[mmio_bar].base_addr,
105
+
mmio_size,
106
+
PCI_DEV_MAP_FLAG_WRITABLE,
107
+
&mmio);
108
+
109
+
if (error != 0) {
110
+
fprintf(stderr, "Couldn't map MMIO region: %s\n",
111
+
strerror(error));
112
+
exit(1);
113
+
}
114
+
}
115
+
116
+
/*
117
+
* If successful, i915_debugfs_path and i915_debugfs_forcewake_path are both
118
+
* updated with the correct path.
119
+
*/
120
+
static int
121
+
find_debugfs_path(const char *dri_base)
122
+
{
123
+
char buf[FILENAME_MAX];
124
+
struct stat sb;
125
+
int i, ret;
126
+
127
+
for (i = 0; i < 16; i++) {
128
+
snprintf(buf, FILENAME_MAX, "%s/%i/name", dri_base, i);
129
+
130
+
snprintf(mmio_data.debugfs_path, FILENAME_MAX,
131
+
"%s/%i/", dri_base, i);
132
+
snprintf(mmio_data.debugfs_forcewake_path, FILENAME_MAX,
133
+
"%s/%i/i915_forcewake_user", dri_base, i);
134
+
135
+
ret = stat(mmio_data.debugfs_forcewake_path, &sb);
136
+
if (ret) {
137
+
mmio_data.debugfs_path[0] = 0;
138
+
mmio_data.debugfs_forcewake_path[0] = 0;
139
+
} else
140
+
return 0;
141
+
}
142
+
143
+
return -1;
144
+
}
145
+
146
+
static int
147
+
get_forcewake_lock(void)
148
+
{
149
+
return open(mmio_data.debugfs_forcewake_path, 0);
150
+
}
151
+
152
+
static void
153
+
release_forcewake_lock(int fd)
154
+
{
155
+
close(fd);
156
+
}
157
+
158
+
/* Dumb check to see if i915 was loaded */
159
+
static bool
160
+
i915_loaded(void)
161
+
{
162
+
struct stat sb;
163
+
int ret;
164
+
165
+
ret = stat("/sys/module/i915/", &sb);
166
+
if (ret) {
167
+
return false;
168
+
}
169
+
170
+
assert(S_ISDIR(sb.st_mode));
171
+
return true;
172
+
}
173
+
174
+
/*
175
+
* Initialize register access library.
176
+
*
177
+
* @pci_dev: pci device we're mucking with
178
+
* @safe: use safe register access tables
179
+
*/
180
+
int
181
+
intel_register_access_init(struct pci_device *pci_dev, int safe)
182
+
{
183
+
int ret;
184
+
185
+
/* after old API is deprecated, remove this */
186
+
if (mmio == NULL)
187
+
intel_get_mmio(pci_dev);
188
+
189
+
assert(mmio != NULL);
190
+
191
+
if (mmio_data.inited)
192
+
return -1;
193
+
194
+
mmio_data.safe = (safe != 0 &&
195
+
intel_gen(pci_dev->device_id) >= 4) ? true : false;
196
+
mmio_data.i915_devid = pci_dev->device_id;
197
+
if (mmio_data.safe)
198
+
mmio_data.map = intel_get_register_map(mmio_data.i915_devid);
199
+
200
+
/* Find where the forcewake lock is. Forcewake doesn't exist
201
+
* gen < 6, but the debugfs should do the right things for us.
202
+
*/
203
+
ret = find_debugfs_path("/sys/kernel/debug/dri");
204
+
if (ret) {
205
+
ret = find_debugfs_path("/debug/dri");
206
+
if (ret) {
207
+
fprintf(stderr, "Couldn't find path to dri/debugfs entry\n");
208
+
if (i915_loaded()) {
209
+
fprintf(stderr, "i915 loaded; not proceeding.\n");
210
+
return ret;
211
+
}
212
+
}
213
+
mmio_data.key = FAKEKEY;
214
+
} else
215
+
mmio_data.key = get_forcewake_lock();
216
+
217
+
mmio_data.inited++;
218
+
return 0;
219
+
}
220
+
static int
221
+
intel_register_access_needs_wake(void)
222
+
{
223
+
return mmio_data.key != FAKEKEY;
224
+
}
225
+
226
+
int intel_register_access_needs_fakewake(void)
227
+
{
228
+
return mmio_data.key == FAKEKEY;
229
+
}
230
+
231
+
void
232
+
intel_register_access_fini(void)
233
+
{
234
+
if (mmio_data.key && intel_register_access_needs_wake())
235
+
release_forcewake_lock(mmio_data.key);
236
+
mmio_data.inited--;
237
+
}
238
+
239
+
uint32_t
240
+
intel_register_read(uint32_t reg)
241
+
{
242
+
struct intel_register_range *range;
243
+
uint32_t ret;
244
+
245
+
assert(mmio_data.inited);
246
+
247
+
if (intel_gen(mmio_data.i915_devid) >= 6)
248
+
assert(mmio_data.key != -1);
249
+
250
+
if (!mmio_data.safe)
251
+
goto read_out;
252
+
253
+
range = intel_get_register_range(mmio_data.map,
254
+
reg,
255
+
INTEL_RANGE_READ);
256
+
257
+
if(!range) {
258
+
fprintf(stderr, "Register read blocked for safety "
259
+
"(*0x%08x)\n", reg);
260
+
ret = 0xffffffff;
261
+
goto out;
262
+
}
263
+
264
+
read_out:
265
+
ret = *(volatile uint32_t *)((volatile char *)mmio + reg);
266
+
out:
267
+
return ret;
268
+
}
269
+
270
+
void
271
+
intel_register_write(uint32_t reg, uint32_t val)
272
+
{
273
+
struct intel_register_range *range;
274
+
275
+
assert(mmio_data.inited);
276
+
277
+
if (intel_gen(mmio_data.i915_devid) >= 6)
278
+
assert(mmio_data.key != -1);
279
+
280
+
if (!mmio_data.safe)
281
+
goto write_out;
282
+
283
+
range = intel_get_register_range(mmio_data.map,
284
+
reg,
285
+
INTEL_RANGE_WRITE);
286
+
287
+
if (!range) {
288
+
fprintf(stderr, "Register write blocked for safety "
289
+
"(*0x%08x = 0x%x)\n", reg, val);
290
+
}
291
+
292
+
write_out:
293
+
*(volatile uint32_t *)((volatile char *)mmio + reg) = val;
294
+
}
+123
intel_pci.c
+123
intel_pci.c
···
1
+
/*
2
+
* Copyright © 2008 Intel Corporation
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice (including the next
12
+
* paragraph) shall be included in all copies or substantial portions of the
13
+
* Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21
+
* DEALINGS IN THE SOFTWARE.
22
+
*
23
+
* Authors:
24
+
* Eric Anholt <eric@anholt.net>
25
+
*
26
+
*/
27
+
28
+
#include <unistd.h>
29
+
#include <stdlib.h>
30
+
#include <stdio.h>
31
+
#include <string.h>
32
+
#include <errno.h>
33
+
#include <err.h>
34
+
#include <assert.h>
35
+
#include <sys/ioctl.h>
36
+
#include <fcntl.h>
37
+
#include <sys/stat.h>
38
+
#include <sys/mman.h>
39
+
40
+
#include "intel_gpu_tools.h"
41
+
42
+
enum pch_type pch;
43
+
44
+
struct pci_device *
45
+
intel_get_pci_device(void)
46
+
{
47
+
struct pci_device *pci_dev;
48
+
int error;
49
+
50
+
error = pci_system_init();
51
+
if (error != 0) {
52
+
fprintf(stderr, "Couldn't initialize PCI system: %s\n",
53
+
strerror(error));
54
+
exit(1);
55
+
}
56
+
57
+
/* Grab the graphics card. Try the canonical slot first, then
58
+
* walk the entire PCI bus for a matching device. */
59
+
pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
60
+
if (pci_dev == NULL || pci_dev->vendor_id != 0x8086) {
61
+
struct pci_device_iterator *iter;
62
+
struct pci_id_match match;
63
+
64
+
match.vendor_id = 0x8086; /* Intel */
65
+
match.device_id = PCI_MATCH_ANY;
66
+
match.subvendor_id = PCI_MATCH_ANY;
67
+
match.subdevice_id = PCI_MATCH_ANY;
68
+
69
+
match.device_class = 0x3 << 16;
70
+
match.device_class_mask = 0xff << 16;
71
+
72
+
match.match_data = 0;
73
+
74
+
iter = pci_id_match_iterator_create(&match);
75
+
pci_dev = pci_device_next(iter);
76
+
pci_iterator_destroy(iter);
77
+
}
78
+
if (pci_dev == NULL)
79
+
errx(1, "Couldn't find graphics card");
80
+
81
+
error = pci_device_probe(pci_dev);
82
+
if (error != 0) {
83
+
fprintf(stderr, "Couldn't probe graphics card: %s\n",
84
+
strerror(error));
85
+
exit(1);
86
+
}
87
+
88
+
if (pci_dev->vendor_id != 0x8086)
89
+
errx(1, "Graphics card is non-intel");
90
+
91
+
return pci_dev;
92
+
}
93
+
94
+
void
95
+
intel_check_pch(void)
96
+
{
97
+
struct pci_device *pch_dev;
98
+
99
+
pch_dev = pci_device_find_by_slot(0, 0, 31, 0);
100
+
if (pch_dev == NULL)
101
+
return;
102
+
103
+
if (pch_dev->vendor_id != 0x8086)
104
+
return;
105
+
106
+
switch (pch_dev->device_id & 0xff00) {
107
+
case 0x3b00:
108
+
pch = PCH_IBX;
109
+
break;
110
+
case 0x1c00:
111
+
case 0x1e00:
112
+
pch = PCH_CPT;
113
+
break;
114
+
case 0x8c00:
115
+
case 0x9c00:
116
+
pch = PCH_LPT;
117
+
break;
118
+
default:
119
+
pch = PCH_NONE;
120
+
return;
121
+
}
122
+
}
123
+
+3818
intel_reg.h
+3818
intel_reg.h
···
1
+
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/i810/i810_reg.h,v 1.13 2003/02/06 04:18:04 dawes Exp $ */
2
+
/**************************************************************************
3
+
4
+
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
5
+
All Rights Reserved.
6
+
7
+
Permission is hereby granted, free of charge, to any person obtaining a
8
+
copy of this software and associated documentation files (the
9
+
"Software"), to deal in the Software without restriction, including
10
+
without limitation the rights to use, copy, modify, merge, publish,
11
+
distribute, sub license, and/or sell copies of the Software, and to
12
+
permit persons to whom the Software is furnished to do so, subject to
13
+
the following conditions:
14
+
15
+
The above copyright notice and this permission notice (including the
16
+
next paragraph) shall be included in all copies or substantial portions
17
+
of the Software.
18
+
19
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20
+
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21
+
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22
+
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
23
+
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24
+
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25
+
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26
+
27
+
**************************************************************************/
28
+
29
+
/** @file
30
+
* Register names and fields for Intel graphics.
31
+
*/
32
+
33
+
/*
34
+
* Authors:
35
+
* Keith Whitwell <keith@tungstengraphics.com>
36
+
* Eric Anholt <eric@anholt.net>
37
+
*
38
+
* based on the i740 driver by
39
+
* Kevin E. Martin <kevin@precisioninsight.com>
40
+
*
41
+
*
42
+
*/
43
+
44
+
#ifndef _I810_REG_H
45
+
#define _I810_REG_H
46
+
47
+
/* I/O register offsets
48
+
*/
49
+
#define SRX 0x3C4 /* p208 */
50
+
#define GRX 0x3CE /* p213 */
51
+
#define ARX 0x3C0 /* p224 */
52
+
53
+
/* VGA Color Palette Registers */
54
+
#define DACMASK 0x3C6 /* p232 */
55
+
#define DACSTATE 0x3C7 /* p232 */
56
+
#define DACRX 0x3C7 /* p233 */
57
+
#define DACWX 0x3C8 /* p233 */
58
+
#define DACDATA 0x3C9 /* p233 */
59
+
60
+
/* CRT Controller Registers (CRX) */
61
+
#define START_ADDR_HI 0x0C /* p246 */
62
+
#define START_ADDR_LO 0x0D /* p247 */
63
+
#define VERT_SYNC_END 0x11 /* p249 */
64
+
#define EXT_VERT_TOTAL 0x30 /* p257 */
65
+
#define EXT_VERT_DISPLAY 0x31 /* p258 */
66
+
#define EXT_VERT_SYNC_START 0x32 /* p259 */
67
+
#define EXT_VERT_BLANK_START 0x33 /* p260 */
68
+
#define EXT_HORIZ_TOTAL 0x35 /* p261 */
69
+
#define EXT_HORIZ_BLANK 0x39 /* p261 */
70
+
#define EXT_START_ADDR 0x40 /* p262 */
71
+
#define EXT_START_ADDR_ENABLE 0x80
72
+
#define EXT_OFFSET 0x41 /* p263 */
73
+
#define EXT_START_ADDR_HI 0x42 /* p263 */
74
+
#define INTERLACE_CNTL 0x70 /* p264 */
75
+
#define INTERLACE_ENABLE 0x80
76
+
#define INTERLACE_DISABLE 0x00
77
+
78
+
/* Miscellaneous Output Register
79
+
*/
80
+
#define MSR_R 0x3CC /* p207 */
81
+
#define MSR_W 0x3C2 /* p207 */
82
+
#define IO_ADDR_SELECT 0x01
83
+
84
+
#define MDA_BASE 0x3B0 /* p207 */
85
+
#define CGA_BASE 0x3D0 /* p207 */
86
+
87
+
/* CR80 - IO Control, p264
88
+
*/
89
+
#define IO_CTNL 0x80
90
+
#define EXTENDED_ATTR_CNTL 0x02
91
+
#define EXTENDED_CRTC_CNTL 0x01
92
+
93
+
/* GR10 - Address mapping, p221
94
+
*/
95
+
#define ADDRESS_MAPPING 0x10
96
+
#define PAGE_TO_LOCAL_MEM_ENABLE 0x10
97
+
#define GTT_MEM_MAP_ENABLE 0x08
98
+
#define PACKED_MODE_ENABLE 0x04
99
+
#define LINEAR_MODE_ENABLE 0x02
100
+
#define PAGE_MAPPING_ENABLE 0x01
101
+
102
+
#define HOTKEY_VBIOS_SWITCH_BLOCK 0x80
103
+
#define HOTKEY_SWITCH 0x20
104
+
#define HOTKEY_TOGGLE 0x10
105
+
106
+
/* Blitter control, p378
107
+
*/
108
+
#define BITBLT_CNTL 0x7000c
109
+
#define COLEXP_MODE 0x30
110
+
#define COLEXP_8BPP 0x00
111
+
#define COLEXP_16BPP 0x10
112
+
#define COLEXP_24BPP 0x20
113
+
#define COLEXP_RESERVED 0x30
114
+
#define BITBLT_STATUS 0x01
115
+
116
+
#define CHDECMISC 0x10111
117
+
#define DCC 0x10200
118
+
#define C0DRB0 0x10200
119
+
#define C0DRB1 0x10202
120
+
#define C0DRB2 0x10204
121
+
#define C0DRB3 0x10206
122
+
#define C0DRA01 0x10208
123
+
#define C0DRA23 0x1020a
124
+
#define C1DRB0 0x10600
125
+
#define C1DRB1 0x10602
126
+
#define C1DRB2 0x10604
127
+
#define C1DRB3 0x10606
128
+
#define C1DRA01 0x10608
129
+
#define C1DRA23 0x1060a
130
+
131
+
/* p375.
132
+
*/
133
+
#define DISPLAY_CNTL 0x70008
134
+
#define VGA_WRAP_MODE 0x02
135
+
#define VGA_WRAP_AT_256KB 0x00
136
+
#define VGA_NO_WRAP 0x02
137
+
#define GUI_MODE 0x01
138
+
#define STANDARD_VGA_MODE 0x00
139
+
#define HIRES_MODE 0x01
140
+
141
+
/* p375
142
+
*/
143
+
#define PIXPIPE_CONFIG_0 0x70009
144
+
#define DAC_8_BIT 0x80
145
+
#define DAC_6_BIT 0x00
146
+
#define HW_CURSOR_ENABLE 0x10
147
+
#define EXTENDED_PALETTE 0x01
148
+
149
+
/* p375
150
+
*/
151
+
#define PIXPIPE_CONFIG_1 0x7000a
152
+
#define DISPLAY_COLOR_MODE 0x0F
153
+
#define DISPLAY_VGA_MODE 0x00
154
+
#define DISPLAY_8BPP_MODE 0x02
155
+
#define DISPLAY_15BPP_MODE 0x04
156
+
#define DISPLAY_16BPP_MODE 0x05
157
+
#define DISPLAY_24BPP_MODE 0x06
158
+
#define DISPLAY_32BPP_MODE 0x07
159
+
160
+
/* p375
161
+
*/
162
+
#define PIXPIPE_CONFIG_2 0x7000b
163
+
#define DISPLAY_GAMMA_ENABLE 0x08
164
+
#define DISPLAY_GAMMA_DISABLE 0x00
165
+
#define OVERLAY_GAMMA_ENABLE 0x04
166
+
#define OVERLAY_GAMMA_DISABLE 0x00
167
+
168
+
169
+
/* p380
170
+
*/
171
+
#define DISPLAY_BASE 0x70020
172
+
#define DISPLAY_BASE_MASK 0x03fffffc
173
+
174
+
175
+
/* Cursor control registers, pp383-384
176
+
*/
177
+
/* Desktop (845G, 865G) */
178
+
#define CURSOR_CONTROL 0x70080
179
+
#define CURSOR_ENABLE 0x80000000
180
+
#define CURSOR_GAMMA_ENABLE 0x40000000
181
+
#define CURSOR_STRIDE_MASK 0x30000000
182
+
#define CURSOR_FORMAT_SHIFT 24
183
+
#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
184
+
#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
185
+
#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
186
+
#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
187
+
#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
188
+
#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
189
+
190
+
/* Mobile and i810 */
191
+
#define CURSOR_A_CONTROL CURSOR_CONTROL
192
+
#define CURSOR_ORIGIN_SCREEN 0x00 /* i810 only */
193
+
#define CURSOR_ORIGIN_DISPLAY 0x1 /* i810 only */
194
+
#define CURSOR_MODE 0x27
195
+
#define CURSOR_MODE_DISABLE 0x00
196
+
#define CURSOR_MODE_32_4C_AX 0x01 /* i810 only */
197
+
#define CURSOR_MODE_64_3C 0x04
198
+
#define CURSOR_MODE_64_4C_AX 0x05
199
+
#define CURSOR_MODE_64_4C 0x06
200
+
#define CURSOR_MODE_64_32B_AX 0x07
201
+
#define CURSOR_MODE_64_ARGB_AX (0x20 | CURSOR_MODE_64_32B_AX)
202
+
#define MCURSOR_PIPE_SELECT (1 << 28)
203
+
#define MCURSOR_PIPE_A 0x00
204
+
#define MCURSOR_PIPE_B (1 << 28)
205
+
#define MCURSOR_GAMMA_ENABLE (1 << 26)
206
+
#define MCURSOR_MEM_TYPE_LOCAL (1 << 25)
207
+
208
+
209
+
#define CURSOR_BASEADDR 0x70084
210
+
#define CURSOR_A_BASE CURSOR_BASEADDR
211
+
#define CURSOR_BASEADDR_MASK 0x1FFFFF00
212
+
#define CURSOR_A_POSITION 0x70088
213
+
#define CURSOR_POS_SIGN 0x8000
214
+
#define CURSOR_POS_MASK 0x007FF
215
+
#define CURSOR_X_SHIFT 0
216
+
#define CURSOR_Y_SHIFT 16
217
+
#define CURSOR_X_LO 0x70088
218
+
#define CURSOR_X_HI 0x70089
219
+
#define CURSOR_X_POS 0x00
220
+
#define CURSOR_X_NEG 0x80
221
+
#define CURSOR_Y_LO 0x7008A
222
+
#define CURSOR_Y_HI 0x7008B
223
+
#define CURSOR_Y_POS 0x00
224
+
#define CURSOR_Y_NEG 0x80
225
+
226
+
#define CURSOR_A_PALETTE0 0x70090
227
+
#define CURSOR_A_PALETTE1 0x70094
228
+
#define CURSOR_A_PALETTE2 0x70098
229
+
#define CURSOR_A_PALETTE3 0x7009C
230
+
231
+
#define CURSOR_SIZE 0x700A0
232
+
#define CURSOR_SIZE_MASK 0x3FF
233
+
#define CURSOR_SIZE_HSHIFT 0
234
+
#define CURSOR_SIZE_VSHIFT 12
235
+
236
+
#define CURSOR_B_CONTROL 0x700C0
237
+
#define CURSOR_B_BASE 0x700C4
238
+
#define CURSOR_B_POSITION 0x700C8
239
+
#define CURSOR_B_PALETTE0 0x700D0
240
+
#define CURSOR_B_PALETTE1 0x700D4
241
+
#define CURSOR_B_PALETTE2 0x700D8
242
+
#define CURSOR_B_PALETTE3 0x700DC
243
+
244
+
245
+
/* Similar registers exist in Device 0 on the i810 (pp55-65), but I'm
246
+
* not sure they refer to local (graphics) memory.
247
+
*
248
+
* These details are for the local memory control registers,
249
+
* (pp301-310). The test machines are not equiped with local memory,
250
+
* so nothing is tested. Only a single row seems to be supported.
251
+
*/
252
+
#define DRAM_ROW_TYPE 0x3000
253
+
#define DRAM_ROW_0 0x01
254
+
#define DRAM_ROW_0_SDRAM 0x01
255
+
#define DRAM_ROW_0_EMPTY 0x00
256
+
#define DRAM_ROW_CNTL_LO 0x3001
257
+
#define DRAM_PAGE_MODE_CTRL 0x10
258
+
#define DRAM_RAS_TO_CAS_OVRIDE 0x08
259
+
#define DRAM_CAS_LATENCY 0x04
260
+
#define DRAM_RAS_TIMING 0x02
261
+
#define DRAM_RAS_PRECHARGE 0x01
262
+
#define DRAM_ROW_CNTL_HI 0x3002
263
+
#define DRAM_REFRESH_RATE 0x18
264
+
#define DRAM_REFRESH_DISABLE 0x00
265
+
#define DRAM_REFRESH_60HZ 0x08
266
+
#define DRAM_REFRESH_FAST_TEST 0x10
267
+
#define DRAM_REFRESH_RESERVED 0x18
268
+
#define DRAM_SMS 0x07
269
+
#define DRAM_SMS_NORMAL 0x00
270
+
#define DRAM_SMS_NOP_ENABLE 0x01
271
+
#define DRAM_SMS_ABPCE 0x02
272
+
#define DRAM_SMS_MRCE 0x03
273
+
#define DRAM_SMS_CBRCE 0x04
274
+
275
+
/* p307
276
+
*/
277
+
#define DPMS_SYNC_SELECT 0x5002
278
+
#define VSYNC_CNTL 0x08
279
+
#define VSYNC_ON 0x00
280
+
#define VSYNC_OFF 0x08
281
+
#define HSYNC_CNTL 0x02
282
+
#define HSYNC_ON 0x00
283
+
#define HSYNC_OFF 0x02
284
+
285
+
#define GPIOA 0x5010
286
+
#define GPIOB 0x5014
287
+
#define GPIOC 0x5018
288
+
#define GPIOD 0x501c
289
+
#define GPIOE 0x5020
290
+
#define GPIOF 0x5024
291
+
#define GPIOG 0x5028
292
+
#define GPIOH 0x502c
293
+
# define GPIO_CLOCK_DIR_MASK (1 << 0)
294
+
# define GPIO_CLOCK_DIR_IN (0 << 1)
295
+
# define GPIO_CLOCK_DIR_OUT (1 << 1)
296
+
# define GPIO_CLOCK_VAL_MASK (1 << 2)
297
+
# define GPIO_CLOCK_VAL_OUT (1 << 3)
298
+
# define GPIO_CLOCK_VAL_IN (1 << 4)
299
+
# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
300
+
# define GPIO_DATA_DIR_MASK (1 << 8)
301
+
# define GPIO_DATA_DIR_IN (0 << 9)
302
+
# define GPIO_DATA_DIR_OUT (1 << 9)
303
+
# define GPIO_DATA_VAL_MASK (1 << 10)
304
+
# define GPIO_DATA_VAL_OUT (1 << 11)
305
+
# define GPIO_DATA_VAL_IN (1 << 12)
306
+
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
307
+
308
+
/* GMBus registers for hardware-assisted (non-bitbanging) I2C access */
309
+
#define GMBUS0 0x5100
310
+
#define GMBUS1 0x5104
311
+
#define GMBUS2 0x5108
312
+
#define GMBUS3 0x510c
313
+
#define GMBUS4 0x5110
314
+
#define GMBUS5 0x5120
315
+
316
+
/* p317, 319
317
+
*/
318
+
#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
319
+
#define VCLK2_VCO_N 0x600a
320
+
#define VCLK2_VCO_DIV_SEL 0x6012
321
+
322
+
#define VCLK_DIVISOR_VGA0 0x6000
323
+
#define VCLK_DIVISOR_VGA1 0x6004
324
+
#define VCLK_POST_DIV 0x6010
325
+
/** Selects a post divisor of 4 instead of 2. */
326
+
# define VGA1_PD_P2_DIV_4 (1 << 15)
327
+
/** Overrides the p2 post divisor field */
328
+
# define VGA1_PD_P1_DIV_2 (1 << 13)
329
+
# define VGA1_PD_P1_SHIFT 8
330
+
/** P1 value is 2 greater than this field */
331
+
# define VGA1_PD_P1_MASK (0x1f << 8)
332
+
/** Selects a post divisor of 4 instead of 2. */
333
+
# define VGA0_PD_P2_DIV_4 (1 << 7)
334
+
/** Overrides the p2 post divisor field */
335
+
# define VGA0_PD_P1_DIV_2 (1 << 5)
336
+
# define VGA0_PD_P1_SHIFT 0
337
+
/** P1 value is 2 greater than this field */
338
+
# define VGA0_PD_P1_MASK (0x1f << 0)
339
+
340
+
#define POST_DIV_SELECT 0x70
341
+
#define POST_DIV_1 0x00
342
+
#define POST_DIV_2 0x10
343
+
#define POST_DIV_4 0x20
344
+
#define POST_DIV_8 0x30
345
+
#define POST_DIV_16 0x40
346
+
#define POST_DIV_32 0x50
347
+
#define VCO_LOOP_DIV_BY_4M 0x00
348
+
#define VCO_LOOP_DIV_BY_16M 0x04
349
+
350
+
351
+
/* Instruction Parser Mode Register
352
+
* - p281
353
+
* - 2 new bits.
354
+
*/
355
+
#define INST_PM 0x20c0
356
+
#define AGP_SYNC_PACKET_FLUSH_ENABLE 0x20 /* reserved */
357
+
#define SYNC_PACKET_FLUSH_ENABLE 0x10
358
+
#define TWO_D_INST_DISABLE 0x08
359
+
#define THREE_D_INST_DISABLE 0x04
360
+
#define STATE_VAR_UPDATE_DISABLE 0x02
361
+
#define PAL_STIP_DISABLE 0x01
362
+
#define GEN6_GLOBAL_DEBUG_ENABLE 0x10
363
+
364
+
365
+
#define MEMMODE 0x20dc
366
+
367
+
368
+
/* Instruction parser error register. p279
369
+
*/
370
+
#define IPEIR 0x2088
371
+
#define IPEHR 0x208C
372
+
373
+
#define INST_DONE 0x2090
374
+
# define IDCT_DONE (1 << 30)
375
+
# define IQ_DONE (1 << 29)
376
+
# define PR_DONE (1 << 28)
377
+
# define VLD_DONE (1 << 27)
378
+
# define IP_DONE (1 << 26)
379
+
# define FBC_DONE (1 << 25)
380
+
# define BINNER_DONE (1 << 24)
381
+
# define SF_DONE (1 << 23)
382
+
# define SE_DONE (1 << 22)
383
+
# define WM_DONE (1 << 21)
384
+
# define IZ_DONE (1 << 20)
385
+
# define PERSPECTIVE_INTERP_DONE (1 << 19)
386
+
# define DISPATCHER_DONE (1 << 18)
387
+
# define PROJECTION_DONE (1 << 17)
388
+
# define DEPENDENT_ADDRESS_DONE (1 << 16)
389
+
# define QUAD_CACHE_DONE (1 << 15)
390
+
# define TEXTURE_FETCH_DONE (1 << 14)
391
+
# define TEXTURE_DECOMPRESS_DONE (1 << 13)
392
+
# define SAMPLER_CACHE_DONE (1 << 12)
393
+
# define FILTER_DONE (1 << 11)
394
+
# define BYPASS_FIFO_DONE (1 << 10)
395
+
# define PS_DONE (1 << 9)
396
+
# define CC_DONE (1 << 8)
397
+
# define MAP_FILTER_DONE (1 << 7)
398
+
# define MAP_L2_IDLE (1 << 6)
399
+
# define RING_2_ENABLE (1 << 2)
400
+
# define RING_1_ENABLE (1 << 1)
401
+
# define RING_0_ENABLE (1 << 0)
402
+
403
+
# define I830_GMBUS_DONE (1 << 26)
404
+
# define I830_FBC_DONE (1 << 25)
405
+
# define I830_BINNER_DONE (1 << 24)
406
+
# define I830_MPEG_DONE (1 << 23)
407
+
# define I830_MECO_DONE (1 << 22)
408
+
# define I830_MCD_DONE (1 << 21)
409
+
# define I830_MCSTP_DONE (1 << 20)
410
+
# define I830_CC_DONE (1 << 19)
411
+
# define I830_DG_DONE (1 << 18)
412
+
# define I830_DCMP_DONE (1 << 17)
413
+
# define I830_FTCH_DONE (1 << 16)
414
+
# define I830_IT_DONE (1 << 15)
415
+
# define I830_MG_DONE (1 << 14)
416
+
# define I830_MEC_DONE (1 << 13)
417
+
# define I830_PC_DONE (1 << 12)
418
+
# define I830_QCC_DONE (1 << 11)
419
+
# define I830_TB_DONE (1 << 10)
420
+
# define I830_WM_DONE (1 << 9)
421
+
# define I830_EF_DONE (1 << 8)
422
+
# define I830_BLITTER_DONE (1 << 7)
423
+
# define I830_MAP_L2_DONE (1 << 6)
424
+
# define I830_SECONDARY_RING_3_DONE (1 << 5)
425
+
# define I830_SECONDARY_RING_2_DONE (1 << 4)
426
+
# define I830_SECONDARY_RING_1_DONE (1 << 3)
427
+
# define I830_SECONDARY_RING_0_DONE (1 << 2)
428
+
# define I830_PRIMARY_RING_1_DONE (1 << 1)
429
+
# define I830_PRIMARY_RING_0_DONE (1 << 0)
430
+
431
+
#define NOP_ID 0x2094
432
+
433
+
#define SCPD0 0x209c /* debug */
434
+
#define INST_PS 0x20c4
435
+
#define IPEIR_I965 0x2064 /* i965 */
436
+
#define IPEHR_I965 0x2068 /* i965 */
437
+
#define INST_DONE_I965 0x206c
438
+
# define I965_ROW_0_EU_0_DONE (1 << 31)
439
+
# define I965_ROW_0_EU_1_DONE (1 << 30)
440
+
# define I965_ROW_0_EU_2_DONE (1 << 29)
441
+
# define I965_ROW_0_EU_3_DONE (1 << 28)
442
+
# define I965_ROW_1_EU_0_DONE (1 << 27)
443
+
# define I965_ROW_1_EU_1_DONE (1 << 26)
444
+
# define I965_ROW_1_EU_2_DONE (1 << 25)
445
+
# define I965_ROW_1_EU_3_DONE (1 << 24)
446
+
# define I965_SF_DONE (1 << 23)
447
+
# define I965_SE_DONE (1 << 22)
448
+
# define I965_WM_DONE (1 << 21)
449
+
# define I965_DISPATCHER_DONE (1 << 18)
450
+
# define I965_PROJECTION_DONE (1 << 17)
451
+
# define I965_DG_DONE (1 << 16)
452
+
# define I965_QUAD_CACHE_DONE (1 << 15)
453
+
# define I965_TEXTURE_FETCH_DONE (1 << 14)
454
+
# define I965_TEXTURE_DECOMPRESS_DONE (1 << 13)
455
+
# define I965_SAMPLER_CACHE_DONE (1 << 12)
456
+
# define I965_FILTER_DONE (1 << 11)
457
+
# define I965_BYPASS_DONE (1 << 10)
458
+
# define I965_PS_DONE (1 << 9)
459
+
# define I965_CC_DONE (1 << 8)
460
+
# define I965_MAP_FILTER_DONE (1 << 7)
461
+
# define I965_MAP_L2_IDLE (1 << 6)
462
+
# define I965_MA_ROW_0_DONE (1 << 5)
463
+
# define I965_MA_ROW_1_DONE (1 << 4)
464
+
# define I965_IC_ROW_0_DONE (1 << 3)
465
+
# define I965_IC_ROW_1_DONE (1 << 2)
466
+
# define I965_CP_DONE (1 << 1)
467
+
# define I965_RING_0_ENABLE (1 << 0)
468
+
469
+
# define ILK_ROW_0_EU_0_DONE (1 << 31)
470
+
# define ILK_ROW_0_EU_1_DONE (1 << 30)
471
+
# define ILK_ROW_0_EU_2_DONE (1 << 29)
472
+
# define ILK_ROW_0_EU_3_DONE (1 << 28)
473
+
# define ILK_ROW_1_EU_0_DONE (1 << 27)
474
+
# define ILK_ROW_1_EU_1_DONE (1 << 26)
475
+
# define ILK_ROW_1_EU_2_DONE (1 << 25)
476
+
# define ILK_ROW_1_EU_3_DONE (1 << 24)
477
+
# define ILK_ROW_2_EU_0_DONE (1 << 23)
478
+
# define ILK_ROW_2_EU_1_DONE (1 << 22)
479
+
# define ILK_ROW_2_EU_2_DONE (1 << 21)
480
+
# define ILK_ROW_2_EU_3_DONE (1 << 20)
481
+
# define ILK_VCP_DONE (1 << 19)
482
+
# define ILK_ROW_0_MATH_DONE (1 << 18)
483
+
# define ILK_ROW_1_MATH_DONE (1 << 17)
484
+
# define ILK_ROW_2_MATH_DONE (1 << 16)
485
+
# define ILK_VC1_DONE (1 << 15)
486
+
# define ILK_ROW_0_MA_DONE (1 << 14)
487
+
# define ILK_ROW_1_MA_DONE (1 << 13)
488
+
# define ILK_ROW_2_MA_DONE (1 << 12)
489
+
# define ILK_ROW_0_ISC_DONE (1 << 11)
490
+
# define ILK_ROW_1_ISC_DONE (1 << 10)
491
+
# define ILK_ROW_2_ISC_DONE (1 << 9)
492
+
# define ILK_VFE_DONE (1 << 8)
493
+
# define ILK_TD_DONE (1 << 7)
494
+
# define ILK_SVTS_DONE (1 << 6)
495
+
# define ILK_TS_DONE (1 << 5)
496
+
# define ILK_GW_DONE (1 << 4)
497
+
# define ILK_AI_DONE (1 << 3)
498
+
# define ILK_AC_DONE (1 << 2)
499
+
# define ILK_AM_DONE (1 << 1)
500
+
501
+
#define GEN6_INSTDONE_1 0x206c
502
+
# define GEN6_MA_3_DONE (1 << 31)
503
+
# define GEN6_EU_32_DONE (1 << 30)
504
+
# define GEN6_EU_31_DONE (1 << 29)
505
+
# define GEN6_EU_30_DONE (1 << 28)
506
+
# define GEN6_MA_2_DONE (1 << 27)
507
+
# define GEN6_EU_22_DONE (1 << 26)
508
+
# define GEN6_EU_21_DONE (1 << 25)
509
+
# define GEN6_EU_20_DONE (1 << 24)
510
+
# define GEN6_MA_1_DONE (1 << 23)
511
+
# define GEN6_EU_12_DONE (1 << 22)
512
+
# define GEN6_EU_11_DONE (1 << 21)
513
+
# define GEN6_EU_10_DONE (1 << 20)
514
+
# define GEN6_MA_0_DONE (1 << 19)
515
+
# define GEN6_EU_02_DONE (1 << 18)
516
+
# define GEN6_EU_01_DONE (1 << 17)
517
+
# define GEN6_EU_00_DONE (1 << 16)
518
+
# define GEN6_IC_3_DONE (1 << 15)
519
+
# define GEN6_IC_2_DONE (1 << 14)
520
+
# define GEN6_IC_1_DONE (1 << 13)
521
+
# define GEN6_IC_0_DONE (1 << 12)
522
+
# define GEN6_ISC_10_DONE (1 << 11)
523
+
# define GEN6_ISC_32_DONE (1 << 10)
524
+
# define GEN6_VSC_DONE (1 << 9)
525
+
# define GEN6_IEF_DONE (1 << 8)
526
+
# define GEN6_VFE_DONE (1 << 7)
527
+
# define GEN6_TD_DONE (1 << 6)
528
+
# define GEN6_TS_DONE (1 << 4)
529
+
# define GEN6_GW_DONE (1 << 3)
530
+
# define GEN6_HIZ_DONE (1 << 2)
531
+
# define GEN6_AVS_DONE (1 << 1)
532
+
533
+
#define INST_PS_I965 0x2070
534
+
535
+
/* Current active ring head address:
536
+
*/
537
+
#define ACTHD_I965 0x2074
538
+
#define ACTHD 0x20C8
539
+
540
+
/* Current primary/secondary DMA fetch addresses:
541
+
*/
542
+
#define DMA_FADD_P 0x2078
543
+
#define DMA_FADD_S 0x20d4
544
+
#define INST_DONE_1 0x207c
545
+
# define I965_GW_CS_DONE_CR (1 << 19)
546
+
# define I965_SVSM_CS_DONE_CR (1 << 18)
547
+
# define I965_SVDW_CS_DONE_CR (1 << 17)
548
+
# define I965_SVDR_CS_DONE_CR (1 << 16)
549
+
# define I965_SVRW_CS_DONE_CR (1 << 15)
550
+
# define I965_SVRR_CS_DONE_CR (1 << 14)
551
+
# define I965_SVTW_CS_DONE_CR (1 << 13)
552
+
# define I965_MASM_CS_DONE_CR (1 << 12)
553
+
# define I965_MASF_CS_DONE_CR (1 << 11)
554
+
# define I965_MAW_CS_DONE_CR (1 << 10)
555
+
# define I965_EM1_CS_DONE_CR (1 << 9)
556
+
# define I965_EM0_CS_DONE_CR (1 << 8)
557
+
# define I965_UC1_CS_DONE (1 << 7)
558
+
# define I965_UC0_CS_DONE (1 << 6)
559
+
# define I965_URB_CS_DONE (1 << 5)
560
+
# define I965_ISC_CS_DONE (1 << 4)
561
+
# define I965_CL_CS_DONE (1 << 3)
562
+
# define I965_GS_CS_DONE (1 << 2)
563
+
# define I965_VS0_CS_DONE (1 << 1)
564
+
# define I965_VF_CS_DONE (1 << 0)
565
+
566
+
# define G4X_BCS_DONE (1 << 31)
567
+
# define G4X_CS_DONE (1 << 30)
568
+
# define G4X_MASF_DONE (1 << 29)
569
+
# define G4X_SVDW_DONE (1 << 28)
570
+
# define G4X_SVDR_DONE (1 << 27)
571
+
# define G4X_SVRW_DONE (1 << 26)
572
+
# define G4X_SVRR_DONE (1 << 25)
573
+
# define G4X_ISC_DONE (1 << 24)
574
+
# define G4X_MT_DONE (1 << 23)
575
+
# define G4X_RC_DONE (1 << 22)
576
+
# define G4X_DAP_DONE (1 << 21)
577
+
# define G4X_MAWB_DONE (1 << 20)
578
+
# define G4X_MT_IDLE (1 << 19)
579
+
# define G4X_GBLT_BUSY (1 << 18)
580
+
# define G4X_SVSM_DONE (1 << 17)
581
+
# define G4X_MASM_DONE (1 << 16)
582
+
# define G4X_QC_DONE (1 << 15)
583
+
# define G4X_FL_DONE (1 << 14)
584
+
# define G4X_SC_DONE (1 << 13)
585
+
# define G4X_DM_DONE (1 << 12)
586
+
# define G4X_FT_DONE (1 << 11)
587
+
# define G4X_DG_DONE (1 << 10)
588
+
# define G4X_SI_DONE (1 << 9)
589
+
# define G4X_SO_DONE (1 << 8)
590
+
# define G4X_PL_DONE (1 << 7)
591
+
# define G4X_WIZ_DONE (1 << 6)
592
+
# define G4X_URB_DONE (1 << 5)
593
+
# define G4X_SF_DONE (1 << 4)
594
+
# define G4X_CL_DONE (1 << 3)
595
+
# define G4X_GS_DONE (1 << 2)
596
+
# define G4X_VS0_DONE (1 << 1)
597
+
# define G4X_VF_DONE (1 << 0)
598
+
599
+
#define GEN6_INSTDONE_2 0x207c
600
+
# define GEN6_GAM_DONE (1 << 31)
601
+
# define GEN6_CS_DONE (1 << 30)
602
+
# define GEN6_WMBE_DONE (1 << 29)
603
+
# define GEN6_SVRW_DONE (1 << 28)
604
+
# define GEN6_RCC_DONE (1 << 27)
605
+
# define GEN6_SVG_DONE (1 << 26)
606
+
# define GEN6_ISC_DONE (1 << 25)
607
+
# define GEN6_MT_DONE (1 << 24)
608
+
# define GEN6_RCPFE_DONE (1 << 23)
609
+
# define GEN6_RCPBE_DONE (1 << 22)
610
+
# define GEN6_VDI_DONE (1 << 21)
611
+
# define GEN6_RCZ_DONE (1 << 20)
612
+
# define GEN6_DAP_DONE (1 << 19)
613
+
# define GEN6_PSD_DONE (1 << 18)
614
+
# define GEN6_IZ_DONE (1 << 17)
615
+
# define GEN6_WMFE_DONE (1 << 16)
616
+
# define GEN6_SVSM_DONE (1 << 15)
617
+
# define GEN6_QC_DONE (1 << 14)
618
+
# define GEN6_FL_DONE (1 << 13)
619
+
# define GEN6_SC_DONE (1 << 12)
620
+
# define GEN6_DM_DONE (1 << 11)
621
+
# define GEN6_FT_DONE (1 << 10)
622
+
# define GEN6_DG_DONE (1 << 9)
623
+
# define GEN6_SI_DONE (1 << 8)
624
+
# define GEN6_SO_DONE (1 << 7)
625
+
# define GEN6_PL_DONE (1 << 6)
626
+
# define GEN6_VME_DONE (1 << 5)
627
+
# define GEN6_SF_DONE (1 << 4)
628
+
# define GEN6_CL_DONE (1 << 3)
629
+
# define GEN6_GS_DONE (1 << 2)
630
+
# define GEN6_VS0_DONE (1 << 1)
631
+
# define GEN6_VF_DONE (1 << 0)
632
+
633
+
#define CACHE_MODE_0 0x2120
634
+
#define CACHE_MODE_1 0x2124
635
+
#define MI_MODE 0x209c
636
+
#define MI_DISPLAY_POWER_DOWN 0x20e0
637
+
#define MI_ARB_STATE 0x20e4
638
+
#define MI_RDRET_STATE 0x20fc
639
+
640
+
/* Start addresses for each of the primary rings:
641
+
*/
642
+
#define PR0_STR 0x20f0
643
+
#define PR1_STR 0x20f4
644
+
#define PR2_STR 0x20f8
645
+
646
+
#define WIZ_CTL 0x7c00
647
+
#define WIZ_CTL_SINGLE_SUBSPAN (1<<6)
648
+
#define WIZ_CTL_IGNORE_STALLS (1<<5)
649
+
650
+
#define SVG_WORK_CTL 0x7408
651
+
652
+
#define TS_CTL 0x7e00
653
+
#define TS_MUX_ERR_CODE (0<<8)
654
+
#define TS_MUX_URB_0 (1<<8)
655
+
#define TS_MUX_DISPATCH_ID_0 (10<<8)
656
+
#define TS_MUX_ERR_CODE_VALID (15<<8)
657
+
#define TS_MUX_TID_0 (16<<8)
658
+
#define TS_MUX_EUID_0 (18<<8)
659
+
#define TS_MUX_FFID_0 (22<<8)
660
+
#define TS_MUX_EOT (26<<8)
661
+
#define TS_MUX_SIDEBAND_0 (27<<8)
662
+
#define TS_SNAP_ALL_CHILD (1<<2)
663
+
#define TS_SNAP_ALL_ROOT (1<<1)
664
+
#define TS_SNAP_ENABLE (1<<0)
665
+
666
+
#define TS_DEBUG_DATA 0x7e0c
667
+
668
+
#define TD_CTL 0x8000
669
+
#define TD_CTL2 0x8004
670
+
671
+
672
+
#define ECOSKPD 0x21d0
673
+
#define EXCC 0x2028
674
+
675
+
/* I965 debug regs:
676
+
*/
677
+
#define IA_VERTICES_COUNT_QW 0x2310
678
+
#define IA_PRIMITIVES_COUNT_QW 0x2318
679
+
#define VS_INVOCATION_COUNT_QW 0x2320
680
+
#define GS_INVOCATION_COUNT_QW 0x2328
681
+
#define GS_PRIMITIVES_COUNT_QW 0x2330
682
+
#define CL_INVOCATION_COUNT_QW 0x2338
683
+
#define CL_PRIMITIVES_COUNT_QW 0x2340
684
+
#define PS_INVOCATION_COUNT_QW 0x2348
685
+
#define PS_DEPTH_COUNT_QW 0x2350
686
+
#define TIMESTAMP_QW 0x2358
687
+
#define CLKCMP_QW 0x2360
688
+
689
+
690
+
691
+
692
+
693
+
694
+
/* General error reporting regs, p296
695
+
*/
696
+
#define EIR 0x20B0
697
+
#define EMR 0x20B4
698
+
#define ESR 0x20B8
699
+
# define ERR_VERTEX_MAX (1 << 5) /* lpt/cst */
700
+
# define ERR_PGTBL_ERROR (1 << 4)
701
+
# define ERR_DISPLAY_OVERLAY_UNDERRUN (1 << 3)
702
+
# define ERR_MAIN_MEMORY_REFRESH (1 << 1)
703
+
# define ERR_INSTRUCTION_ERROR (1 << 0)
704
+
705
+
706
+
/* Interrupt Control Registers
707
+
* - new bits for i810
708
+
* - new register hwstam (mask)
709
+
*/
710
+
#define HWS_PGA 0x2080
711
+
#define PWRCTXA 0x2088 /* 965GM+ only */
712
+
#define PWRCTX_EN (1<<0)
713
+
#define HWSTAM 0x2098 /* p290 */
714
+
#define IER 0x20a0 /* p291 */
715
+
#define IIR 0x20a4 /* p292 */
716
+
#define IMR 0x20a8 /* p293 */
717
+
#define ISR 0x20ac /* p294 */
718
+
#define HW_ERROR 0x8000
719
+
#define SYNC_STATUS_TOGGLE 0x1000
720
+
#define DPY_0_FLIP_PENDING 0x0800
721
+
#define DPY_1_FLIP_PENDING 0x0400 /* not implemented on i810 */
722
+
#define OVL_0_FLIP_PENDING 0x0200
723
+
#define OVL_1_FLIP_PENDING 0x0100 /* not implemented on i810 */
724
+
#define DPY_0_VBLANK 0x0080
725
+
#define DPY_0_EVENT 0x0040
726
+
#define DPY_1_VBLANK 0x0020 /* not implemented on i810 */
727
+
#define DPY_1_EVENT 0x0010 /* not implemented on i810 */
728
+
#define HOST_PORT_EVENT 0x0008 /* */
729
+
#define CAPTURE_EVENT 0x0004 /* */
730
+
#define USER_DEFINED 0x0002
731
+
#define BREAKPOINT 0x0001
732
+
733
+
734
+
#define INTR_RESERVED (0x6000 | \
735
+
DPY_1_FLIP_PENDING | \
736
+
OVL_1_FLIP_PENDING | \
737
+
DPY_1_VBLANK | \
738
+
DPY_1_EVENT | \
739
+
HOST_PORT_EVENT | \
740
+
CAPTURE_EVENT )
741
+
742
+
/* FIFO Watermark and Burst Length Control Register
743
+
*
744
+
* - different offset and contents on i810 (p299) (fewer bits per field)
745
+
* - some overlay fields added
746
+
* - what does it all mean?
747
+
*/
748
+
#define FWATER_BLC 0x20d8
749
+
#define FWATER_BLC2 0x20dc
750
+
#define MM_BURST_LENGTH 0x00700000
751
+
#define MM_FIFO_WATERMARK 0x0001F000
752
+
#define LM_BURST_LENGTH 0x00000700
753
+
#define LM_FIFO_WATERMARK 0x0000001F
754
+
755
+
756
+
/* Fence/Tiling ranges [0..7]
757
+
*/
758
+
#define FENCE 0x2000
759
+
#define FENCE_NR 8
760
+
761
+
#define FENCE_NEW 0x3000
762
+
#define FENCE_NEW_NR 16
763
+
764
+
#define FENCE_LINEAR 0
765
+
#define FENCE_XMAJOR 1
766
+
#define FENCE_YMAJOR 2
767
+
768
+
#define I915G_FENCE_START_MASK 0x0ff00000
769
+
770
+
#define I830_FENCE_START_MASK 0x07f80000
771
+
772
+
#define FENCE_START_MASK 0x03F80000
773
+
#define FENCE_X_MAJOR 0x00000000
774
+
#define FENCE_Y_MAJOR 0x00001000
775
+
#define FENCE_SIZE_MASK 0x00000700
776
+
#define FENCE_SIZE_512K 0x00000000
777
+
#define FENCE_SIZE_1M 0x00000100
778
+
#define FENCE_SIZE_2M 0x00000200
779
+
#define FENCE_SIZE_4M 0x00000300
780
+
#define FENCE_SIZE_8M 0x00000400
781
+
#define FENCE_SIZE_16M 0x00000500
782
+
#define FENCE_SIZE_32M 0x00000600
783
+
#define FENCE_SIZE_64M 0x00000700
784
+
#define I915G_FENCE_SIZE_1M 0x00000000
785
+
#define I915G_FENCE_SIZE_2M 0x00000100
786
+
#define I915G_FENCE_SIZE_4M 0x00000200
787
+
#define I915G_FENCE_SIZE_8M 0x00000300
788
+
#define I915G_FENCE_SIZE_16M 0x00000400
789
+
#define I915G_FENCE_SIZE_32M 0x00000500
790
+
#define I915G_FENCE_SIZE_64M 0x00000600
791
+
#define I915G_FENCE_SIZE_128M 0x00000700
792
+
#define I965_FENCE_X_MAJOR 0x00000000
793
+
#define I965_FENCE_Y_MAJOR 0x00000002
794
+
#define FENCE_PITCH_1 0x00000000
795
+
#define FENCE_PITCH_2 0x00000010
796
+
#define FENCE_PITCH_4 0x00000020
797
+
#define FENCE_PITCH_8 0x00000030
798
+
#define FENCE_PITCH_16 0x00000040
799
+
#define FENCE_PITCH_32 0x00000050
800
+
#define FENCE_PITCH_64 0x00000060
801
+
#define FENCE_VALID 0x00000001
802
+
803
+
#define FENCE_REG_SANDYBRIDGE_0 0x100000
804
+
805
+
/* Registers to control page table, p274
806
+
*/
807
+
#define PGETBL_CTL 0x2020
808
+
#define PGETBL_ADDR_MASK 0xFFFFF000
809
+
#define PGETBL_ENABLE_MASK 0x00000001
810
+
#define PGETBL_ENABLED 0x00000001
811
+
/** Added in 965G, this field has the actual size of the global GTT */
812
+
#define PGETBL_SIZE_MASK 0x0000000e
813
+
#define PGETBL_SIZE_512KB (0 << 1)
814
+
#define PGETBL_SIZE_256KB (1 << 1)
815
+
#define PGETBL_SIZE_128KB (2 << 1)
816
+
#define PGETBL_SIZE_1MB (3 << 1)
817
+
#define PGETBL_SIZE_2MB (4 << 1)
818
+
#define PGETBL_SIZE_1_5MB (5 << 1)
819
+
#define G33_PGETBL_SIZE_MASK (3 << 8)
820
+
#define G33_PGETBL_SIZE_1M (1 << 8)
821
+
#define G33_PGETBL_SIZE_2M (2 << 8)
822
+
823
+
#define I830_PTE_BASE 0x10000
824
+
#define PTE_ADDRESS_MASK 0xfffff000
825
+
#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
826
+
#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
827
+
#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
828
+
#define PTE_MAPPING_TYPE_CACHED (3 << 1)
829
+
#define PTE_MAPPING_TYPE_MASK (3 << 1)
830
+
#define PTE_VALID (1 << 0)
831
+
832
+
/** @defgroup PGE_ERR
833
+
* @{
834
+
*/
835
+
/** Page table debug register for i845 */
836
+
#define PGE_ERR 0x2024
837
+
#define PGE_ERR_ADDR_MASK 0xFFFFF000
838
+
#define PGE_ERR_ID_MASK 0x00000038
839
+
#define PGE_ERR_CAPTURE 0x00000000
840
+
#define PGE_ERR_OVERLAY 0x00000008
841
+
#define PGE_ERR_DISPLAY 0x00000010
842
+
#define PGE_ERR_HOST 0x00000018
843
+
#define PGE_ERR_RENDER 0x00000020
844
+
#define PGE_ERR_BLITTER 0x00000028
845
+
#define PGE_ERR_MAPPING 0x00000030
846
+
#define PGE_ERR_CMD_PARSER 0x00000038
847
+
#define PGE_ERR_TYPE_MASK 0x00000007
848
+
#define PGE_ERR_INV_TABLE 0x00000000
849
+
#define PGE_ERR_INV_PTE 0x00000001
850
+
#define PGE_ERR_MIXED_TYPES 0x00000002
851
+
#define PGE_ERR_PAGE_MISS 0x00000003
852
+
#define PGE_ERR_ILLEGAL_TRX 0x00000004
853
+
#define PGE_ERR_LOCAL_MEM 0x00000005
854
+
#define PGE_ERR_TILED 0x00000006
855
+
/** @} */
856
+
857
+
/** @defgroup PGTBL_ER
858
+
* @{
859
+
*/
860
+
/** Page table debug register for i945 */
861
+
# define PGTBL_ER 0x2024
862
+
# define PGTBL_ERR_MT_TILING (1 << 27)
863
+
# define PGTBL_ERR_MT_GTT_PTE (1 << 26)
864
+
# define PGTBL_ERR_LC_TILING (1 << 25)
865
+
# define PGTBL_ERR_LC_GTT_PTE (1 << 24)
866
+
# define PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE (1 << 23)
867
+
# define PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE (1 << 22)
868
+
# define PGTBL_ERR_CS_VERTEXDATA_GTT_PTE (1 << 21)
869
+
# define PGTBL_ERR_CS_INSTRUCTION_GTT_PTE (1 << 20)
870
+
# define PGTBL_ERR_CS_GTT (1 << 19)
871
+
# define PGTBL_ERR_OVERLAY_TILING (1 << 18)
872
+
# define PGTBL_ERR_OVERLAY_GTT_PTE (1 << 16)
873
+
# define PGTBL_ERR_DISPC_TILING (1 << 14)
874
+
# define PGTBL_ERR_DISPC_GTT_PTE (1 << 12)
875
+
# define PGTBL_ERR_DISPB_TILING (1 << 10)
876
+
# define PGTBL_ERR_DISPB_GTT_PTE (1 << 8)
877
+
# define PGTBL_ERR_DISPA_TILING (1 << 6)
878
+
# define PGTBL_ERR_DISPA_GTT_PTE (1 << 4)
879
+
# define PGTBL_ERR_HOST_PTE_DATA (1 << 1)
880
+
# define PGTBL_ERR_HOST_GTT_PTE (1 << 0)
881
+
/** @} */
882
+
883
+
/* Ring buffer registers, p277, overview p19
884
+
*/
885
+
#define LP_RING 0x2030
886
+
#define HP_RING 0x2040
887
+
888
+
#define RING_TAIL 0x00
889
+
#define TAIL_ADDR 0x000FFFF8
890
+
#define I830_TAIL_MASK 0x001FFFF8
891
+
892
+
#define RING_HEAD 0x04
893
+
#define HEAD_WRAP_COUNT 0xFFE00000
894
+
#define HEAD_WRAP_ONE 0x00200000
895
+
#define HEAD_ADDR 0x001FFFFC
896
+
#define I830_HEAD_MASK 0x001FFFFC
897
+
898
+
#define RING_START 0x08
899
+
#define START_ADDR 0x03FFFFF8
900
+
#define I830_RING_START_MASK 0xFFFFF000
901
+
902
+
#define RING_LEN 0x0C
903
+
#define RING_NR_PAGES 0x001FF000
904
+
#define I830_RING_NR_PAGES 0x001FF000
905
+
#define RING_REPORT_MASK 0x00000006
906
+
#define RING_REPORT_64K 0x00000002
907
+
#define RING_REPORT_128K 0x00000004
908
+
#define RING_NO_REPORT 0x00000000
909
+
#define RING_VALID_MASK 0x00000001
910
+
#define RING_VALID 0x00000001
911
+
#define RING_INVALID 0x00000000
912
+
913
+
914
+
915
+
/* BitBlt Instructions
916
+
*
917
+
* There are many more masks & ranges yet to add.
918
+
*/
919
+
#define BR00_BITBLT_CLIENT 0x40000000
920
+
#define BR00_OP_COLOR_BLT 0x10000000
921
+
#define BR00_OP_SRC_COPY_BLT 0x10C00000
922
+
#define BR00_OP_FULL_BLT 0x11400000
923
+
#define BR00_OP_MONO_SRC_BLT 0x11800000
924
+
#define BR00_OP_MONO_SRC_COPY_BLT 0x11000000
925
+
#define BR00_OP_MONO_PAT_BLT 0x11C00000
926
+
#define BR00_OP_MONO_SRC_COPY_IMMEDIATE_BLT (0x61 << 22)
927
+
#define BR00_OP_TEXT_IMMEDIATE_BLT 0xc000000
928
+
929
+
930
+
#define BR00_TPCY_DISABLE 0x00000000
931
+
#define BR00_TPCY_ENABLE 0x00000010
932
+
933
+
#define BR00_TPCY_ROP 0x00000000
934
+
#define BR00_TPCY_NO_ROP 0x00000020
935
+
#define BR00_TPCY_EQ 0x00000000
936
+
#define BR00_TPCY_NOT_EQ 0x00000040
937
+
938
+
#define BR00_PAT_MSB_FIRST 0x00000000 /* ? */
939
+
940
+
#define BR00_PAT_VERT_ALIGN 0x000000e0
941
+
942
+
#define BR00_LENGTH 0x0000000F
943
+
944
+
#define BR09_DEST_ADDR 0x03FFFFFF
945
+
946
+
#define BR11_SOURCE_PITCH 0x00003FFF
947
+
948
+
#define BR12_SOURCE_ADDR 0x03FFFFFF
949
+
950
+
#define BR13_SOLID_PATTERN 0x80000000
951
+
#define BR13_RIGHT_TO_LEFT 0x40000000
952
+
#define BR13_LEFT_TO_RIGHT 0x00000000
953
+
#define BR13_MONO_TRANSPCY 0x20000000
954
+
#define BR13_MONO_PATN_TRANS 0x10000000
955
+
#define BR13_USE_DYN_DEPTH 0x04000000
956
+
#define BR13_DYN_8BPP 0x00000000
957
+
#define BR13_DYN_16BPP 0x01000000
958
+
#define BR13_DYN_24BPP 0x02000000
959
+
#define BR13_ROP_MASK 0x00FF0000
960
+
#define BR13_DEST_PITCH 0x0000FFFF
961
+
#define BR13_PITCH_SIGN_BIT 0x00008000
962
+
963
+
#define BR14_DEST_HEIGHT 0xFFFF0000
964
+
#define BR14_DEST_WIDTH 0x0000FFFF
965
+
966
+
#define BR15_PATTERN_ADDR 0x03FFFFFF
967
+
968
+
#define BR16_SOLID_PAT_COLOR 0x00FFFFFF
969
+
#define BR16_BACKGND_PAT_CLR 0x00FFFFFF
970
+
971
+
#define BR17_FGND_PAT_CLR 0x00FFFFFF
972
+
973
+
#define BR18_SRC_BGND_CLR 0x00FFFFFF
974
+
#define BR19_SRC_FGND_CLR 0x00FFFFFF
975
+
976
+
977
+
/* Instruction parser instructions
978
+
*/
979
+
980
+
#define INST_PARSER_CLIENT 0x00000000
981
+
#define INST_OP_FLUSH 0x02000000
982
+
#define INST_FLUSH_MAP_CACHE 0x00000001
983
+
984
+
985
+
#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
986
+
987
+
988
+
/* Registers in the i810 host-pci bridge pci config space which affect
989
+
* the i810 graphics operations.
990
+
*/
991
+
#define SMRAM_MISCC 0x70
992
+
#define GMS 0x000000c0
993
+
#define GMS_DISABLE 0x00000000
994
+
#define GMS_ENABLE_BARE 0x00000040
995
+
#define GMS_ENABLE_512K 0x00000080
996
+
#define GMS_ENABLE_1M 0x000000c0
997
+
#define USMM 0x00000030
998
+
#define USMM_DISABLE 0x00000000
999
+
#define USMM_TSEG_ZERO 0x00000010
1000
+
#define USMM_TSEG_512K 0x00000020
1001
+
#define USMM_TSEG_1M 0x00000030
1002
+
#define GFX_MEM_WIN_SIZE 0x00010000
1003
+
#define GFX_MEM_WIN_32M 0x00010000
1004
+
#define GFX_MEM_WIN_64M 0x00000000
1005
+
1006
+
/* Overkill? I don't know. Need to figure out top of mem to make the
1007
+
* SMRAM calculations come out. Linux seems to have problems
1008
+
* detecting it all on its own, so this seems a reasonable double
1009
+
* check to any user supplied 'mem=...' boot param.
1010
+
*
1011
+
* ... unfortunately this reg doesn't work according to spec on the
1012
+
* test hardware.
1013
+
*/
1014
+
#define WHTCFG_PAMR_DRP 0x50
1015
+
#define SYS_DRAM_ROW_0_SHIFT 16
1016
+
#define SYS_DRAM_ROW_1_SHIFT 20
1017
+
#define DRAM_MASK 0x0f
1018
+
#define DRAM_VALUE_0 0
1019
+
#define DRAM_VALUE_1 8
1020
+
/* No 2 value defined */
1021
+
#define DRAM_VALUE_3 16
1022
+
#define DRAM_VALUE_4 16
1023
+
#define DRAM_VALUE_5 24
1024
+
#define DRAM_VALUE_6 32
1025
+
#define DRAM_VALUE_7 32
1026
+
#define DRAM_VALUE_8 48
1027
+
#define DRAM_VALUE_9 64
1028
+
#define DRAM_VALUE_A 64
1029
+
#define DRAM_VALUE_B 96
1030
+
#define DRAM_VALUE_C 128
1031
+
#define DRAM_VALUE_D 128
1032
+
#define DRAM_VALUE_E 192
1033
+
#define DRAM_VALUE_F 256 /* nice one, geezer */
1034
+
#define LM_FREQ_MASK 0x10
1035
+
#define LM_FREQ_133 0x10
1036
+
#define LM_FREQ_100 0x00
1037
+
1038
+
1039
+
1040
+
1041
+
/* These are 3d state registers, but the state is invarient, so we let
1042
+
* the X server handle it:
1043
+
*/
1044
+
1045
+
1046
+
1047
+
/* GFXRENDERSTATE_COLOR_CHROMA_KEY, p135
1048
+
*/
1049
+
#define GFX_OP_COLOR_CHROMA_KEY ((0x3<<29)|(0x1d<<24)|(0x2<<16)|0x1)
1050
+
#define CC1_UPDATE_KILL_WRITE (1<<28)
1051
+
#define CC1_ENABLE_KILL_WRITE (1<<27)
1052
+
#define CC1_DISABLE_KILL_WRITE 0
1053
+
#define CC1_UPDATE_COLOR_IDX (1<<26)
1054
+
#define CC1_UPDATE_CHROMA_LOW (1<<25)
1055
+
#define CC1_UPDATE_CHROMA_HI (1<<24)
1056
+
#define CC1_CHROMA_LOW_MASK ((1<<24)-1)
1057
+
#define CC2_COLOR_IDX_SHIFT 24
1058
+
#define CC2_COLOR_IDX_MASK (0xff<<24)
1059
+
#define CC2_CHROMA_HI_MASK ((1<<24)-1)
1060
+
1061
+
1062
+
#define GFX_CMD_CONTEXT_SEL ((0<<29)|(0x5<<23))
1063
+
#define CS_UPDATE_LOAD (1<<17)
1064
+
#define CS_UPDATE_USE (1<<16)
1065
+
#define CS_UPDATE_LOAD (1<<17)
1066
+
#define CS_LOAD_CTX0 0
1067
+
#define CS_LOAD_CTX1 (1<<8)
1068
+
#define CS_USE_CTX0 0
1069
+
#define CS_USE_CTX1 (1<<0)
1070
+
1071
+
/* I810 LCD/TV registers */
1072
+
#define LCD_TV_HTOTAL 0x60000
1073
+
#define LCD_TV_C 0x60018
1074
+
#define LCD_TV_OVRACT 0x6001C
1075
+
1076
+
#define LCD_TV_ENABLE (1 << 31)
1077
+
#define LCD_TV_VGAMOD (1 << 28)
1078
+
1079
+
/* I830 CRTC registers */
1080
+
#define HTOTAL_A 0x60000
1081
+
#define HBLANK_A 0x60004
1082
+
#define HSYNC_A 0x60008
1083
+
#define VTOTAL_A 0x6000c
1084
+
#define VBLANK_A 0x60010
1085
+
#define VSYNC_A 0x60014
1086
+
#define PIPEASRC 0x6001c
1087
+
#define BCLRPAT_A 0x60020
1088
+
#define VSYNCSHIFT_A 0x60028
1089
+
1090
+
#define HTOTAL_B 0x61000
1091
+
#define HBLANK_B 0x61004
1092
+
#define HSYNC_B 0x61008
1093
+
#define VTOTAL_B 0x6100c
1094
+
#define VBLANK_B 0x61010
1095
+
#define VSYNC_B 0x61014
1096
+
#define PIPEBSRC 0x6101c
1097
+
#define BCLRPAT_B 0x61020
1098
+
#define VSYNCSHIFT_B 0x61028
1099
+
1100
+
#define HTOTAL_C 0x62000
1101
+
#define HBLANK_C 0x62004
1102
+
#define HSYNC_C 0x62008
1103
+
#define VTOTAL_C 0x6200c
1104
+
#define VBLANK_C 0x62010
1105
+
#define VSYNC_C 0x62014
1106
+
#define PIPECSRC 0x6201c
1107
+
#define BCLRPAT_C 0x62020
1108
+
#define VSYNCSHIFT_C 0x62028
1109
+
1110
+
#define HTOTAL_EDP 0x6F000
1111
+
#define HBLANK_EDP 0x6F004
1112
+
#define HSYNC_EDP 0x6F008
1113
+
#define VTOTAL_EDP 0x6F00c
1114
+
#define VBLANK_EDP 0x6F010
1115
+
#define VSYNC_EDP 0x6F014
1116
+
#define VSYNCSHIFT_EDP 0x6F028
1117
+
1118
+
#define PP_STATUS 0x61200
1119
+
# define PP_ON (1 << 31)
1120
+
/**
1121
+
* Indicates that all dependencies of the panel are on:
1122
+
*
1123
+
* - PLL enabled
1124
+
* - pipe enabled
1125
+
* - LVDS/DVOB/DVOC on
1126
+
*/
1127
+
# define PP_READY (1 << 30)
1128
+
# define PP_SEQUENCE_NONE (0 << 28)
1129
+
# define PP_SEQUENCE_ON (1 << 28)
1130
+
# define PP_SEQUENCE_OFF (2 << 28)
1131
+
# define PP_SEQUENCE_MASK 0x30000000
1132
+
1133
+
#define PP_CONTROL 0x61204
1134
+
# define POWER_DOWN_ON_RESET (1 << 1)
1135
+
# define POWER_TARGET_ON (1 << 0)
1136
+
1137
+
#define PP_ON_DELAYS 0x61208
1138
+
#define PP_OFF_DELAYS 0x6120c
1139
+
#define PP_DIVISOR 0x61210
1140
+
1141
+
#define PFIT_CONTROL 0x61230
1142
+
# define PFIT_ENABLE (1 << 31)
1143
+
/* Pre-965 */
1144
+
# define VERT_INTERP_DISABLE (0 << 10)
1145
+
# define VERT_INTERP_BILINEAR (1 << 10)
1146
+
# define VERT_INTERP_MASK (3 << 10)
1147
+
# define VERT_AUTO_SCALE (1 << 9)
1148
+
# define HORIZ_INTERP_DISABLE (0 << 6)
1149
+
# define HORIZ_INTERP_BILINEAR (1 << 6)
1150
+
# define HORIZ_INTERP_MASK (3 << 6)
1151
+
# define HORIZ_AUTO_SCALE (1 << 5)
1152
+
# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1153
+
/* 965+ */
1154
+
# define PFIT_PIPE_MASK (3 << 29)
1155
+
# define PFIT_PIPE_SHIFT 29
1156
+
# define PFIT_SCALING_MODE_MASK (7 << 26)
1157
+
# define PFIT_SCALING_AUTO (0 << 26)
1158
+
# define PFIT_SCALING_PROGRAMMED (1 << 26)
1159
+
# define PFIT_SCALING_PILLAR (2 << 26)
1160
+
# define PFIT_SCALING_LETTER (3 << 26)
1161
+
# define PFIT_FILTER_SELECT_MASK (3 << 24)
1162
+
# define PFIT_FILTER_FUZZY (0 << 24)
1163
+
# define PFIT_FILTER_CRISP (1 << 24)
1164
+
# define PFIT_FILTER_MEDIAN (2 << 24)
1165
+
1166
+
#define PFIT_PGM_RATIOS 0x61234
1167
+
/* Pre-965 */
1168
+
# define PFIT_VERT_SCALE_SHIFT 20
1169
+
# define PFIT_VERT_SCALE_MASK 0xfff00000
1170
+
# define PFIT_HORIZ_SCALE_SHIFT 4
1171
+
# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1172
+
/* 965+ */
1173
+
# define PFIT_VERT_SCALE_SHIFT_965 16
1174
+
# define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1175
+
# define PFIT_HORIZ_SCALE_SHIFT_965 0
1176
+
# define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1177
+
1178
+
#define DPLL_A 0x06014
1179
+
#define DPLL_B 0x06018
1180
+
# define DPLL_VCO_ENABLE (1 << 31)
1181
+
# define DPLL_DVO_HIGH_SPEED (1 << 30)
1182
+
# define DPLL_SYNCLOCK_ENABLE (1 << 29)
1183
+
# define DPLL_VGA_MODE_DIS (1 << 28)
1184
+
# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1185
+
# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1186
+
# define DPLL_MODE_MASK (3 << 26)
1187
+
# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1188
+
# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1189
+
# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1190
+
# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1191
+
# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1192
+
# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1193
+
# define DPLL_FPA01_P1_POST_DIV_MASK_IGD 0x00ff8000 /* IGD */
1194
+
/**
1195
+
* The i830 generation, in DAC/serial mode, defines p1 as two plus this
1196
+
* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
1197
+
*/
1198
+
# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1199
+
/**
1200
+
* The i830 generation, in LVDS mode, defines P1 as the bit number set within
1201
+
* this field (only one bit may be set).
1202
+
*/
1203
+
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1204
+
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1205
+
# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
1206
+
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
1207
+
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1208
+
# define PLL_REF_INPUT_DREFCLK (0 << 13)
1209
+
# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1210
+
# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* Ironlake: 120M SSC */
1211
+
# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1212
+
# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1213
+
# define PLL_REF_INPUT_MASK (3 << 13)
1214
+
# define PLL_REF_INPUT_DMICLK (5 << 13) /* Ironlake: DMI refclk */
1215
+
# define PLL_LOAD_PULSE_PHASE_SHIFT 9
1216
+
/*
1217
+
* Parallel to Serial Load Pulse phase selection.
1218
+
* Selects the phase for the 10X DPLL clock for the PCIe
1219
+
* digital display port. The range is 4 to 13; 10 or more
1220
+
* is just a flip delay. The default is 6
1221
+
*/
1222
+
# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1223
+
# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1224
+
/* Ironlake */
1225
+
# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1226
+
# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1227
+
# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT)
1228
+
# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1229
+
# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1230
+
1231
+
/**
1232
+
* SDVO multiplier for 945G/GM. Not used on 965.
1233
+
*
1234
+
* \sa DPLL_MD_UDI_MULTIPLIER_MASK
1235
+
*/
1236
+
# define SDVO_MULTIPLIER_MASK 0x000000ff
1237
+
# define SDVO_MULTIPLIER_SHIFT_HIRES 4
1238
+
# define SDVO_MULTIPLIER_SHIFT_VGA 0
1239
+
1240
+
/** @defgroup DPLL_MD
1241
+
* @{
1242
+
*/
1243
+
/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
1244
+
#define DPLL_A_MD 0x0601c
1245
+
/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
1246
+
#define DPLL_B_MD 0x06020
1247
+
/**
1248
+
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
1249
+
*
1250
+
* Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1251
+
*/
1252
+
# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1253
+
# define DPLL_MD_UDI_DIVIDER_SHIFT 24
1254
+
/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1255
+
# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1256
+
# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1257
+
/**
1258
+
* SDVO/UDI pixel multiplier.
1259
+
*
1260
+
* SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1261
+
* clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1262
+
* modes, the bus rate would be below the limits, so SDVO allows for stuffing
1263
+
* dummy bytes in the datastream at an increased clock rate, with both sides of
1264
+
* the link knowing how many bytes are fill.
1265
+
*
1266
+
* So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1267
+
* rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1268
+
* set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1269
+
* through an SDVO command.
1270
+
*
1271
+
* This register field has values of multiplication factor minus 1, with
1272
+
* a maximum multiplier of 5 for SDVO.
1273
+
*/
1274
+
# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1275
+
# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1276
+
/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1277
+
* This best be set to the default value (3) or the CRT won't work. No,
1278
+
* I don't entirely understand what this does...
1279
+
*/
1280
+
# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1281
+
# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1282
+
/** @} */
1283
+
1284
+
#define DPLL_TEST 0x606c
1285
+
# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1286
+
# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1287
+
# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1288
+
# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1289
+
# define DPLLB_TEST_N_BYPASS (1 << 19)
1290
+
# define DPLLB_TEST_M_BYPASS (1 << 18)
1291
+
# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1292
+
# define DPLLA_TEST_N_BYPASS (1 << 3)
1293
+
# define DPLLA_TEST_M_BYPASS (1 << 2)
1294
+
# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1295
+
1296
+
#define D_STATE 0x6104
1297
+
#define DSPCLK_GATE_D 0x6200
1298
+
# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1299
+
# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1300
+
# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1301
+
# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1302
+
# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1303
+
# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1304
+
# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1305
+
# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1306
+
# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1307
+
# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1308
+
# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1309
+
# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1310
+
# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1311
+
# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1312
+
# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1313
+
# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1314
+
# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1315
+
# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1316
+
# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1317
+
# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1318
+
# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1319
+
# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1320
+
# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1321
+
# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1322
+
# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1323
+
# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1324
+
# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1325
+
# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1326
+
/**
1327
+
* This bit must be set on the 830 to prevent hangs when turning off the
1328
+
* overlay scaler.
1329
+
*/
1330
+
# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1331
+
# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1332
+
# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1333
+
# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1334
+
# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1335
+
1336
+
#define RENCLK_GATE_D1 0x6204
1337
+
# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1338
+
# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1339
+
# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1340
+
# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1341
+
# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1342
+
# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1343
+
# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1344
+
# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1345
+
# define MAG_CLOCK_GATE_DISABLE (1 << 5)
1346
+
/** This bit must be unset on 855,865 */
1347
+
# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1348
+
# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1349
+
# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1350
+
# define MECO_CLOCK_GATE_DISABLE (1 << 1)
1351
+
/** This bit must be set on 855,865. */
1352
+
# define SV_CLOCK_GATE_DISABLE (1 << 0)
1353
+
# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1354
+
# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1355
+
# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1356
+
# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1357
+
# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1358
+
# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1359
+
# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1360
+
# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1361
+
# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1362
+
# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1363
+
# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1364
+
# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1365
+
# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1366
+
# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1367
+
# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1368
+
# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1369
+
# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1370
+
1371
+
# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1372
+
/** This bit must always be set on 965G/965GM */
1373
+
# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1374
+
# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1375
+
# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1376
+
# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1377
+
# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1378
+
# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1379
+
/** This bit must always be set on 965G */
1380
+
# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1381
+
# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1382
+
# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1383
+
# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1384
+
# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1385
+
# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1386
+
# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1387
+
# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1388
+
# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1389
+
# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1390
+
# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1391
+
# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1392
+
# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1393
+
# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1394
+
# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1395
+
# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1396
+
# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1397
+
# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1398
+
# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1399
+
1400
+
#define RENCLK_GATE_D2 0x6208
1401
+
#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1402
+
#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1403
+
#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1404
+
#define RAMCLK_GATE_D 0x6210 /* CRL only */
1405
+
#define DEUC 0x6214 /* CRL only */
1406
+
1407
+
/*
1408
+
* This is a PCI config space register to manipulate backlight brightness
1409
+
* It is used when the BLM_LEGACY_MODE is turned on. When enabled, the first
1410
+
* byte of this config register sets brightness within the range from
1411
+
* 0 to 0xff
1412
+
*/
1413
+
#define LEGACY_BACKLIGHT_BRIGHTNESS 0xf4
1414
+
1415
+
#define BLC_PWM_CTL 0x61254
1416
+
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1417
+
#define BACKLIGHT_MODULATION_FREQ_SHIFT2 (16)
1418
+
/**
1419
+
* This is the most significant 15 bits of the number of backlight cycles in a
1420
+
* complete cycle of the modulated backlight control.
1421
+
*
1422
+
* The actual value is this field multiplied by two.
1423
+
*/
1424
+
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1425
+
#define BACKLIGHT_MODULATION_FREQ_MASK2 (0xffff << 16)
1426
+
#define BLM_LEGACY_MODE (1 << 16)
1427
+
1428
+
/**
1429
+
* This is the number of cycles out of the backlight modulation cycle for which
1430
+
* the backlight is on.
1431
+
*
1432
+
* This field must be no greater than the number of cycles in the complete
1433
+
* backlight modulation cycle.
1434
+
*/
1435
+
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1436
+
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1437
+
1438
+
/* On 965+ backlight control is in another register */
1439
+
#define BLC_PWM_CTL2 0x61250
1440
+
#define BLM_LEGACY_MODE2 (1 << 30)
1441
+
1442
+
#define BLM_CTL 0x61260
1443
+
#define BLM_THRESHOLD_0 0x61270
1444
+
#define BLM_THRESHOLD_1 0x61274
1445
+
#define BLM_THRESHOLD_2 0x61278
1446
+
#define BLM_THRESHOLD_3 0x6127c
1447
+
#define BLM_THRESHOLD_4 0x61280
1448
+
#define BLM_THRESHOLD_5 0x61284
1449
+
1450
+
#define BLM_ACCUMULATOR_0 0x61290
1451
+
#define BLM_ACCUMULATOR_1 0x61294
1452
+
#define BLM_ACCUMULATOR_2 0x61298
1453
+
#define BLM_ACCUMULATOR_3 0x6129c
1454
+
#define BLM_ACCUMULATOR_4 0x612a0
1455
+
#define BLM_ACCUMULATOR_5 0x612a4
1456
+
1457
+
#define FPA0 0x06040
1458
+
#define FPA1 0x06044
1459
+
#define FPB0 0x06048
1460
+
#define FPB1 0x0604c
1461
+
# define FP_N_DIV_MASK 0x003f0000
1462
+
# define FP_N_IGD_DIV_MASK 0x00ff0000
1463
+
# define FP_N_DIV_SHIFT 16
1464
+
# define FP_M1_DIV_MASK 0x00003f00
1465
+
# define FP_M1_DIV_SHIFT 8
1466
+
# define FP_M2_DIV_MASK 0x0000003f
1467
+
# define FP_M2_IGD_DIV_MASK 0x000000ff
1468
+
# define FP_M2_DIV_SHIFT 0
1469
+
1470
+
#define PORT_HOTPLUG_EN 0x61110
1471
+
# define HDMIB_HOTPLUG_INT_EN (1 << 29)
1472
+
# define HDMIC_HOTPLUG_INT_EN (1 << 28)
1473
+
# define HDMID_HOTPLUG_INT_EN (1 << 27)
1474
+
# define SDVOB_HOTPLUG_INT_EN (1 << 26)
1475
+
# define SDVOC_HOTPLUG_INT_EN (1 << 25)
1476
+
# define TV_HOTPLUG_INT_EN (1 << 18)
1477
+
# define CRT_HOTPLUG_INT_EN (1 << 9)
1478
+
# define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1479
+
/* must use period 64 on GM45 according to docs */
1480
+
# define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1481
+
# define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1482
+
# define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1483
+
# define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1484
+
# define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1485
+
# define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1486
+
# define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1487
+
# define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1488
+
# define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1489
+
# define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1490
+
# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1491
+
# define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1492
+
# define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1493
+
# define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
1494
+
1495
+
#define PORT_HOTPLUG_STAT 0x61114
1496
+
# define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1497
+
# define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1498
+
# define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1499
+
# define CRT_HOTPLUG_INT_STATUS (1 << 11)
1500
+
# define TV_HOTPLUG_INT_STATUS (1 << 10)
1501
+
# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1502
+
# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1503
+
# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1504
+
# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1505
+
# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1506
+
# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1507
+
1508
+
#define SDVOB 0x61140
1509
+
#define SDVOC 0x61160
1510
+
#define SDVO_ENABLE (1 << 31)
1511
+
#define SDVO_PIPE_B_SELECT (1 << 30)
1512
+
#define SDVO_STALL_SELECT (1 << 29)
1513
+
#define SDVO_INTERRUPT_ENABLE (1 << 26)
1514
+
/**
1515
+
* 915G/GM SDVO pixel multiplier.
1516
+
*
1517
+
* Programmed value is multiplier - 1, up to 5x.
1518
+
*
1519
+
* \sa DPLL_MD_UDI_MULTIPLIER_MASK
1520
+
*/
1521
+
#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1522
+
#define SDVO_PORT_MULTIPLY_SHIFT 23
1523
+
#define SDVO_PHASE_SELECT_MASK (15 << 19)
1524
+
#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1525
+
#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1526
+
#define SDVOC_GANG_MODE (1 << 16)
1527
+
#define SDVO_ENCODING_SDVO (0x0 << 10)
1528
+
#define SDVO_ENCODING_HDMI (0x2 << 10)
1529
+
/** Requird for HDMI operation */
1530
+
#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1531
+
#define SDVO_BORDER_ENABLE (1 << 7)
1532
+
#define SDVO_AUDIO_ENABLE (1 << 6)
1533
+
/** New with 965, default is to be set */
1534
+
#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1535
+
/** New with 965, default is to be set */
1536
+
#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1537
+
/** 915/945 only, read-only bit */
1538
+
#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1539
+
#define SDVO_DETECTED (1 << 2)
1540
+
/* Bits to be preserved when writing */
1541
+
#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
1542
+
#define SDVOC_PRESERVE_MASK (1 << 17)
1543
+
1544
+
#define UDIB_SVB_SHB_CODES 0x61144
1545
+
#define UDIB_SHA_BLANK_CODES 0x61148
1546
+
#define UDIB_START_END_FILL_CODES 0x6114c
1547
+
1548
+
1549
+
#define SDVOUDI 0x61150
1550
+
1551
+
#define I830_HTOTAL_MASK 0xfff0000
1552
+
#define I830_HACTIVE_MASK 0x7ff
1553
+
1554
+
#define I830_HBLANKEND_MASK 0xfff0000
1555
+
#define I830_HBLANKSTART_MASK 0xfff
1556
+
1557
+
#define I830_HSYNCEND_MASK 0xfff0000
1558
+
#define I830_HSYNCSTART_MASK 0xfff
1559
+
1560
+
#define I830_VTOTAL_MASK 0xfff0000
1561
+
#define I830_VACTIVE_MASK 0x7ff
1562
+
1563
+
#define I830_VBLANKEND_MASK 0xfff0000
1564
+
#define I830_VBLANKSTART_MASK 0xfff
1565
+
1566
+
#define I830_VSYNCEND_MASK 0xfff0000
1567
+
#define I830_VSYNCSTART_MASK 0xfff
1568
+
1569
+
#define I830_PIPEA_HORZ_MASK 0x7ff0000
1570
+
#define I830_PIPEA_VERT_MASK 0x7ff
1571
+
1572
+
#define ADPA 0x61100
1573
+
#define ADPA_DAC_ENABLE (1<<31)
1574
+
#define ADPA_DAC_DISABLE 0
1575
+
#define ADPA_PIPE_SELECT_MASK (1<<30)
1576
+
#define ADPA_PIPE_A_SELECT 0
1577
+
#define ADPA_PIPE_B_SELECT (1<<30)
1578
+
#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1579
+
#define ADPA_SETS_HVPOLARITY 0
1580
+
#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1581
+
#define ADPA_VSYNC_CNTL_ENABLE 0
1582
+
#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1583
+
#define ADPA_HSYNC_CNTL_ENABLE 0
1584
+
#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1585
+
#define ADPA_VSYNC_ACTIVE_LOW 0
1586
+
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1587
+
#define ADPA_HSYNC_ACTIVE_LOW 0
1588
+
1589
+
#define PCH_DSP_CHICKEN1 0x42000
1590
+
#define PCH_DSP_CHICKEN2 0x42004
1591
+
#define PCH_DSP_CHICKEN3 0x4200c
1592
+
#define PCH_DSPCLK_GATE_D 0x42020
1593
+
#define PCH_DSPRAMCLK_GATE_D 0x42024
1594
+
#define PCH_3DCGDIS0 0x46020
1595
+
#define PCH_3DCGDIS1 0x46024
1596
+
#define PCH_3DRAMCGDIS0 0x46028
1597
+
#define SOUTH_DSPCLK_GATE_D 0xc2020
1598
+
1599
+
#define CPU_eDP_A 0x64000
1600
+
#define PCH_DP_B 0xe4100
1601
+
#define PCH_DP_C 0xe4200
1602
+
#define PCH_DP_D 0xe4300
1603
+
1604
+
#define DVOA 0x61120
1605
+
#define DVOB 0x61140
1606
+
#define DVOC 0x61160
1607
+
#define DVO_ENABLE (1 << 31)
1608
+
#define DVO_PIPE_B_SELECT (1 << 30)
1609
+
#define DVO_PIPE_STALL_UNUSED (0 << 28)
1610
+
#define DVO_PIPE_STALL (1 << 28)
1611
+
#define DVO_PIPE_STALL_TV (2 << 28)
1612
+
#define DVO_PIPE_STALL_MASK (3 << 28)
1613
+
#define DVO_USE_VGA_SYNC (1 << 15)
1614
+
#define DVO_DATA_ORDER_I740 (0 << 14)
1615
+
#define DVO_DATA_ORDER_FP (1 << 14)
1616
+
#define DVO_VSYNC_DISABLE (1 << 11)
1617
+
#define DVO_HSYNC_DISABLE (1 << 10)
1618
+
#define DVO_VSYNC_TRISTATE (1 << 9)
1619
+
#define DVO_HSYNC_TRISTATE (1 << 8)
1620
+
#define DVO_BORDER_ENABLE (1 << 7)
1621
+
#define DVO_DATA_ORDER_GBRG (1 << 6)
1622
+
#define DVO_DATA_ORDER_RGGB (0 << 6)
1623
+
#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1624
+
#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1625
+
#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1626
+
#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1627
+
#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1628
+
#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1629
+
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1630
+
#define DVO_PRESERVE_MASK (0x7<<24)
1631
+
1632
+
#define DVOA_SRCDIM 0x61124
1633
+
#define DVOB_SRCDIM 0x61144
1634
+
#define DVOC_SRCDIM 0x61164
1635
+
#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1636
+
#define DVO_SRCDIM_VERTICAL_SHIFT 0
1637
+
1638
+
/** @defgroup LVDS
1639
+
* @{
1640
+
*/
1641
+
/**
1642
+
* This register controls the LVDS output enable, pipe selection, and data
1643
+
* format selection.
1644
+
*
1645
+
* All of the clock/data pairs are force powered down by power sequencing.
1646
+
*/
1647
+
#define LVDS 0x61180
1648
+
/**
1649
+
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1650
+
* the DPLL semantics change when the LVDS is assigned to that pipe.
1651
+
*/
1652
+
# define LVDS_PORT_EN (1 << 31)
1653
+
/** Selects pipe B for LVDS data. Must be set on pre-965. */
1654
+
# define LVDS_PIPEB_SELECT (1 << 30)
1655
+
1656
+
/* on 965, dithering is enabled in this register, not PFIT_CONTROL */
1657
+
# define LVDS_DITHER_ENABLE (1 << 25)
1658
+
1659
+
/*
1660
+
* Selects between .0 and .1 formats:
1661
+
*
1662
+
* 0 = 1x18.0, 2x18.0, 1x24.0 or 2x24.0
1663
+
* 1 = 1x24.1 or 2x24.1
1664
+
*/
1665
+
# define LVDS_DATA_FORMAT_DOT_ONE (1 << 24)
1666
+
1667
+
/* Using LE instead of HS on second channel control signal */
1668
+
# define LVDS_LE_CONTROL_ENABLE (1 << 23)
1669
+
1670
+
/* Using LF instead of VS on second channel control signal */
1671
+
# define LVDS_LF_CONTROL_ENABLE (1 << 22)
1672
+
1673
+
/* invert vsync signal polarity */
1674
+
# define LVDS_VSYNC_POLARITY_INVERT (1 << 21)
1675
+
1676
+
/* invert hsync signal polarity */
1677
+
# define LVDS_HSYNC_POLARITY_INVERT (1 << 20)
1678
+
1679
+
/* invert display enable signal polarity */
1680
+
# define LVDS_DE_POLARITY_INVERT (1 << 19)
1681
+
1682
+
/*
1683
+
* Control signals for second channel, ignored in single channel modes
1684
+
*/
1685
+
1686
+
/* send DE, HS, VS on second channel */
1687
+
# define LVDS_SECOND_CHANNEL_DE_HS_VS (0 << 17)
1688
+
1689
+
# define LVDS_SECOND_CHANNEL_RESERVED (1 << 17)
1690
+
1691
+
/* Send zeros instead of DE, HS, VS on second channel */
1692
+
# define LVDS_SECOND_CHANNEL_ZEROS (2 << 17)
1693
+
1694
+
/* Set DE=0, HS=LE, VS=LF on second channel */
1695
+
# define LVDS_SECOND_CHANNEL_HS_VS (3 << 17)
1696
+
1697
+
/*
1698
+
* Send duplicate data for channel reserved bits, otherwise send zeros
1699
+
*/
1700
+
# define LVDS_CHANNEL_DUP_RESERVED (1 << 16)
1701
+
1702
+
/*
1703
+
* Enable border for unscaled (or aspect-scaled) display
1704
+
*/
1705
+
# define LVDS_BORDER_ENABLE (1 << 15)
1706
+
1707
+
/*
1708
+
* Tri-state the LVDS buffers when powered down, otherwise
1709
+
* they are set to 0V
1710
+
*/
1711
+
# define LVDS_POWER_DOWN_TRI_STATE (1 << 10)
1712
+
1713
+
/**
1714
+
* Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1715
+
* pixel.
1716
+
*/
1717
+
# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1718
+
# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1719
+
# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1720
+
/**
1721
+
* Controls the A3 data pair, which contains the additional LSBs for 24 bit
1722
+
* mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1723
+
* on.
1724
+
*/
1725
+
# define LVDS_A3_POWER_MASK (3 << 6)
1726
+
# define LVDS_A3_POWER_DOWN (0 << 6)
1727
+
# define LVDS_A3_POWER_UP (3 << 6)
1728
+
/**
1729
+
* Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1730
+
* is set.
1731
+
*/
1732
+
# define LVDS_CLKB_POWER_MASK (3 << 4)
1733
+
# define LVDS_CLKB_POWER_DOWN (0 << 4)
1734
+
# define LVDS_CLKB_POWER_UP (3 << 4)
1735
+
1736
+
/**
1737
+
* Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1738
+
* setting for whether we are in dual-channel mode. The B3 pair will
1739
+
* additionally only be powered up when LVDS_A3_POWER_UP is set.
1740
+
*/
1741
+
# define LVDS_B0B3_POWER_MASK (3 << 2)
1742
+
# define LVDS_B0B3_POWER_DOWN (0 << 2)
1743
+
# define LVDS_B0B3_POWER_UP (3 << 2)
1744
+
1745
+
/** @} */
1746
+
1747
+
#define DP_B 0x64100
1748
+
#define DPB_AUX_CH_CTL 0x64110
1749
+
#define DPB_AUX_CH_DATA1 0x64114
1750
+
#define DPB_AUX_CH_DATA2 0x64118
1751
+
#define DPB_AUX_CH_DATA3 0x6411c
1752
+
#define DPB_AUX_CH_DATA4 0x64120
1753
+
#define DPB_AUX_CH_DATA5 0x64124
1754
+
1755
+
#define DP_C 0x64200
1756
+
#define DPC_AUX_CH_CTL 0x64210
1757
+
#define DPC_AUX_CH_DATA1 0x64214
1758
+
#define DPC_AUX_CH_DATA2 0x64218
1759
+
#define DPC_AUX_CH_DATA3 0x6421c
1760
+
#define DPC_AUX_CH_DATA4 0x64220
1761
+
#define DPC_AUX_CH_DATA5 0x64224
1762
+
1763
+
#define DP_D 0x64300
1764
+
#define DPD_AUX_CH_CTL 0x64310
1765
+
#define DPD_AUX_CH_DATA1 0x64314
1766
+
#define DPD_AUX_CH_DATA2 0x64318
1767
+
#define DPD_AUX_CH_DATA3 0x6431c
1768
+
#define DPD_AUX_CH_DATA4 0x64320
1769
+
#define DPD_AUX_CH_DATA5 0x64324
1770
+
1771
+
/*
1772
+
* Two channel clock control. Turn this on if you need clkb for two channel mode
1773
+
* Overridden by global LVDS power sequencing
1774
+
*/
1775
+
1776
+
/* clkb off */
1777
+
# define LVDS_CLKB_POWER_DOWN (0 << 4)
1778
+
1779
+
/* powered up, but clkb forced to 0 */
1780
+
# define LVDS_CLKB_POWER_PARTIAL (1 << 4)
1781
+
1782
+
/* clock B running */
1783
+
# define LVDS_CLKB_POWER_UP (3 << 4)
1784
+
1785
+
/*
1786
+
* Two channel mode B0-B2 control. Sets state when power is on.
1787
+
* Set to POWER_DOWN in single channel mode, other settings enable
1788
+
* two channel mode. The CLKB power control controls whether that clock
1789
+
* is enabled during two channel mode.
1790
+
*
1791
+
*/
1792
+
/* Everything is off, including B3 and CLKB */
1793
+
# define LVDS_B_POWER_DOWN (0 << 2)
1794
+
1795
+
/* B0, B1, B2 and data lines forced to 0. timing is active */
1796
+
# define LVDS_B_POWER_PARTIAL (1 << 2)
1797
+
1798
+
/* data lines active (both timing and colour) */
1799
+
# define LVDS_B_POWER_UP (3 << 2)
1800
+
1801
+
/** @defgroup TV_CTL
1802
+
* @{
1803
+
*/
1804
+
#define TV_CTL 0x68000
1805
+
/** Enables the TV encoder */
1806
+
# define TV_ENC_ENABLE (1 << 31)
1807
+
/** Sources the TV encoder input from pipe B instead of A. */
1808
+
# define TV_ENC_PIPEB_SELECT (1 << 30)
1809
+
/** Outputs composite video (DAC A only) */
1810
+
# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1811
+
/** Outputs SVideo video (DAC B/C) */
1812
+
# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1813
+
/** Outputs Component video (DAC A/B/C) */
1814
+
# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1815
+
/** Outputs Composite and SVideo (DAC A/B/C) */
1816
+
# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1817
+
# define TV_TRILEVEL_SYNC (1 << 21)
1818
+
/** Enables slow sync generation (945GM only) */
1819
+
# define TV_SLOW_SYNC (1 << 20)
1820
+
/** Selects 4x oversampling for 480i and 576p */
1821
+
# define TV_OVERSAMPLE_4X (0 << 18)
1822
+
/** Selects 2x oversampling for 720p and 1080i */
1823
+
# define TV_OVERSAMPLE_2X (1 << 18)
1824
+
/** Selects no oversampling for 1080p */
1825
+
# define TV_OVERSAMPLE_NONE (2 << 18)
1826
+
/** Selects 8x oversampling */
1827
+
# define TV_OVERSAMPLE_8X (3 << 18)
1828
+
/** Selects progressive mode rather than interlaced */
1829
+
# define TV_PROGRESSIVE (1 << 17)
1830
+
/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1831
+
# define TV_PAL_BURST (1 << 16)
1832
+
/** Field for setting delay of Y compared to C */
1833
+
# define TV_YC_SKEW_MASK (7 << 12)
1834
+
/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1835
+
# define TV_ENC_SDP_FIX (1 << 11)
1836
+
/**
1837
+
* Enables a fix for the 915GM only.
1838
+
*
1839
+
* Not sure what it does.
1840
+
*/
1841
+
# define TV_ENC_C0_FIX (1 << 10)
1842
+
/** Bits that must be preserved by software */
1843
+
# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1844
+
# define TV_FUSE_STATE_MASK (3 << 4)
1845
+
/** Read-only state that reports all features enabled */
1846
+
# define TV_FUSE_STATE_ENABLED (0 << 4)
1847
+
/** Read-only state that reports that Macrovision is disabled in hardware*/
1848
+
# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1849
+
/** Read-only state that reports that TV-out is disabled in hardware. */
1850
+
# define TV_FUSE_STATE_DISABLED (2 << 4)
1851
+
/** Normal operation */
1852
+
# define TV_TEST_MODE_NORMAL (0 << 0)
1853
+
/** Encoder test pattern 1 - combo pattern */
1854
+
# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1855
+
/** Encoder test pattern 2 - full screen vertical 75% color bars */
1856
+
# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1857
+
/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1858
+
# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1859
+
/** Encoder test pattern 4 - random noise */
1860
+
# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1861
+
/** Encoder test pattern 5 - linear color ramps */
1862
+
# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1863
+
/**
1864
+
* This test mode forces the DACs to 50% of full output.
1865
+
*
1866
+
* This is used for load detection in combination with TVDAC_SENSE_MASK
1867
+
*/
1868
+
# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1869
+
# define TV_TEST_MODE_MASK (7 << 0)
1870
+
/** @} */
1871
+
1872
+
/** @defgroup TV_DAC
1873
+
* @{
1874
+
*/
1875
+
#define TV_DAC 0x68004
1876
+
/**
1877
+
* Reports that DAC state change logic has reported change (RO).
1878
+
*
1879
+
* This gets cleared when TV_DAC_STATE_EN is cleared
1880
+
*/
1881
+
# define TVDAC_STATE_CHG (1 << 31)
1882
+
# define TVDAC_SENSE_MASK (7 << 28)
1883
+
/** Reports that DAC A voltage is above the detect threshold */
1884
+
# define TVDAC_A_SENSE (1 << 30)
1885
+
/** Reports that DAC B voltage is above the detect threshold */
1886
+
# define TVDAC_B_SENSE (1 << 29)
1887
+
/** Reports that DAC C voltage is above the detect threshold */
1888
+
# define TVDAC_C_SENSE (1 << 28)
1889
+
/**
1890
+
* Enables DAC state detection logic, for load-based TV detection.
1891
+
*
1892
+
* The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1893
+
* to off, for load detection to work.
1894
+
*/
1895
+
# define TVDAC_STATE_CHG_EN (1 << 27)
1896
+
/** Sets the DAC A sense value to high */
1897
+
# define TVDAC_A_SENSE_CTL (1 << 26)
1898
+
/** Sets the DAC B sense value to high */
1899
+
# define TVDAC_B_SENSE_CTL (1 << 25)
1900
+
/** Sets the DAC C sense value to high */
1901
+
# define TVDAC_C_SENSE_CTL (1 << 24)
1902
+
/** Overrides the ENC_ENABLE and DAC voltage levels */
1903
+
# define DAC_CTL_OVERRIDE (1 << 7)
1904
+
/** Sets the slew rate. Must be preserved in software */
1905
+
# define ENC_TVDAC_SLEW_FAST (1 << 6)
1906
+
# define DAC_A_1_3_V (0 << 4)
1907
+
# define DAC_A_1_1_V (1 << 4)
1908
+
# define DAC_A_0_7_V (2 << 4)
1909
+
# define DAC_A_OFF (3 << 4)
1910
+
# define DAC_B_1_3_V (0 << 2)
1911
+
# define DAC_B_1_1_V (1 << 2)
1912
+
# define DAC_B_0_7_V (2 << 2)
1913
+
# define DAC_B_OFF (3 << 2)
1914
+
# define DAC_C_1_3_V (0 << 0)
1915
+
# define DAC_C_1_1_V (1 << 0)
1916
+
# define DAC_C_0_7_V (2 << 0)
1917
+
# define DAC_C_OFF (3 << 0)
1918
+
/** @} */
1919
+
1920
+
/**
1921
+
* CSC coefficients are stored in a floating point format with 9 bits of
1922
+
* mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1923
+
* where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1924
+
* -1 (0x3) being the only legal negative value.
1925
+
*/
1926
+
#define TV_CSC_Y 0x68010
1927
+
# define TV_RY_MASK 0x07ff0000
1928
+
# define TV_RY_SHIFT 16
1929
+
# define TV_GY_MASK 0x00000fff
1930
+
# define TV_GY_SHIFT 0
1931
+
1932
+
#define TV_CSC_Y2 0x68014
1933
+
# define TV_BY_MASK 0x07ff0000
1934
+
# define TV_BY_SHIFT 16
1935
+
/**
1936
+
* Y attenuation for component video.
1937
+
*
1938
+
* Stored in 1.9 fixed point.
1939
+
*/
1940
+
# define TV_AY_MASK 0x000003ff
1941
+
# define TV_AY_SHIFT 0
1942
+
1943
+
#define TV_CSC_U 0x68018
1944
+
# define TV_RU_MASK 0x07ff0000
1945
+
# define TV_RU_SHIFT 16
1946
+
# define TV_GU_MASK 0x000007ff
1947
+
# define TV_GU_SHIFT 0
1948
+
1949
+
#define TV_CSC_U2 0x6801c
1950
+
# define TV_BU_MASK 0x07ff0000
1951
+
# define TV_BU_SHIFT 16
1952
+
/**
1953
+
* U attenuation for component video.
1954
+
*
1955
+
* Stored in 1.9 fixed point.
1956
+
*/
1957
+
# define TV_AU_MASK 0x000003ff
1958
+
# define TV_AU_SHIFT 0
1959
+
1960
+
#define TV_CSC_V 0x68020
1961
+
# define TV_RV_MASK 0x0fff0000
1962
+
# define TV_RV_SHIFT 16
1963
+
# define TV_GV_MASK 0x000007ff
1964
+
# define TV_GV_SHIFT 0
1965
+
1966
+
#define TV_CSC_V2 0x68024
1967
+
# define TV_BV_MASK 0x07ff0000
1968
+
# define TV_BV_SHIFT 16
1969
+
/**
1970
+
* V attenuation for component video.
1971
+
*
1972
+
* Stored in 1.9 fixed point.
1973
+
*/
1974
+
# define TV_AV_MASK 0x000007ff
1975
+
# define TV_AV_SHIFT 0
1976
+
1977
+
/** @defgroup TV_CSC_KNOBS
1978
+
* @{
1979
+
*/
1980
+
#define TV_CLR_KNOBS 0x68028
1981
+
/** 2s-complement brightness adjustment */
1982
+
# define TV_BRIGHTNESS_MASK 0xff000000
1983
+
# define TV_BRIGHTNESS_SHIFT 24
1984
+
/** Contrast adjustment, as a 2.6 unsigned floating point number */
1985
+
# define TV_CONTRAST_MASK 0x00ff0000
1986
+
# define TV_CONTRAST_SHIFT 16
1987
+
/** Saturation adjustment, as a 2.6 unsigned floating point number */
1988
+
# define TV_SATURATION_MASK 0x0000ff00
1989
+
# define TV_SATURATION_SHIFT 8
1990
+
/** Hue adjustment, as an integer phase angle in degrees */
1991
+
# define TV_HUE_MASK 0x000000ff
1992
+
# define TV_HUE_SHIFT 0
1993
+
/** @} */
1994
+
1995
+
/** @defgroup TV_CLR_LEVEL
1996
+
* @{
1997
+
*/
1998
+
#define TV_CLR_LEVEL 0x6802c
1999
+
/** Controls the DAC level for black */
2000
+
# define TV_BLACK_LEVEL_MASK 0x01ff0000
2001
+
# define TV_BLACK_LEVEL_SHIFT 16
2002
+
/** Controls the DAC level for blanking */
2003
+
# define TV_BLANK_LEVEL_MASK 0x000001ff
2004
+
# define TV_BLANK_LEVEL_SHIFT 0
2005
+
/* @} */
2006
+
2007
+
/** @defgroup TV_H_CTL_1
2008
+
* @{
2009
+
*/
2010
+
#define TV_H_CTL_1 0x68030
2011
+
/** Number of pixels in the hsync. */
2012
+
# define TV_HSYNC_END_MASK 0x1fff0000
2013
+
# define TV_HSYNC_END_SHIFT 16
2014
+
/** Total number of pixels minus one in the line (display and blanking). */
2015
+
# define TV_HTOTAL_MASK 0x00001fff
2016
+
# define TV_HTOTAL_SHIFT 0
2017
+
/** @} */
2018
+
2019
+
/** @defgroup TV_H_CTL_2
2020
+
* @{
2021
+
*/
2022
+
#define TV_H_CTL_2 0x68034
2023
+
/** Enables the colorburst (needed for non-component color) */
2024
+
# define TV_BURST_ENA (1 << 31)
2025
+
/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2026
+
# define TV_HBURST_START_SHIFT 16
2027
+
# define TV_HBURST_START_MASK 0x1fff0000
2028
+
/** Length of the colorburst */
2029
+
# define TV_HBURST_LEN_SHIFT 0
2030
+
# define TV_HBURST_LEN_MASK 0x0001fff
2031
+
/** @} */
2032
+
2033
+
/** @defgroup TV_H_CTL_3
2034
+
* @{
2035
+
*/
2036
+
#define TV_H_CTL_3 0x68038
2037
+
/** End of hblank, measured in pixels minus one from start of hsync */
2038
+
# define TV_HBLANK_END_SHIFT 16
2039
+
# define TV_HBLANK_END_MASK 0x1fff0000
2040
+
/** Start of hblank, measured in pixels minus one from start of hsync */
2041
+
# define TV_HBLANK_START_SHIFT 0
2042
+
# define TV_HBLANK_START_MASK 0x0001fff
2043
+
/** @} */
2044
+
2045
+
/** @defgroup TV_V_CTL_1
2046
+
* @{
2047
+
*/
2048
+
#define TV_V_CTL_1 0x6803c
2049
+
/** XXX */
2050
+
# define TV_NBR_END_SHIFT 16
2051
+
# define TV_NBR_END_MASK 0x07ff0000
2052
+
/** XXX */
2053
+
# define TV_VI_END_F1_SHIFT 8
2054
+
# define TV_VI_END_F1_MASK 0x00003f00
2055
+
/** XXX */
2056
+
# define TV_VI_END_F2_SHIFT 0
2057
+
# define TV_VI_END_F2_MASK 0x0000003f
2058
+
/** @} */
2059
+
2060
+
/** @defgroup TV_V_CTL_2
2061
+
* @{
2062
+
*/
2063
+
#define TV_V_CTL_2 0x68040
2064
+
/** Length of vsync, in half lines */
2065
+
# define TV_VSYNC_LEN_MASK 0x07ff0000
2066
+
# define TV_VSYNC_LEN_SHIFT 16
2067
+
/** Offset of the start of vsync in field 1, measured in one less than the
2068
+
* number of half lines.
2069
+
*/
2070
+
# define TV_VSYNC_START_F1_MASK 0x00007f00
2071
+
# define TV_VSYNC_START_F1_SHIFT 8
2072
+
/**
2073
+
* Offset of the start of vsync in field 2, measured in one less than the
2074
+
* number of half lines.
2075
+
*/
2076
+
# define TV_VSYNC_START_F2_MASK 0x0000007f
2077
+
# define TV_VSYNC_START_F2_SHIFT 0
2078
+
/** @} */
2079
+
2080
+
/** @defgroup TV_V_CTL_3
2081
+
* @{
2082
+
*/
2083
+
#define TV_V_CTL_3 0x68044
2084
+
/** Enables generation of the equalization signal */
2085
+
# define TV_EQUAL_ENA (1 << 31)
2086
+
/** Length of vsync, in half lines */
2087
+
# define TV_VEQ_LEN_MASK 0x007f0000
2088
+
# define TV_VEQ_LEN_SHIFT 16
2089
+
/** Offset of the start of equalization in field 1, measured in one less than
2090
+
* the number of half lines.
2091
+
*/
2092
+
# define TV_VEQ_START_F1_MASK 0x0007f00
2093
+
# define TV_VEQ_START_F1_SHIFT 8
2094
+
/**
2095
+
* Offset of the start of equalization in field 2, measured in one less than
2096
+
* the number of half lines.
2097
+
*/
2098
+
# define TV_VEQ_START_F2_MASK 0x000007f
2099
+
# define TV_VEQ_START_F2_SHIFT 0
2100
+
/** @} */
2101
+
2102
+
/** @defgroup TV_V_CTL_4
2103
+
* @{
2104
+
*/
2105
+
#define TV_V_CTL_4 0x68048
2106
+
/**
2107
+
* Offset to start of vertical colorburst, measured in one less than the
2108
+
* number of lines from vertical start.
2109
+
*/
2110
+
# define TV_VBURST_START_F1_MASK 0x003f0000
2111
+
# define TV_VBURST_START_F1_SHIFT 16
2112
+
/**
2113
+
* Offset to the end of vertical colorburst, measured in one less than the
2114
+
* number of lines from the start of NBR.
2115
+
*/
2116
+
# define TV_VBURST_END_F1_MASK 0x000000ff
2117
+
# define TV_VBURST_END_F1_SHIFT 0
2118
+
/** @} */
2119
+
2120
+
/** @defgroup TV_V_CTL_5
2121
+
* @{
2122
+
*/
2123
+
#define TV_V_CTL_5 0x6804c
2124
+
/**
2125
+
* Offset to start of vertical colorburst, measured in one less than the
2126
+
* number of lines from vertical start.
2127
+
*/
2128
+
# define TV_VBURST_START_F2_MASK 0x003f0000
2129
+
# define TV_VBURST_START_F2_SHIFT 16
2130
+
/**
2131
+
* Offset to the end of vertical colorburst, measured in one less than the
2132
+
* number of lines from the start of NBR.
2133
+
*/
2134
+
# define TV_VBURST_END_F2_MASK 0x000000ff
2135
+
# define TV_VBURST_END_F2_SHIFT 0
2136
+
/** @} */
2137
+
2138
+
/** @defgroup TV_V_CTL_6
2139
+
* @{
2140
+
*/
2141
+
#define TV_V_CTL_6 0x68050
2142
+
/**
2143
+
* Offset to start of vertical colorburst, measured in one less than the
2144
+
* number of lines from vertical start.
2145
+
*/
2146
+
# define TV_VBURST_START_F3_MASK 0x003f0000
2147
+
# define TV_VBURST_START_F3_SHIFT 16
2148
+
/**
2149
+
* Offset to the end of vertical colorburst, measured in one less than the
2150
+
* number of lines from the start of NBR.
2151
+
*/
2152
+
# define TV_VBURST_END_F3_MASK 0x000000ff
2153
+
# define TV_VBURST_END_F3_SHIFT 0
2154
+
/** @} */
2155
+
2156
+
/** @defgroup TV_V_CTL_7
2157
+
* @{
2158
+
*/
2159
+
#define TV_V_CTL_7 0x68054
2160
+
/**
2161
+
* Offset to start of vertical colorburst, measured in one less than the
2162
+
* number of lines from vertical start.
2163
+
*/
2164
+
# define TV_VBURST_START_F4_MASK 0x003f0000
2165
+
# define TV_VBURST_START_F4_SHIFT 16
2166
+
/**
2167
+
* Offset to the end of vertical colorburst, measured in one less than the
2168
+
* number of lines from the start of NBR.
2169
+
*/
2170
+
# define TV_VBURST_END_F4_MASK 0x000000ff
2171
+
# define TV_VBURST_END_F4_SHIFT 0
2172
+
/** @} */
2173
+
2174
+
/** @defgroup TV_SC_CTL_1
2175
+
* @{
2176
+
*/
2177
+
#define TV_SC_CTL_1 0x68060
2178
+
/** Turns on the first subcarrier phase generation DDA */
2179
+
# define TV_SC_DDA1_EN (1 << 31)
2180
+
/** Turns on the first subcarrier phase generation DDA */
2181
+
# define TV_SC_DDA2_EN (1 << 30)
2182
+
/** Turns on the first subcarrier phase generation DDA */
2183
+
# define TV_SC_DDA3_EN (1 << 29)
2184
+
/** Sets the subcarrier DDA to reset frequency every other field */
2185
+
# define TV_SC_RESET_EVERY_2 (0 << 24)
2186
+
/** Sets the subcarrier DDA to reset frequency every fourth field */
2187
+
# define TV_SC_RESET_EVERY_4 (1 << 24)
2188
+
/** Sets the subcarrier DDA to reset frequency every eighth field */
2189
+
# define TV_SC_RESET_EVERY_8 (2 << 24)
2190
+
/** Sets the subcarrier DDA to never reset the frequency */
2191
+
# define TV_SC_RESET_NEVER (3 << 24)
2192
+
/** Sets the peak amplitude of the colorburst.*/
2193
+
# define TV_BURST_LEVEL_MASK 0x00ff0000
2194
+
# define TV_BURST_LEVEL_SHIFT 16
2195
+
/** Sets the increment of the first subcarrier phase generation DDA */
2196
+
# define TV_SCDDA1_INC_MASK 0x00000fff
2197
+
# define TV_SCDDA1_INC_SHIFT 0
2198
+
/** @} */
2199
+
2200
+
/** @defgroup TV_SC_CTL_2
2201
+
* @{
2202
+
*/
2203
+
#define TV_SC_CTL_2 0x68064
2204
+
/** Sets the rollover for the second subcarrier phase generation DDA */
2205
+
# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2206
+
# define TV_SCDDA2_SIZE_SHIFT 16
2207
+
/** Sets the increent of the second subcarrier phase generation DDA */
2208
+
# define TV_SCDDA2_INC_MASK 0x00007fff
2209
+
# define TV_SCDDA2_INC_SHIFT 0
2210
+
/** @} */
2211
+
2212
+
/** @defgroup TV_SC_CTL_3
2213
+
* @{
2214
+
*/
2215
+
#define TV_SC_CTL_3 0x68068
2216
+
/** Sets the rollover for the third subcarrier phase generation DDA */
2217
+
# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2218
+
# define TV_SCDDA3_SIZE_SHIFT 16
2219
+
/** Sets the increent of the third subcarrier phase generation DDA */
2220
+
# define TV_SCDDA3_INC_MASK 0x00007fff
2221
+
# define TV_SCDDA3_INC_SHIFT 0
2222
+
/** @} */
2223
+
2224
+
/** @defgroup TV_WIN_POS
2225
+
* @{
2226
+
*/
2227
+
#define TV_WIN_POS 0x68070
2228
+
/** X coordinate of the display from the start of horizontal active */
2229
+
# define TV_XPOS_MASK 0x1fff0000
2230
+
# define TV_XPOS_SHIFT 16
2231
+
/** Y coordinate of the display from the start of vertical active (NBR) */
2232
+
# define TV_YPOS_MASK 0x00000fff
2233
+
# define TV_YPOS_SHIFT 0
2234
+
/** @} */
2235
+
2236
+
/** @defgroup TV_WIN_SIZE
2237
+
* @{
2238
+
*/
2239
+
#define TV_WIN_SIZE 0x68074
2240
+
/** Horizontal size of the display window, measured in pixels*/
2241
+
# define TV_XSIZE_MASK 0x1fff0000
2242
+
# define TV_XSIZE_SHIFT 16
2243
+
/**
2244
+
* Vertical size of the display window, measured in pixels.
2245
+
*
2246
+
* Must be even for interlaced modes.
2247
+
*/
2248
+
# define TV_YSIZE_MASK 0x00000fff
2249
+
# define TV_YSIZE_SHIFT 0
2250
+
/** @} */
2251
+
2252
+
/** @defgroup TV_FILTER_CTL_1
2253
+
* @{
2254
+
*/
2255
+
#define TV_FILTER_CTL_1 0x68080
2256
+
/**
2257
+
* Enables automatic scaling calculation.
2258
+
*
2259
+
* If set, the rest of the registers are ignored, and the calculated values can
2260
+
* be read back from the register.
2261
+
*/
2262
+
# define TV_AUTO_SCALE (1 << 31)
2263
+
/**
2264
+
* Disables the vertical filter.
2265
+
*
2266
+
* This is required on modes more than 1024 pixels wide */
2267
+
# define TV_V_FILTER_BYPASS (1 << 29)
2268
+
/** Enables adaptive vertical filtering */
2269
+
# define TV_VADAPT (1 << 28)
2270
+
# define TV_VADAPT_MODE_MASK (3 << 26)
2271
+
/** Selects the least adaptive vertical filtering mode */
2272
+
# define TV_VADAPT_MODE_LEAST (0 << 26)
2273
+
/** Selects the moderately adaptive vertical filtering mode */
2274
+
# define TV_VADAPT_MODE_MODERATE (1 << 26)
2275
+
/** Selects the most adaptive vertical filtering mode */
2276
+
# define TV_VADAPT_MODE_MOST (3 << 26)
2277
+
/**
2278
+
* Sets the horizontal scaling factor.
2279
+
*
2280
+
* This should be the fractional part of the horizontal scaling factor divided
2281
+
* by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2282
+
*
2283
+
* (src width - 1) / ((oversample * dest width) - 1)
2284
+
*/
2285
+
# define TV_HSCALE_FRAC_MASK 0x00003fff
2286
+
# define TV_HSCALE_FRAC_SHIFT 0
2287
+
/** @} */
2288
+
2289
+
/** @defgroup TV_FILTER_CTL_2
2290
+
* @{
2291
+
*/
2292
+
#define TV_FILTER_CTL_2 0x68084
2293
+
/**
2294
+
* Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2295
+
*
2296
+
* TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2297
+
*/
2298
+
# define TV_VSCALE_INT_MASK 0x00038000
2299
+
# define TV_VSCALE_INT_SHIFT 15
2300
+
/**
2301
+
* Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2302
+
*
2303
+
* \sa TV_VSCALE_INT_MASK
2304
+
*/
2305
+
# define TV_VSCALE_FRAC_MASK 0x00007fff
2306
+
# define TV_VSCALE_FRAC_SHIFT 0
2307
+
/** @} */
2308
+
2309
+
/** @defgroup TV_FILTER_CTL_3
2310
+
* @{
2311
+
*/
2312
+
#define TV_FILTER_CTL_3 0x68088
2313
+
/**
2314
+
* Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2315
+
*
2316
+
* TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2317
+
*
2318
+
* For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2319
+
*/
2320
+
# define TV_VSCALE_IP_INT_MASK 0x00038000
2321
+
# define TV_VSCALE_IP_INT_SHIFT 15
2322
+
/**
2323
+
* Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2324
+
*
2325
+
* For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2326
+
*
2327
+
* \sa TV_VSCALE_IP_INT_MASK
2328
+
*/
2329
+
# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2330
+
# define TV_VSCALE_IP_FRAC_SHIFT 0
2331
+
/** @} */
2332
+
2333
+
/** @defgroup TV_CC_CONTROL
2334
+
* @{
2335
+
*/
2336
+
#define TV_CC_CONTROL 0x68090
2337
+
# define TV_CC_ENABLE (1 << 31)
2338
+
/**
2339
+
* Specifies which field to send the CC data in.
2340
+
*
2341
+
* CC data is usually sent in field 0.
2342
+
*/
2343
+
# define TV_CC_FID_MASK (1 << 27)
2344
+
# define TV_CC_FID_SHIFT 27
2345
+
/** Sets the horizontal position of the CC data. Usually 135. */
2346
+
# define TV_CC_HOFF_MASK 0x03ff0000
2347
+
# define TV_CC_HOFF_SHIFT 16
2348
+
/** Sets the vertical position of the CC data. Usually 21 */
2349
+
# define TV_CC_LINE_MASK 0x0000003f
2350
+
# define TV_CC_LINE_SHIFT 0
2351
+
/** @} */
2352
+
2353
+
/** @defgroup TV_CC_DATA
2354
+
* @{
2355
+
*/
2356
+
#define TV_CC_DATA 0x68094
2357
+
# define TV_CC_RDY (1 << 31)
2358
+
/** Second word of CC data to be transmitted. */
2359
+
# define TV_CC_DATA_2_MASK 0x007f0000
2360
+
# define TV_CC_DATA_2_SHIFT 16
2361
+
/** First word of CC data to be transmitted. */
2362
+
# define TV_CC_DATA_1_MASK 0x0000007f
2363
+
# define TV_CC_DATA_1_SHIFT 0
2364
+
/** @}
2365
+
*/
2366
+
2367
+
/** @{ */
2368
+
#define TV_H_LUMA_0 0x68100
2369
+
#define TV_H_LUMA_59 0x681ec
2370
+
#define TV_H_CHROMA_0 0x68200
2371
+
#define TV_H_CHROMA_59 0x682ec
2372
+
#define TV_V_LUMA_0 0x68300
2373
+
#define TV_V_LUMA_42 0x683a8
2374
+
#define TV_V_CHROMA_0 0x68400
2375
+
#define TV_V_CHROMA_42 0x684a8
2376
+
/** @} */
2377
+
2378
+
#define PIPEA_DSL 0x70000
2379
+
2380
+
#define PIPEACONF 0x70008
2381
+
#define PIPEACONF_ENABLE (1<<31)
2382
+
#define PIPEACONF_DISABLE 0
2383
+
#define PIPEACONF_DOUBLE_WIDE (1<<30)
2384
+
#define I965_PIPECONF_ACTIVE (1<<30)
2385
+
#define PIPEACONF_SINGLE_WIDE 0
2386
+
#define PIPEACONF_PIPE_UNLOCKED 0
2387
+
#define PIPEACONF_PIPE_LOCKED (1<<25)
2388
+
#define PIPEACONF_PALETTE 0
2389
+
#define PIPEACONF_GAMMA (1<<24)
2390
+
#define PIPECONF_FORCE_BORDER (1<<25)
2391
+
#define PIPECONF_PROGRESSIVE (0 << 21)
2392
+
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2393
+
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2394
+
/* ironlake: gamma */
2395
+
#define PIPECONF_PALETTE_8BIT (0<<24)
2396
+
#define PIPECONF_PALETTE_10BIT (1<<24)
2397
+
#define PIPECONF_PALETTE_12BIT (2<<24)
2398
+
#define PIPECONF_FORCE_BORDER (1<<25)
2399
+
#define PIPECONF_PROGRESSIVE (0 << 21)
2400
+
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2401
+
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2402
+
/* ironlake */
2403
+
#define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */
2404
+
#define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16)
2405
+
#define PIPECONF_NO_ROTATION (0<<14)
2406
+
#define PIPECONF_FULL_COLOR_RANGE (0<<13)
2407
+
#define PIPECONF_CE_COLOR_RANGE (1<<13)
2408
+
#define PIPECONF_COLOR_SPACE_RGB (0<<11)
2409
+
#define PIPECONF_COLOR_SPACE_YUV601 (1<<11)
2410
+
#define PIPECONF_COLOR_SPACE_YUV709 (2<<11)
2411
+
#define PIPECONF_CONNECT_DEFAULT (0<<9)
2412
+
#define PIPECONF_8BPP (0<<5)
2413
+
#define PIPECONF_10BPP (1<<5)
2414
+
#define PIPECONF_6BPP (2<<5)
2415
+
#define PIPECONF_12BPP (3<<5)
2416
+
#define PIPECONF_ENABLE_DITHER (1<<4)
2417
+
#define PIPECONF_DITHER_SPATIAL (0<<2)
2418
+
#define PIPECONF_DITHER_ST1 (1<<2)
2419
+
#define PIPECONF_DITHER_ST2 (2<<2)
2420
+
#define PIPECONF_DITHER_TEMPORAL (3<<2)
2421
+
2422
+
#define PIPEAGCMAXRED 0x70010
2423
+
#define PIPEAGCMAXGREEN 0x70014
2424
+
#define PIPEAGCMAXBLUE 0x70018
2425
+
#define PIPEASTAT 0x70024
2426
+
# define FIFO_UNDERRUN (1 << 31)
2427
+
# define CRC_ERROR_ENABLE (1 << 29)
2428
+
# define CRC_DONE_ENABLE (1 << 28)
2429
+
# define GMBUS_EVENT_ENABLE (1 << 27)
2430
+
# define VSYNC_INT_ENABLE (1 << 25)
2431
+
# define DLINE_COMPARE_ENABLE (1 << 24)
2432
+
# define DPST_EVENT_ENABLE (1 << 23)
2433
+
# define LBLC_EVENT_ENABLE (1 << 22)
2434
+
# define OFIELD_INT_ENABLE (1 << 21)
2435
+
# define EFIELD_INT_ENABLE (1 << 20)
2436
+
# define SVBLANK_INT_ENABLE (1 << 18)
2437
+
# define VBLANK_INT_ENABLE (1 << 17)
2438
+
# define OREG_UPDATE_ENABLE (1 << 16)
2439
+
# define CRC_ERROR_INT_STATUS (1 << 13)
2440
+
# define CRC_DONE_INT_STATUS (1 << 12)
2441
+
# define GMBUS_INT_STATUS (1 << 11)
2442
+
# define VSYNC_INT_STATUS (1 << 9)
2443
+
# define DLINE_COMPARE_STATUS (1 << 8)
2444
+
# define DPST_EVENT_STATUS (1 << 7)
2445
+
# define LBLC_EVENT_STATUS (1 << 6)
2446
+
# define OFIELD_INT_STATUS (1 << 5)
2447
+
# define EFIELD_INT_STATUS (1 << 4)
2448
+
# define SVBLANK_INT_STATUS (1 << 2)
2449
+
# define VBLANK_INT_STATUS (1 << 1)
2450
+
# define OREG_UPDATE_STATUS (1 << 0)
2451
+
2452
+
2453
+
#define DSPARB 0x70030
2454
+
#define DSPARB_CSTART_SHIFT 7
2455
+
#define DSPARB_BSTART_SHIFT 0
2456
+
#define DSPARB_BEND_SHIFT 9 /* on 855 */
2457
+
#define DSPARB_AEND_SHIFT 0
2458
+
#define DSPFW1 0x70034
2459
+
#define DSPFW2 0x70038
2460
+
#define DSPFW3 0x7003c
2461
+
/*
2462
+
* The two pipe frame counter registers are not synchronized, so
2463
+
* reading a stable value is somewhat tricky. The following code
2464
+
* should work:
2465
+
*
2466
+
* do {
2467
+
* high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT;
2468
+
* low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> PIPE_FRAME_LOW_SHIFT);
2469
+
* high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> PIPE_FRAME_HIGH_SHIFT);
2470
+
* } while (high1 != high2);
2471
+
* frame = (high1 << 8) | low1;
2472
+
*/
2473
+
#define PIPEAFRAMEHIGH 0x70040
2474
+
#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2475
+
#define PIPE_FRAME_HIGH_SHIFT 0
2476
+
#define PIPEAFRAMEPIXEL 0x70044
2477
+
#define PIPE_FRAME_LOW_MASK 0xff000000
2478
+
#define PIPE_FRAME_LOW_SHIFT 24
2479
+
/*
2480
+
* Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
2481
+
* and is 24 bits wide.
2482
+
*/
2483
+
#define PIPE_PIXEL_MASK 0x00ffffff
2484
+
#define PIPE_PIXEL_SHIFT 0
2485
+
2486
+
/*
2487
+
* Computing GMCH M and N values.
2488
+
*
2489
+
* GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2490
+
*
2491
+
* ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2492
+
*
2493
+
* The GMCH value is used internally
2494
+
*/
2495
+
#define PIPEA_GMCH_DATA_M 0x70050
2496
+
2497
+
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2498
+
#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2499
+
#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2500
+
2501
+
#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2502
+
2503
+
#define PIPEA_GMCH_DATA_N 0x70054
2504
+
#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2505
+
2506
+
/*
2507
+
* Computing Link M and N values.
2508
+
*
2509
+
* Link M / N = pixel_clock / ls_clk
2510
+
*
2511
+
* (the DP spec calls pixel_clock the 'strm_clk')
2512
+
*
2513
+
* The Link value is transmitted in the Main Stream
2514
+
* Attributes and VB-ID.
2515
+
*/
2516
+
2517
+
#define PIPEA_DP_LINK_M 0x70060
2518
+
#define PIPEA_DP_LINK_M_MASK (0xffffff)
2519
+
2520
+
#define PIPEA_DP_LINK_N 0x70064
2521
+
#define PIPEA_DP_LINK_N_MASK (0xffffff)
2522
+
2523
+
#define PIPEB_DSL 0x71000
2524
+
2525
+
#define PIPEBCONF 0x71008
2526
+
2527
+
#define PIPEBGCMAXRED 0x71010
2528
+
#define PIPEBGCMAXGREEN 0x71014
2529
+
#define PIPEBGCMAXBLUE 0x71018
2530
+
#define PIPEBSTAT 0x71024
2531
+
#define PIPEBFRAMEHIGH 0x71040
2532
+
#define PIPEBFRAMEPIXEL 0x71044
2533
+
2534
+
#define PIPEB_GMCH_DATA_M 0x71050
2535
+
#define PIPEB_GMCH_DATA_N 0x71054
2536
+
#define PIPEB_DP_LINK_M 0x71060
2537
+
#define PIPEB_DP_LINK_N 0x71064
2538
+
2539
+
#define PIPECCONF 0x72008
2540
+
2541
+
#define PIPECGCMAXRED 0x72010
2542
+
#define PIPECGCMAXGREEN 0x72014
2543
+
#define PIPECGCMAXBLUE 0x72018
2544
+
#define PIPECSTAT 0x72024
2545
+
#define PIPECFRAMEHIGH 0x72040
2546
+
#define PIPECFRAMEPIXEL 0x72044
2547
+
2548
+
#define PIPEC_GMCH_DATA_M 0x72050
2549
+
#define PIPEC_GMCH_DATA_N 0x72054
2550
+
#define PIPEC_DP_LINK_M 0x72060
2551
+
#define PIPEC_DP_LINK_N 0x72064
2552
+
2553
+
#define PIPEEDPCONF 0x7F008
2554
+
2555
+
#define DSPACNTR 0x70180
2556
+
#define DSPBCNTR 0x71180
2557
+
#define DSPCCNTR 0x72180
2558
+
#define DISPLAY_PLANE_ENABLE (1<<31)
2559
+
#define DISPLAY_PLANE_DISABLE 0
2560
+
#define DISPLAY_PLANE_TILED (1<<10)
2561
+
#define DISPPLANE_GAMMA_ENABLE (1<<30)
2562
+
#define DISPPLANE_GAMMA_DISABLE 0
2563
+
#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2564
+
#define DISPPLANE_8BPP (0x2<<26)
2565
+
#define DISPPLANE_15_16BPP (0x4<<26)
2566
+
#define DISPPLANE_16BPP (0x5<<26)
2567
+
#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2568
+
#define DISPPLANE_32BPP (0x7<<26)
2569
+
#define DISPPLANE_STEREO_ENABLE (1<<25)
2570
+
#define DISPPLANE_STEREO_DISABLE 0
2571
+
#define DISPPLANE_SEL_PIPE_MASK (1<<24)
2572
+
#define DISPPLANE_SEL_PIPE_A 0
2573
+
#define DISPPLANE_SEL_PIPE_B (1<<24)
2574
+
#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2575
+
#define DISPPLANE_SRC_KEY_DISABLE 0
2576
+
#define DISPPLANE_LINE_DOUBLE (1<<20)
2577
+
#define DISPPLANE_NO_LINE_DOUBLE 0
2578
+
#define DISPPLANE_STEREO_POLARITY_FIRST 0
2579
+
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2580
+
/* plane B only */
2581
+
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2582
+
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2583
+
#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
2584
+
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2585
+
2586
+
#define DSPABASE 0x70184
2587
+
#define DSPASTRIDE 0x70188
2588
+
2589
+
#define DSPBBASE 0x71184
2590
+
#define DSPBADDR DSPBBASE
2591
+
#define DSPBSTRIDE 0x71188
2592
+
2593
+
#define DSPCBASE 0x72184
2594
+
#define DSPCADDR DSPCBASE
2595
+
#define DSPCSTRIDE 0x72188
2596
+
2597
+
#define DSPAKEYVAL 0x70194
2598
+
#define DSPAKEYMASK 0x70198
2599
+
2600
+
#define DSPAPOS 0x7018C /* reserved */
2601
+
#define DSPASIZE 0x70190
2602
+
#define DSPBPOS 0x7118C
2603
+
#define DSPBSIZE 0x71190
2604
+
2605
+
#define DSPASURF 0x7019C
2606
+
#define DSPATILEOFF 0x701A4
2607
+
2608
+
#define DSPBSURF 0x7119C
2609
+
#define DSPBTILEOFF 0x711A4
2610
+
2611
+
#define DSPCSURF 0x7219C
2612
+
#define DSPCTILEOFF 0x721A4
2613
+
2614
+
#define VGACNTRL 0x71400
2615
+
# define VGA_DISP_DISABLE (1 << 31)
2616
+
# define VGA_2X_MODE (1 << 30)
2617
+
# define VGA_PIPE_B_SELECT (1 << 29)
2618
+
2619
+
/* Various masks for reserved bits, etc. */
2620
+
#define I830_FWATER1_MASK (~((1<<11)|(1<<10)|(1<<9)| \
2621
+
(1<<8)|(1<<26)|(1<<25)|(1<<24)|(1<<5)|(1<<4)|(1<<3)| \
2622
+
(1<<2)|(1<<1)|1|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)))
2623
+
#define I830_FWATER2_MASK ~(0)
2624
+
2625
+
#define DV0A_RESERVED ((1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1)
2626
+
#define DV0B_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<16)|(1<<5)|(1<<1)|1)
2627
+
#define VGA0_N_DIVISOR_MASK ((1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2628
+
#define VGA0_M1_DIVISOR_MASK ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
2629
+
#define VGA0_M2_DIVISOR_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2630
+
#define VGA0_M1M2N_RESERVED ~(VGA0_N_DIVISOR_MASK|VGA0_M1_DIVISOR_MASK|VGA0_M2_DIVISOR_MASK)
2631
+
#define VGA0_POSTDIV_MASK ((1<<7)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2632
+
#define VGA1_POSTDIV_MASK ((1<<15)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
2633
+
#define VGA_POSTDIV_RESERVED ~(VGA0_POSTDIV_MASK|VGA1_POSTDIV_MASK|(1<<7)|(1<<15))
2634
+
#define DPLLA_POSTDIV_MASK ((1<<23)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2635
+
#define DPLLA_RESERVED ((1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<22)|(1<<15)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2636
+
#define ADPA_RESERVED ((1<<2)|(1<<1)|1|(1<<9)|(1<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<24)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2637
+
#define SUPER_WORD 32
2638
+
#define BURST_A_MASK ((1<<11)|(1<<10)|(1<<9)|(1<<8))
2639
+
#define BURST_B_MASK ((1<<26)|(1<<25)|(1<<24))
2640
+
#define WATER_A_MASK ((1<<5)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|1)
2641
+
#define WATER_B_MASK ((1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16))
2642
+
#define WATER_RESERVED ((1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<7)|(1<<6))
2643
+
#define PIPEACONF_RESERVED ((1<<29)|(1<<28)|(1<<27)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)
2644
+
#define PIPEBCONF_RESERVED ((1<<30)|(1<<29)|(1<<28)|(1<<27)|(1<<26)|(1<<25)|(1<<23)|(1<<22)|(1<<21)|(1<<20)|(1<<19)|(1<<18)|(1<<17)|(1<<16)|0xffff)
2645
+
#define DSPACNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0xffff)
2646
+
#define DSPBCNTR_RESERVED ((1<<23)|(1<<19)|(1<<17)|(1<<16)|0x7ffe)
2647
+
2648
+
#define I830_GMCH_CTRL 0x52
2649
+
2650
+
#define I830_GMCH_ENABLED 0x4
2651
+
#define I830_GMCH_MEM_MASK 0x1
2652
+
#define I830_GMCH_MEM_64M 0x1
2653
+
#define I830_GMCH_MEM_128M 0
2654
+
2655
+
#define I830_GMCH_GMS_MASK 0x70
2656
+
#define I830_GMCH_GMS_DISABLED 0x00
2657
+
#define I830_GMCH_GMS_LOCAL 0x10
2658
+
#define I830_GMCH_GMS_STOLEN_512 0x20
2659
+
#define I830_GMCH_GMS_STOLEN_1024 0x30
2660
+
#define I830_GMCH_GMS_STOLEN_8192 0x40
2661
+
2662
+
#define I830_RDRAM_CHANNEL_TYPE 0x03010
2663
+
#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
2664
+
#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
2665
+
2666
+
#define I855_GMCH_GMS_MASK (0xF << 4)
2667
+
#define I855_GMCH_GMS_DISABLED 0x00
2668
+
#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
2669
+
#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
2670
+
#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
2671
+
#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
2672
+
#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
2673
+
#define I915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
2674
+
#define I915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
2675
+
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
2676
+
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
2677
+
#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
2678
+
#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
2679
+
#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
2680
+
#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
2681
+
2682
+
2683
+
#define I85X_CAPID 0x44
2684
+
#define I85X_VARIANT_MASK 0x7
2685
+
#define I85X_VARIANT_SHIFT 5
2686
+
#define I855_GME 0x0
2687
+
#define I855_GM 0x4
2688
+
#define I852_GME 0x2
2689
+
#define I852_GM 0x5
2690
+
2691
+
#define I915_GCFGC 0xf0
2692
+
#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
2693
+
#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
2694
+
#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
2695
+
#define I915_DISPLAY_CLOCK_MASK (7 << 4)
2696
+
2697
+
#define I855_HPLLCC 0xc0
2698
+
#define I855_CLOCK_CONTROL_MASK (3 << 0)
2699
+
#define I855_CLOCK_133_200 (0 << 0)
2700
+
#define I855_CLOCK_100_200 (1 << 0)
2701
+
#define I855_CLOCK_100_133 (2 << 0)
2702
+
#define I855_CLOCK_166_250 (3 << 0)
2703
+
2704
+
/* BLT commands */
2705
+
#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3))
2706
+
#define COLOR_BLT_WRITE_ALPHA (1<<21)
2707
+
#define COLOR_BLT_WRITE_RGB (1<<20)
2708
+
2709
+
#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4))
2710
+
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
2711
+
#define XY_COLOR_BLT_WRITE_RGB (1<<20)
2712
+
#define XY_COLOR_BLT_TILED (1<<11)
2713
+
2714
+
#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1)
2715
+
2716
+
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
2717
+
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
2718
+
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
2719
+
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
2720
+
#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
2721
+
2722
+
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4)
2723
+
#define SRC_COPY_BLT_WRITE_ALPHA (1<<21)
2724
+
#define SRC_COPY_BLT_WRITE_RGB (1<<20)
2725
+
2726
+
#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22))
2727
+
2728
+
#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7)
2729
+
#define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8))
2730
+
#define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12))
2731
+
#define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21)
2732
+
#define XY_MONO_PAT_BLT_WRITE_RGB (1<<20)
2733
+
2734
+
#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6))
2735
+
#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21)
2736
+
#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20)
2737
+
2738
+
#define MI_STORE_DWORD_IMM ((0x20<<23)|2)
2739
+
#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
2740
+
2741
+
#define MI_SET_CONTEXT (0x18<<23)
2742
+
#define CTXT_NO_RESTORE (1)
2743
+
#define CTXT_PALETTE_SAVE_DISABLE (1<<3)
2744
+
#define CTXT_PALETTE_RESTORE_DISABLE (1<<2)
2745
+
2746
+
/* Dword 0 */
2747
+
#define MI_VERTEX_BUFFER (0x17<<23)
2748
+
#define MI_VERTEX_BUFFER_IDX(x) (x<<20)
2749
+
#define MI_VERTEX_BUFFER_PITCH(x) (x<<13)
2750
+
#define MI_VERTEX_BUFFER_WIDTH(x) (x<<6)
2751
+
/* Dword 1 */
2752
+
#define MI_VERTEX_BUFFER_DISABLE (1)
2753
+
2754
+
/* Overlay Flip */
2755
+
#define MI_OVERLAY_FLIP (0x11<<23)
2756
+
#define MI_OVERLAY_FLIP_CONTINUE (0<<21)
2757
+
#define MI_OVERLAY_FLIP_ON (1<<21)
2758
+
#define MI_OVERLAY_FLIP_OFF (2<<21)
2759
+
2760
+
/* Wait for Events */
2761
+
#define MI_WAIT_FOR_EVENT (0x03<<23)
2762
+
#define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18)
2763
+
#define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17)
2764
+
#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
2765
+
#define MI_WAIT_FOR_PIPEB_VBLANK (1<<7)
2766
+
#define MI_WAIT_FOR_PIPEA_VBLANK (1<<3)
2767
+
#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5)
2768
+
#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1)
2769
+
2770
+
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
2771
+
2772
+
/* Flush */
2773
+
#define MI_FLUSH (0x04<<23)
2774
+
#define MI_WRITE_DIRTY_STATE (1<<4)
2775
+
#define MI_END_SCENE (1<<3)
2776
+
#define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3)
2777
+
#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2)
2778
+
#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1)
2779
+
#define MI_INVALIDATE_MAP_CACHE (1<<0)
2780
+
/* broadwater flush bits */
2781
+
#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3)
2782
+
2783
+
/* Noop */
2784
+
#define MI_NOOP 0x00
2785
+
#define MI_NOOP_WRITE_ID (1<<22)
2786
+
#define MI_NOOP_ID_MASK (1<<22 - 1)
2787
+
2788
+
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
2789
+
2790
+
/* Batch */
2791
+
#define MI_BATCH_BUFFER ((0x30 << 23) | 1)
2792
+
#define MI_BATCH_BUFFER_START (0x31 << 23)
2793
+
#define MI_BATCH_BUFFER_END (0xA << 23)
2794
+
#define MI_BATCH_NON_SECURE (1)
2795
+
#define MI_BATCH_NON_SECURE_I965 (1 << 8)
2796
+
2797
+
#define MAX_DISPLAY_PIPES 2
2798
+
2799
+
typedef enum {
2800
+
CrtIndex = 0,
2801
+
TvIndex,
2802
+
DfpIndex,
2803
+
LfpIndex,
2804
+
Crt2Index,
2805
+
Tv2Index,
2806
+
Dfp2Index,
2807
+
Lfp2Index,
2808
+
NumDisplayTypes
2809
+
} DisplayType;
2810
+
2811
+
/* What's connected to the pipes (as reported by the BIOS) */
2812
+
#define PIPE_ACTIVE_MASK 0xff
2813
+
#define PIPE_CRT_ACTIVE (1 << CrtIndex)
2814
+
#define PIPE_TV_ACTIVE (1 << TvIndex)
2815
+
#define PIPE_DFP_ACTIVE (1 << DfpIndex)
2816
+
#define PIPE_LCD_ACTIVE (1 << LfpIndex)
2817
+
#define PIPE_CRT2_ACTIVE (1 << Crt2Index)
2818
+
#define PIPE_TV2_ACTIVE (1 << Tv2Index)
2819
+
#define PIPE_DFP2_ACTIVE (1 << Dfp2Index)
2820
+
#define PIPE_LCD2_ACTIVE (1 << Lfp2Index)
2821
+
2822
+
#define PIPE_SIZED_DISP_MASK (PIPE_DFP_ACTIVE | \
2823
+
PIPE_LCD_ACTIVE | \
2824
+
PIPE_DFP2_ACTIVE)
2825
+
2826
+
#define PIPE_A_SHIFT 0
2827
+
#define PIPE_B_SHIFT 8
2828
+
#define PIPE_SHIFT(n) ((n) == 0 ? \
2829
+
PIPE_A_SHIFT : PIPE_B_SHIFT)
2830
+
2831
+
/*
2832
+
* Some BIOS scratch area registers. The 845 (and 830?) store the amount
2833
+
* of video memory available to the BIOS in SWF1.
2834
+
*/
2835
+
2836
+
#define SWF0 0x71410
2837
+
#define SWF1 0x71414
2838
+
#define SWF2 0x71418
2839
+
#define SWF3 0x7141c
2840
+
#define SWF4 0x71420
2841
+
#define SWF5 0x71424
2842
+
#define SWF6 0x71428
2843
+
2844
+
/*
2845
+
* 855 scratch registers.
2846
+
*/
2847
+
#define SWF00 0x70410
2848
+
#define SWF01 0x70414
2849
+
#define SWF02 0x70418
2850
+
#define SWF03 0x7041c
2851
+
#define SWF04 0x70420
2852
+
#define SWF05 0x70424
2853
+
#define SWF06 0x70428
2854
+
2855
+
#define SWF10 SWF0
2856
+
#define SWF11 SWF1
2857
+
#define SWF12 SWF2
2858
+
#define SWF13 SWF3
2859
+
#define SWF14 SWF4
2860
+
#define SWF15 SWF5
2861
+
#define SWF16 SWF6
2862
+
2863
+
#define SWF30 0x72414
2864
+
#define SWF31 0x72418
2865
+
#define SWF32 0x7241c
2866
+
2867
+
/*
2868
+
* Overlay registers. These are overlay registers accessed via MMIO.
2869
+
* Those loaded via the overlay register page are defined in i830_video.c.
2870
+
*/
2871
+
#define OVADD 0x30000
2872
+
2873
+
#define DOVSTA 0x30008
2874
+
#define OC_BUF (0x3<<20)
2875
+
2876
+
#define OGAMC5 0x30010
2877
+
#define OGAMC4 0x30014
2878
+
#define OGAMC3 0x30018
2879
+
#define OGAMC2 0x3001c
2880
+
#define OGAMC1 0x30020
2881
+
#define OGAMC0 0x30024
2882
+
2883
+
2884
+
/*
2885
+
* Palette registers
2886
+
*/
2887
+
#define PALETTE_A 0x0a000
2888
+
#define PALETTE_B 0x0a800
2889
+
2890
+
/* Framebuffer compression */
2891
+
#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
2892
+
#define FBC_LL_BASE 0x03204 /* 4k page aligned */
2893
+
#define FBC_CONTROL 0x03208
2894
+
#define FBC_CTL_EN (1<<31)
2895
+
#define FBC_CTL_PERIODIC (1<<30)
2896
+
#define FBC_CTL_INTERVAL_SHIFT (16)
2897
+
#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2898
+
#define FBC_CTL_STRIDE_SHIFT (5)
2899
+
#define FBC_CTL_FENCENO (1<<0)
2900
+
#define FBC_COMMAND 0x0320c
2901
+
#define FBC_CMD_COMPRESS (1<<0)
2902
+
#define FBC_STATUS 0x03210
2903
+
#define FBC_STAT_COMPRESSING (1<<31)
2904
+
#define FBC_STAT_COMPRESSED (1<<30)
2905
+
#define FBC_STAT_MODIFIED (1<<29)
2906
+
#define FBC_STAT_CURRENT_LINE (1<<0)
2907
+
#define FBC_CONTROL2 0x03214
2908
+
#define FBC_CTL_FENCE_DBL (0<<4)
2909
+
#define FBC_CTL_IDLE_IMM (0<<2)
2910
+
#define FBC_CTL_IDLE_FULL (1<<2)
2911
+
#define FBC_CTL_IDLE_LINE (2<<2)
2912
+
#define FBC_CTL_IDLE_DEBUG (3<<2)
2913
+
#define FBC_CTL_CPU_FENCE (1<<1)
2914
+
#define FBC_CTL_PLANEA (0<<0)
2915
+
#define FBC_CTL_PLANEB (1<<0)
2916
+
#define FBC_FENCE_OFF 0x0321b
2917
+
#define FBC_MOD_NUM 0x03220
2918
+
#define FBC_TAG_DEBUG 0x03300
2919
+
2920
+
#define FBC_LL_SIZE (1536)
2921
+
#define FBC_LL_PAD (32)
2922
+
2923
+
/* Framebuffer compression version 2 */
2924
+
#define DPFC_CB_BASE 0x3200
2925
+
#define DPFC_CONTROL 0x3208
2926
+
#define DPFC_CTL_EN (1<<31)
2927
+
#define DPFC_CTL_PLANEA (0<<30)
2928
+
#define DPFC_CTL_PLANEB (1<<30)
2929
+
#define DPFC_CTL_FENCE_EN (1<<29)
2930
+
#define DPFC_CTL_LIMIT_1X (0<<6)
2931
+
#define DPFC_CTL_LIMIT_2X (1<<6)
2932
+
#define DPFC_CTL_LIMIT_4X (2<<6)
2933
+
#define DPFC_RECOMP_CTL 0x320c
2934
+
#define DPFC_RECOMP_STALL_EN (1<<27)
2935
+
#define DPFC_RECOMP_STALL_WM_SHIFT (16)
2936
+
#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2937
+
#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2938
+
#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2939
+
#define DPFC_STATUS 0x3210
2940
+
#define DPFC_INVAL_SEG_SHIFT (16)
2941
+
#define DPFC_INVAL_SEG_MASK (0x07ff0000)
2942
+
#define DPFC_COMP_SEG_SHIFT (0)
2943
+
#define DPFC_COMP_SEG_MASK (0x000003ff)
2944
+
#define DPFC_STATUS2 0x3214
2945
+
#define DPFC_FENCE_YOFF 0x3218
2946
+
2947
+
#define PEG_BAND_GAP_DATA 0x14d68
2948
+
2949
+
#define MCHBAR_RENDER_STANDBY 0x111B8
2950
+
#define RENDER_STANDBY_ENABLE (1 << 30)
2951
+
2952
+
2953
+
/* Ironlake */
2954
+
2955
+
/* warmup time in us */
2956
+
#define WARMUP_PCH_REF_CLK_SSC_MOD 1
2957
+
#define WARMUP_PCH_FDI_RECEIVER_PLL 25
2958
+
#define WARMUP_PCH_DPLL 50
2959
+
#define WARMUP_CPU_DP_PLL 20
2960
+
#define WARMUP_CPU_FDI_TRANSMITTER_PLL 10
2961
+
#define WARMUP_DMI_LATENCY 20
2962
+
#define FDI_TRAIN_PATTERN_1_TIME 0.5
2963
+
#define FDI_TRAIN_PATTERN_2_TIME 1.5
2964
+
#define FDI_ONE_IDLE_PATTERN_TIME 31
2965
+
2966
+
#define CPU_VGACNTRL 0x41000
2967
+
2968
+
#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2969
+
#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2970
+
#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2971
+
#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2972
+
#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2973
+
#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2974
+
#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2975
+
#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2976
+
#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2977
+
2978
+
/* refresh rate hardware control */
2979
+
#define RR_HW_CTL 0x45300
2980
+
#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2981
+
#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2982
+
2983
+
#define FDI_PLL_BIOS_0 0x46000
2984
+
#define FDI_PLL_BIOS_1 0x46004
2985
+
#define FDI_PLL_BIOS_2 0x46008
2986
+
#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2987
+
#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2988
+
#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2989
+
2990
+
#define FDI_PLL_FREQ_CTL 0x46030
2991
+
#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2992
+
#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2993
+
#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2994
+
2995
+
#define PIPEA_DATA_M1 0x60030
2996
+
#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2997
+
#define TU_SIZE_MASK 0x7e000000
2998
+
#define PIPEA_DATA_M1_OFFSET 0
2999
+
#define PIPEA_DATA_N1 0x60034
3000
+
#define PIPEA_DATA_N1_OFFSET 0
3001
+
3002
+
#define PIPEA_DATA_M2 0x60038
3003
+
#define PIPEA_DATA_M2_OFFSET 0
3004
+
#define PIPEA_DATA_N2 0x6003c
3005
+
#define PIPEA_DATA_N2_OFFSET 0
3006
+
3007
+
#define PIPEA_LINK_M1 0x60040
3008
+
#define PIPEA_LINK_M1_OFFSET 0
3009
+
#define PIPEA_LINK_N1 0x60044
3010
+
#define PIPEA_LINK_N1_OFFSET 0
3011
+
3012
+
#define PIPEA_LINK_M2 0x60048
3013
+
#define PIPEA_LINK_M2_OFFSET 0
3014
+
#define PIPEA_LINK_N2 0x6004c
3015
+
#define PIPEA_LINK_N2_OFFSET 0
3016
+
3017
+
/* PIPEB timing regs are same start from 0x61000 */
3018
+
3019
+
#define PIPEB_DATA_M1 0x61030
3020
+
#define PIPEB_DATA_N1 0x61034
3021
+
3022
+
#define PIPEB_DATA_M2 0x61038
3023
+
#define PIPEB_DATA_N2 0x6103c
3024
+
3025
+
#define PIPEB_LINK_M1 0x61040
3026
+
#define PIPEB_LINK_N1 0x61044
3027
+
3028
+
#define PIPEB_LINK_M2 0x61048
3029
+
#define PIPEB_LINK_N2 0x6104c
3030
+
3031
+
/* PIPEC timing regs */
3032
+
3033
+
#define PIPEC_DATA_M1 0x62030
3034
+
#define PIPEC_DATA_N1 0x62034
3035
+
3036
+
#define PIPEC_DATA_M2 0x62038
3037
+
#define PIPEC_DATA_N2 0x6203c
3038
+
3039
+
#define PIPEC_LINK_M1 0x62040
3040
+
#define PIPEC_LINK_N1 0x62044
3041
+
3042
+
#define PIPEC_LINK_M2 0x62048
3043
+
#define PIPEC_LINK_N2 0x6204c
3044
+
3045
+
#define PIPEEDP_DATA_M1 0x6F030
3046
+
#define PIPEEDP_DATA_N1 0x6F034
3047
+
3048
+
#define PIPEEDP_LINK_M1 0x6F040
3049
+
#define PIPEEDP_LINK_N1 0x6F044
3050
+
3051
+
/* PIPECONF for pipe A/B addr is same */
3052
+
3053
+
/* cusor A is only connected to pipe A,
3054
+
cursor B is connected to pipe B. Otherwise no change. */
3055
+
3056
+
/* Plane A/B, DSPACNTR/DSPBCNTR addr not changed */
3057
+
3058
+
/* CPU panel fitter */
3059
+
#define PFA_CTL_1 0x68080
3060
+
#define PFB_CTL_1 0x68880
3061
+
#define PFC_CTL_1 0x69080
3062
+
#define PF_ENABLE (1<<31)
3063
+
#define PFA_CTL_2 0x68084
3064
+
#define PFB_CTL_2 0x68884
3065
+
#define PFC_CTL_2 0x69084
3066
+
#define PFA_CTL_3 0x68088
3067
+
#define PFB_CTL_3 0x68888
3068
+
#define PFC_CTL_3 0x69088
3069
+
#define PFA_CTL_4 0x68090
3070
+
#define PFB_CTL_4 0x68890
3071
+
#define PFC_CTL_4 0x69090
3072
+
3073
+
#define PFA_WIN_POS 0x68070
3074
+
#define PFB_WIN_POS 0x68870
3075
+
#define PFC_WIN_POS 0x69070
3076
+
#define PFA_WIN_SIZE 0x68074
3077
+
#define PFB_WIN_SIZE 0x68874
3078
+
#define PFC_WIN_SIZE 0x69074
3079
+
3080
+
/* legacy palette */
3081
+
#define LGC_PALETTE_A 0x4a000
3082
+
#define LGC_PALETTE_B 0x4a800
3083
+
3084
+
/* interrupts */
3085
+
#define DE_MASTER_IRQ_CONTROL (1 << 31)
3086
+
#define DE_SPRITEB_FLIP_DONE (1 << 29)
3087
+
#define DE_SPRITEA_FLIP_DONE (1 << 28)
3088
+
#define DE_PLANEB_FLIP_DONE (1 << 27)
3089
+
#define DE_PLANEA_FLIP_DONE (1 << 26)
3090
+
#define DE_PCU_EVENT (1 << 25)
3091
+
#define DE_GTT_FAULT (1 << 24)
3092
+
#define DE_POISON (1 << 23)
3093
+
#define DE_PERFORM_COUNTER (1 << 22)
3094
+
#define DE_PCH_EVENT (1 << 21)
3095
+
#define DE_AUX_CHANNEL_A (1 << 20)
3096
+
#define DE_DP_A_HOTPLUG (1 << 19)
3097
+
#define DE_GSE (1 << 18)
3098
+
#define DE_PIPEB_VBLANK (1 << 15)
3099
+
#define DE_PIPEB_EVEN_FIELD (1 << 14)
3100
+
#define DE_PIPEB_ODD_FIELD (1 << 13)
3101
+
#define DE_PIPEB_LINE_COMPARE (1 << 12)
3102
+
#define DE_PIPEB_VSYNC (1 << 11)
3103
+
#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
3104
+
#define DE_PIPEA_VBLANK (1 << 7)
3105
+
#define DE_PIPEA_EVEN_FIELD (1 << 6)
3106
+
#define DE_PIPEA_ODD_FIELD (1 << 5)
3107
+
#define DE_PIPEA_LINE_COMPARE (1 << 4)
3108
+
#define DE_PIPEA_VSYNC (1 << 3)
3109
+
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
3110
+
3111
+
#define DEISR 0x44000
3112
+
#define DEIMR 0x44004
3113
+
#define DEIIR 0x44008
3114
+
#define DEIER 0x4400c
3115
+
3116
+
/* GT interrupt */
3117
+
#define GT_SYNC_STATUS (1 << 2)
3118
+
#define GT_USER_INTERRUPT (1 << 0)
3119
+
3120
+
#define GTISR 0x44010
3121
+
#define GTIMR 0x44014
3122
+
#define GTIIR 0x44018
3123
+
#define GTIER 0x4401c
3124
+
3125
+
/* PCH */
3126
+
3127
+
/* south display engine interrupt */
3128
+
#define SDE_CRT_HOTPLUG (1 << 11)
3129
+
#define SDE_PORTD_HOTPLUG (1 << 10)
3130
+
#define SDE_PORTC_HOTPLUG (1 << 9)
3131
+
#define SDE_PORTB_HOTPLUG (1 << 8)
3132
+
#define SDE_SDVOB_HOTPLUG (1 << 6)
3133
+
3134
+
#define SDEISR 0xc4000
3135
+
#define SDEIMR 0xc4004
3136
+
#define SDEIIR 0xc4008
3137
+
#define SDEIER 0xc400c
3138
+
3139
+
/* digital port hotplug */
3140
+
#define PCH_PORT_HOTPLUG 0xc4030
3141
+
#define PORTD_HOTPLUG_ENABLE (1 << 20)
3142
+
#define PORTD_PULSE_DURATION_2ms (0)
3143
+
#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
3144
+
#define PORTD_PULSE_DURATION_6ms (2 << 18)
3145
+
#define PORTD_PULSE_DURATION_100ms (3 << 18)
3146
+
#define PORTD_HOTPLUG_NO_DETECT (0)
3147
+
#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3148
+
#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
3149
+
#define PORTC_HOTPLUG_ENABLE (1 << 12)
3150
+
#define PORTC_PULSE_DURATION_2ms (0)
3151
+
#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
3152
+
#define PORTC_PULSE_DURATION_6ms (2 << 10)
3153
+
#define PORTC_PULSE_DURATION_100ms (3 << 10)
3154
+
#define PORTC_HOTPLUG_NO_DETECT (0)
3155
+
#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3156
+
#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
3157
+
#define PORTB_HOTPLUG_ENABLE (1 << 4)
3158
+
#define PORTB_PULSE_DURATION_2ms (0)
3159
+
#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
3160
+
#define PORTB_PULSE_DURATION_6ms (2 << 2)
3161
+
#define PORTB_PULSE_DURATION_100ms (3 << 2)
3162
+
#define PORTB_HOTPLUG_NO_DETECT (0)
3163
+
#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3164
+
#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
3165
+
3166
+
#define PCH_GPIOA 0xc5010
3167
+
#define PCH_GPIOB 0xc5014
3168
+
#define PCH_GPIOC 0xc5018
3169
+
#define PCH_GPIOD 0xc501c
3170
+
#define PCH_GPIOE 0xc5020
3171
+
#define PCH_GPIOF 0xc5024
3172
+
#define PCH_GMBUS0 0xc5100
3173
+
#define PCH_GMBUS1 0xc5104
3174
+
#define PCH_GMBUS2 0xc5108
3175
+
#define PCH_GMBUS3 0xc510c
3176
+
#define PCH_GMBUS4 0xc5110
3177
+
#define PCH_GMBUS5 0xc5120
3178
+
3179
+
#define PCH_DPLL_A 0xc6014
3180
+
#define PCH_DPLL_B 0xc6018
3181
+
3182
+
#define PCH_FPA0 0xc6040
3183
+
#define PCH_FPA1 0xc6044
3184
+
#define PCH_FPB0 0xc6048
3185
+
#define PCH_FPB1 0xc604c
3186
+
3187
+
#define PCH_DPLL_TEST 0xc606c
3188
+
3189
+
#define PCH_DREF_CONTROL 0xC6200
3190
+
#define DREF_CONTROL_MASK 0x7fc3
3191
+
#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
3192
+
#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
3193
+
#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
3194
+
#define DREF_SSC_SOURCE_DISABLE (0<<11)
3195
+
#define DREF_SSC_SOURCE_ENABLE (2<<11)
3196
+
#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
3197
+
#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
3198
+
#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
3199
+
#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
3200
+
#define DREF_SSC4_DOWNSPREAD (0<<6)
3201
+
#define DREF_SSC4_CENTERSPREAD (1<<6)
3202
+
#define DREF_SSC1_DISABLE (0<<1)
3203
+
#define DREF_SSC1_ENABLE (1<<1)
3204
+
#define DREF_SSC4_DISABLE (0)
3205
+
#define DREF_SSC4_ENABLE (1)
3206
+
3207
+
#define PCH_RAWCLK_FREQ 0xc6204
3208
+
#define FDL_TP1_TIMER_SHIFT 12
3209
+
#define FDL_TP1_TIMER_MASK (3<<12)
3210
+
#define FDL_TP2_TIMER_SHIFT 10
3211
+
#define FDL_TP2_TIMER_MASK (3<<10)
3212
+
#define RAWCLK_FREQ_MASK 0x3ff
3213
+
3214
+
#define PCH_DPLL_TMR_CFG 0xc6208
3215
+
3216
+
#define PCH_SSC4_PARMS 0xc6210
3217
+
#define PCH_SSC4_AUX_PARMS 0xc6214
3218
+
3219
+
/* CPT */
3220
+
#define PCH_DPLL_ANALOG_CTL 0xc6300
3221
+
3222
+
#define PCH_DPLL_SEL 0xc7000
3223
+
#define TRANSA_DPLL_ENABLE (1<<3)
3224
+
#define TRANSA_DPLLA_SEL (0)
3225
+
#define TRANSA_DPLLB_SEL (1<<0)
3226
+
#define TRANSB_DPLL_ENABLE (1<<7)
3227
+
#define TRANSB_DPLLA_SEL (0<<4)
3228
+
#define TRANSB_DPLLB_SEL (1<<4)
3229
+
#define TRANSC_DPLL_ENABLE (1<<11)
3230
+
#define TRANSC_DPLLA_SEL (0<<8)
3231
+
#define TRANSC_DPLLB_SEL (1<<8)
3232
+
3233
+
/* transcoder */
3234
+
3235
+
#define TRANS_HTOTAL_A 0xe0000
3236
+
#define TRANS_HTOTAL_SHIFT 16
3237
+
#define TRANS_HACTIVE_SHIFT 0
3238
+
#define TRANS_HBLANK_A 0xe0004
3239
+
#define TRANS_HBLANK_END_SHIFT 16
3240
+
#define TRANS_HBLANK_START_SHIFT 0
3241
+
#define TRANS_HSYNC_A 0xe0008
3242
+
#define TRANS_HSYNC_END_SHIFT 16
3243
+
#define TRANS_HSYNC_START_SHIFT 0
3244
+
#define TRANS_VTOTAL_A 0xe000c
3245
+
#define TRANS_VTOTAL_SHIFT 16
3246
+
#define TRANS_VACTIVE_SHIFT 0
3247
+
#define TRANS_VBLANK_A 0xe0010
3248
+
#define TRANS_VBLANK_END_SHIFT 16
3249
+
#define TRANS_VBLANK_START_SHIFT 0
3250
+
#define TRANS_VSYNC_A 0xe0014
3251
+
#define TRANS_VSYNC_END_SHIFT 16
3252
+
#define TRANS_VSYNC_START_SHIFT 0
3253
+
#define TRANS_VSYNCSHIFT_A 0xe0028
3254
+
3255
+
#define TRANSA_DATA_M1 0xe0030
3256
+
#define TRANSA_DATA_N1 0xe0034
3257
+
#define TRANSA_DATA_M2 0xe0038
3258
+
#define TRANSA_DATA_N2 0xe003c
3259
+
#define TRANSA_DP_LINK_M1 0xe0040
3260
+
#define TRANSA_DP_LINK_N1 0xe0044
3261
+
#define TRANSA_DP_LINK_M2 0xe0048
3262
+
#define TRANSA_DP_LINK_N2 0xe004c
3263
+
3264
+
#define TRANS_HTOTAL_B 0xe1000
3265
+
#define TRANS_HBLANK_B 0xe1004
3266
+
#define TRANS_HSYNC_B 0xe1008
3267
+
#define TRANS_VTOTAL_B 0xe100c
3268
+
#define TRANS_VBLANK_B 0xe1010
3269
+
#define TRANS_VSYNC_B 0xe1014
3270
+
#define TRANS_VSYNCSHIFT_B 0xe1028
3271
+
3272
+
#define TRANSB_DATA_M1 0xe1030
3273
+
#define TRANSB_DATA_N1 0xe1034
3274
+
#define TRANSB_DATA_M2 0xe1038
3275
+
#define TRANSB_DATA_N2 0xe103c
3276
+
#define TRANSB_DP_LINK_M1 0xe1040
3277
+
#define TRANSB_DP_LINK_N1 0xe1044
3278
+
#define TRANSB_DP_LINK_M2 0xe1048
3279
+
#define TRANSB_DP_LINK_N2 0xe104c
3280
+
3281
+
#define TRANS_HTOTAL_C 0xe2000
3282
+
#define TRANS_HBLANK_C 0xe2004
3283
+
#define TRANS_HSYNC_C 0xe2008
3284
+
#define TRANS_VTOTAL_C 0xe200c
3285
+
#define TRANS_VBLANK_C 0xe2010
3286
+
#define TRANS_VSYNC_C 0xe2014
3287
+
#define TRANS_VSYNCSHIFT_C 0xe2028
3288
+
3289
+
#define TRANSC_DATA_M1 0xe2030
3290
+
#define TRANSC_DATA_N1 0xe2034
3291
+
#define TRANSC_DATA_M2 0xe2038
3292
+
#define TRANSC_DATA_N2 0xe203c
3293
+
#define TRANSC_DP_LINK_M1 0xe2040
3294
+
#define TRANSC_DP_LINK_N1 0xe2044
3295
+
#define TRANSC_DP_LINK_M2 0xe2048
3296
+
#define TRANSC_DP_LINK_N2 0xe204c
3297
+
3298
+
#define TRANSACONF 0xf0008
3299
+
#define TRANSBCONF 0xf1008
3300
+
#define TRANSCCONF 0xf2008
3301
+
#define TRANS_DISABLE (0<<31)
3302
+
#define TRANS_ENABLE (1<<31)
3303
+
#define TRANS_STATE_MASK (1<<30)
3304
+
#define TRANS_STATE_DISABLE (0<<30)
3305
+
#define TRANS_STATE_ENABLE (1<<30)
3306
+
#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3307
+
#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3308
+
#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3309
+
#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3310
+
#define TRANS_DP_AUDIO_ONLY (1<<26)
3311
+
#define TRANS_DP_VIDEO_AUDIO (0<<26)
3312
+
#define TRANS_PROGRESSIVE (0<<21)
3313
+
#define TRANS_8BPC (0<<5)
3314
+
#define TRANS_10BPC (1<<5)
3315
+
#define TRANS_6BPC (2<<5)
3316
+
#define TRANS_12BPC (3<<5)
3317
+
3318
+
#define FDI_RXA_CHICKEN 0xc200c
3319
+
#define FDI_RXB_CHICKEN 0xc2010
3320
+
#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
3321
+
3322
+
/* CPU: FDI_TX */
3323
+
#define FDI_TXA_CTL 0x60100
3324
+
#define FDI_TXB_CTL 0x61100
3325
+
#define FDI_TXC_CTL 0x62100
3326
+
#define FDI_TX_DISABLE (0<<31)
3327
+
#define FDI_TX_ENABLE (1<<31)
3328
+
#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3329
+
#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3330
+
#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3331
+
#define FDI_LINK_TRAIN_NONE (3<<28)
3332
+
#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3333
+
#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3334
+
#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3335
+
#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3336
+
#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3337
+
#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3338
+
#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3339
+
#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3340
+
/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3341
+
SNB has different settings. */
3342
+
/* SNB A-stepping */
3343
+
#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3344
+
#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3345
+
#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3346
+
#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3347
+
/* SNB B-stepping */
3348
+
#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3349
+
#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3350
+
#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3351
+
#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3352
+
#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3353
+
#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3354
+
#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3355
+
#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3356
+
#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3357
+
#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3358
+
/* Ironlake: hardwired to 1 */
3359
+
#define FDI_TX_PLL_ENABLE (1<<14)
3360
+
/* both Tx and Rx */
3361
+
#define FDI_SCRAMBLING_ENABLE (0<<7)
3362
+
#define FDI_SCRAMBLING_DISABLE (1<<7)
3363
+
3364
+
/* Additional cpu TX control regs, from ivb bspec */
3365
+
#define DPAFE_BMFUNC 0x6c024
3366
+
#define DPAFE_DL_IREFCAL0 0x6c02c
3367
+
#define DPAFE_DL_IREFCAL1 0x6c030
3368
+
#define DPAFE_DP_IREFCAL 0x6c034
3369
+
3370
+
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3371
+
#define FDI_RXA_CTL 0xf000c
3372
+
#define FDI_RXB_CTL 0xf100c
3373
+
#define FDI_RXC_CTL 0xf200c
3374
+
#define FDI_RX_ENABLE (1<<31)
3375
+
#define FDI_RX_DISABLE (0<<31)
3376
+
/* train, dp width same as FDI_TX */
3377
+
#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3378
+
#define FDI_8BPC (0<<16)
3379
+
#define FDI_10BPC (1<<16)
3380
+
#define FDI_6BPC (2<<16)
3381
+
#define FDI_12BPC (3<<16)
3382
+
#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3383
+
#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3384
+
#define FDI_RX_PLL_ENABLE (1<<13)
3385
+
#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3386
+
#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3387
+
#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3388
+
#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3389
+
#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3390
+
#define FDI_SEL_RAWCLK (0<<4)
3391
+
#define FDI_SEL_PCDCLK (1<<4)
3392
+
/* CPT */
3393
+
#define FDI_AUTO_TRAINING (1<<10)
3394
+
#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3395
+
#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3396
+
#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3397
+
#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3398
+
#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3399
+
3400
+
#define FDI_RXA_MISC 0xf0010
3401
+
#define FDI_RXB_MISC 0xf1010
3402
+
#define FDI_RXC_MISC 0xf2010
3403
+
#define FDI_RXA_TUSIZE1 0xf0030
3404
+
#define FDI_RXA_TUSIZE2 0xf0038
3405
+
#define FDI_RXB_TUSIZE1 0xf1030
3406
+
#define FDI_RXB_TUSIZE2 0xf1038
3407
+
#define FDI_RXC_TUSIZE1 0xf2030
3408
+
#define FDI_RXC_TUSIZE2 0xf2038
3409
+
3410
+
/* FDI_RX interrupt register format */
3411
+
#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3412
+
#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3413
+
#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3414
+
#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3415
+
#define FDI_RX_FS_CODE_ERR (1<<6)
3416
+
#define FDI_RX_FE_CODE_ERR (1<<5)
3417
+
#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3418
+
#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3419
+
#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3420
+
#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3421
+
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3422
+
3423
+
#define FDI_RXA_IIR 0xf0014
3424
+
#define FDI_RXA_IMR 0xf0018
3425
+
#define FDI_RXB_IIR 0xf1014
3426
+
#define FDI_RXB_IMR 0xf1018
3427
+
3428
+
#define FDI_PLL_CTL_1 0xfe000
3429
+
#define FDI_PLL_CTL_2 0xfe004
3430
+
3431
+
/* CRT */
3432
+
#define PCH_ADPA 0xe1100
3433
+
#define ADPA_TRANS_SELECT_MASK (1<<30)
3434
+
#define ADPA_TRANS_A_SELECT 0
3435
+
#define ADPA_TRANS_B_SELECT (1<<30)
3436
+
/* HPD is here */
3437
+
#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3438
+
#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3439
+
#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3440
+
#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3441
+
#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3442
+
#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3443
+
#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3444
+
#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3445
+
#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3446
+
#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3447
+
#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3448
+
#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3449
+
#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3450
+
#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3451
+
#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3452
+
#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3453
+
#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3454
+
#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3455
+
#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3456
+
/* polarity control not changed */
3457
+
3458
+
/* or SDVOB */
3459
+
#define HDMIB 0xe1140
3460
+
#define PORT_ENABLE (1 << 31)
3461
+
#define TRANSCODER_A (0)
3462
+
#define TRANSCODER_B (1 << 30)
3463
+
#define COLOR_FORMAT_8bpc (0)
3464
+
#define COLOR_FORMAT_12bpc (3 << 26)
3465
+
#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3466
+
#define SDVO_ENCODING (0)
3467
+
#define TMDS_ENCODING (2 << 10)
3468
+
#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3469
+
#define SDVOB_BORDER_ENABLE (1 << 7)
3470
+
#define AUDIO_ENABLE (1 << 6)
3471
+
#define VSYNC_ACTIVE_HIGH (1 << 4)
3472
+
#define HSYNC_ACTIVE_HIGH (1 << 3)
3473
+
#define PORT_DETECTED (1 << 2)
3474
+
3475
+
#define HDMIC 0xe1150
3476
+
#define HDMID 0xe1160
3477
+
#define PCH_LVDS 0xe1180
3478
+
3479
+
/* Since IVB, the old _CTL2 is now _CTL and the old _CTL is now _DATA. */
3480
+
#define BLC_PWM_CPU_CTL2 0x48250
3481
+
#define BLC_PWM2_CPU_CTL2 0x48350
3482
+
#define PWM_ENABLE (1 << 31)
3483
+
#define PWM_PIPE_A (0 << 29)
3484
+
#define PWM_PIPE_B (1 << 29)
3485
+
#define BLC_PWM_CPU_CTL 0x48254
3486
+
#define BLC_PWM2_CPU_CTL 0x48354
3487
+
#define BLC_MISC_CTL 0x48360
3488
+
3489
+
#define UTIL_PIN_CTL 0x48400
3490
+
3491
+
#define BLC_PWM_PCH_CTL1 0xc8250
3492
+
#define PWM_PCH_ENABLE (1 << 31)
3493
+
#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3494
+
#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3495
+
#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3496
+
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3497
+
3498
+
#define BLC_PWM_PCH_CTL2 0xc8254
3499
+
3500
+
#define PCH_PP_STATUS 0xc7200
3501
+
#define PCH_PP_CONTROL 0xc7204
3502
+
#define EDP_FORCE_VDD (1 << 3)
3503
+
#define EDP_BLC_ENABLE (1 << 2)
3504
+
#define PANEL_POWER_RESET (1 << 1)
3505
+
#define PANEL_POWER_OFF (0 << 0)
3506
+
#define PANEL_POWER_ON (1 << 0)
3507
+
#define PCH_PP_ON_DELAYS 0xc7208
3508
+
#define EDP_PANEL (1 << 30)
3509
+
#define PCH_PP_OFF_DELAYS 0xc720c
3510
+
#define PCH_PP_DIVISOR 0xc7210
3511
+
3512
+
#define AUD_CONFIG 0x62000
3513
+
#define AUD_DEBUG 0x62010
3514
+
#define AUD_VID_DID 0x62020
3515
+
#define AUD_RID 0x62024
3516
+
#define AUD_SUBN_CNT 0x62028
3517
+
#define AUD_FUNC_GRP 0x62040
3518
+
#define AUD_SUBN_CNT2 0x62044
3519
+
#define AUD_GRP_CAP 0x62048
3520
+
#define AUD_PWRST 0x6204c
3521
+
#define AUD_SUPPWR 0x62050
3522
+
#define AUD_SID 0x62054
3523
+
#define AUD_OUT_CWCAP 0x62070
3524
+
#define AUD_OUT_PCMSIZE 0x62074
3525
+
#define AUD_OUT_STR 0x62078
3526
+
#define AUD_OUT_DIG_CNVT 0x6207c
3527
+
#define AUD_OUT_CH_STR 0x62080
3528
+
#define AUD_OUT_STR_DESC 0x62084
3529
+
#define AUD_PINW_CAP 0x620a0
3530
+
#define AUD_PIN_CAP 0x620a4
3531
+
#define AUD_PINW_CONNLNG 0x620a8
3532
+
#define AUD_PINW_CONNLST 0x620ac
3533
+
#define AUD_PINW_CNTR 0x620b0
3534
+
#define AUD_PINW_UNSOLRESP 0x620b8
3535
+
#define AUD_CNTL_ST 0x620b4
3536
+
#define AUD_PINW_CONFIG 0x620bc
3537
+
#define AUD_HDMIW_STATUS 0x620d4
3538
+
#define AUD_HDMIW_HDMIEDID 0x6210c
3539
+
#define AUD_HDMIW_INFOFR 0x62118
3540
+
#define AUD_CONV_CHCNT 0x62120
3541
+
#define AUD_CTS_ENABLE 0x62128
3542
+
3543
+
#define VIDEO_DIP_CTL 0x61170
3544
+
#define VIDEO_DIP_DATA 0x61178
3545
+
3546
+
/* CPT */
3547
+
#define TRANS_DP_CTL_A 0xe0300
3548
+
#define TRANS_DP_CTL_B 0xe1300
3549
+
#define TRANS_DP_CTL_C 0xe2300
3550
+
#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3551
+
#define TRANS_DP_PORT_SEL_B (0<<29)
3552
+
#define TRANS_DP_PORT_SEL_C (1<<29)
3553
+
#define TRANS_DP_PORT_SEL_D (2<<29)
3554
+
#define TRANS_DP_PORT_SEL_MASK (3<<29)
3555
+
#define TRANS_DP_AUDIO_ONLY (1<<26)
3556
+
#define TRANS_DP_ENH_FRAMING (1<<18)
3557
+
#define TRANS_DP_8BPC (0<<9)
3558
+
#define TRANS_DP_10BPC (1<<9)
3559
+
#define TRANS_DP_6BPC (2<<9)
3560
+
#define TRANS_DP_12BPC (3<<9)
3561
+
#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3562
+
#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3563
+
#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3564
+
#define TRANS_DP_HSYNC_ACTIVE_LOW 0
3565
+
3566
+
/* Debug regs */
3567
+
#define GEN6_TD_CTL 0x7000 /* <= GEN5 was at 0x8000 */
3568
+
#define GEN6_TD_CTL_FORCE_TD_BKPT (1<<4)
3569
+
3570
+
/* Port debugging
3571
+
*/
3572
+
3573
+
#define PORT_DBG 0x42308
3574
+
#define PORT_DBG_DRRS_HW_STATE_OFF (0<<30)
3575
+
#define PORT_DBG_DRRS_HW_STATE_LOW (1<<30)
3576
+
#define PORT_DBG_DRRS_HW_STATE_HIGH (2<<30)
3577
+
3578
+
/* RC6 residence counters
3579
+
*/
3580
+
#define RC6_RESIDENCY_TIME 0x138108
3581
+
#define RC6p_RESIDENCY_TIME 0x13810C
3582
+
#define RC6pp_RESIDENCY_TIME 0x138110
3583
+
3584
+
#define GEN6_RPNSWREQ 0xA008
3585
+
#define GEN6_RC_VIDEO_FREQ 0xA00C
3586
+
#define GEN6_RC_CONTROL 0xA090
3587
+
#define GEN6_RP_DOWN_TIMEOUT 0xA010
3588
+
#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3589
+
#define GEN6_RPSTAT1 0xA01C
3590
+
#define GEN6_RP_CONTROL 0xA024
3591
+
#define GEN6_RP_UP_THRESHOLD 0xA02C
3592
+
#define GEN6_RP_DOWN_THRESHOLD 0xA030
3593
+
#define GEN6_RP_CUR_UP_EI 0xA050
3594
+
#define GEN6_RP_CUR_UP 0xA054
3595
+
#define GEN6_RP_PREV_UP 0xA058
3596
+
#define GEN6_RP_CUR_DOWN_EI 0xA05C
3597
+
#define GEN6_RP_CUR_DOWN 0xA060
3598
+
#define GEN6_RP_PREV_DOWN 0xA064
3599
+
#define GEN6_RP_UP_EI 0xA068
3600
+
#define GEN6_RP_DOWN_EI 0xA06C
3601
+
#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3602
+
#define GEN6_RC_STATE 0xA094
3603
+
#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3604
+
#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3605
+
#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3606
+
#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3607
+
#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3608
+
#define GEN6_RC_SLEEP 0xA0B0
3609
+
#define GEN6_RC1e_THRESHOLD 0xA0B4
3610
+
#define GEN6_RC6_THRESHOLD 0xA0B8
3611
+
#define GEN6_RC6p_THRESHOLD 0xA0BC
3612
+
#define GEN6_RC6pp_THRESHOLD 0xA0C0
3613
+
#define GEN6_PMINTRMSK 0xA168
3614
+
#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3615
+
#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3616
+
#define GEN6_PMIER 0x4402C
3617
+
#define GEN6_PMIMR 0x44024 /* rps_lock */
3618
+
#define GEN6_PMINTRMSK 0xA168
3619
+
3620
+
/* Haswell-related items */
3621
+
3622
+
/* HSW Power Wells */
3623
+
#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
3624
+
#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
3625
+
#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
3626
+
#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
3627
+
#define HSW_PWR_WELL_ENABLE (1<<31)
3628
+
#define HSW_PWR_WELL_STATE (1<<30)
3629
+
#define HSW_PWR_WELL_CTL5 0x45410
3630
+
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
3631
+
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
3632
+
#define HSW_PWR_WELL_FORCE_ON (1<<19)
3633
+
#define HSW_PWR_WELL_CTL6 0x45414
3634
+
3635
+
/* Per-pipe DDI Function Control */
3636
+
#define PIPE_DDI_FUNC_CTL_A 0x60400
3637
+
#define PIPE_DDI_FUNC_CTL_B 0x61400
3638
+
#define PIPE_DDI_FUNC_CTL_C 0x62400
3639
+
#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
3640
+
#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
3641
+
PIPE_DDI_FUNC_CTL_A, \
3642
+
PIPE_DDI_FUNC_CTL_B)
3643
+
#define PIPE_DDI_FUNC_ENABLE (1<<31)
3644
+
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3645
+
#define PIPE_DDI_PORT_MASK (0xf<<28)
3646
+
#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
3647
+
#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
3648
+
#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
3649
+
#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
3650
+
#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
3651
+
#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
3652
+
#define PIPE_DDI_BPC_8 (0<<20)
3653
+
#define PIPE_DDI_BPC_10 (1<<20)
3654
+
#define PIPE_DDI_BPC_6 (2<<20)
3655
+
#define PIPE_DDI_BPC_12 (3<<20)
3656
+
#define PIPE_DDI_BFI_ENABLE (1<<4)
3657
+
#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
3658
+
#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
3659
+
#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
3660
+
3661
+
/* DisplayPort Transport Control */
3662
+
#define DP_TP_CTL_A 0x64040
3663
+
#define DP_TP_CTL_B 0x64140
3664
+
#define DP_TP_CTL_C 0x64240
3665
+
#define DP_TP_CTL_D 0x64340
3666
+
#define DP_TP_CTL_E 0x64440
3667
+
#define DP_TP_CTL_ENABLE (1<<31)
3668
+
#define DP_TP_CTL_MODE_SST (0<<27)
3669
+
#define DP_TP_CTL_MODE_MST (1<<27)
3670
+
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
3671
+
#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
3672
+
#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
3673
+
#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
3674
+
#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
3675
+
#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
3676
+
3677
+
/* DisplayPort Transport Status */
3678
+
#define DP_TP_STATUS_A 0x64044
3679
+
#define DP_TP_STATUS_B 0x64144
3680
+
#define DP_TP_STATUS_C 0x64244
3681
+
#define DP_TP_STATUS_D 0x64344
3682
+
#define DP_TP_STATUS_E 0x64444
3683
+
#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
3684
+
3685
+
/* DDI Buffer Control */
3686
+
#define DDI_BUF_CTL_A 0x64000
3687
+
#define DDI_BUF_CTL_B 0x64100
3688
+
#define DDI_BUF_CTL_C 0x64200
3689
+
#define DDI_BUF_CTL_D 0x64300
3690
+
#define DDI_BUF_CTL_E 0x64400
3691
+
#define DDI_BUF_CTL_ENABLE (1<<31)
3692
+
#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
3693
+
#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
3694
+
#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
3695
+
#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
3696
+
#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
3697
+
#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
3698
+
#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
3699
+
#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
3700
+
#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
3701
+
#define DDI_BUF_EMP_MASK (0xf<<24)
3702
+
#define DDI_BUF_IS_IDLE (1<<7)
3703
+
#define DDI_PORT_WIDTH_X1 (0<<1)
3704
+
#define DDI_PORT_WIDTH_X2 (1<<1)
3705
+
#define DDI_PORT_WIDTH_X4 (3<<1)
3706
+
#define DDI_INIT_DISPLAY_DETECTED (1<<0)
3707
+
3708
+
/* LPT PIXCLK_GATE */
3709
+
#define PIXCLK_GATE 0xC6020
3710
+
#define PIXCLK_GATE_UNGATE 1<<0
3711
+
#define PIXCLK_GATE_GATE 0<<0
3712
+
3713
+
/* SPLL */
3714
+
#define SPLL_CTL 0x46020
3715
+
#define SPLL_PLL_ENABLE (1<<31)
3716
+
#define SPLL_PLL_SCC (1<<28)
3717
+
#define SPLL_PLL_NON_SCC (2<<28)
3718
+
#define SPLL_PLL_FREQ_810MHz (0<<26)
3719
+
#define SPLL_PLL_FREQ_1350MHz (1<<26)
3720
+
3721
+
/* WRPLL */
3722
+
#define WRPLL_CTL1 0x46040
3723
+
#define WRPLL_CTL2 0x46060
3724
+
#define WRPLL_PLL_ENABLE (1<<31)
3725
+
#define WRPLL_PLL_SELECT_SSC (0x01<<28)
3726
+
#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
3727
+
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
3728
+
/* WRPLL divider programming */
3729
+
#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
3730
+
#define WRPLL_DIVIDER_POST(x) ((x)<<8)
3731
+
#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
3732
+
3733
+
/* Port clock selection */
3734
+
#define PORT_CLK_SEL_A 0x46100
3735
+
#define PORT_CLK_SEL_B 0x46104
3736
+
#define PORT_CLK_SEL_C 0x46108
3737
+
#define PORT_CLK_SEL_D 0x4610C
3738
+
#define PORT_CLK_SEL_E 0x46110
3739
+
#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
3740
+
#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
3741
+
#define PORT_CLK_SEL_LCPLL_810 (2<<29)
3742
+
#define PORT_CLK_SEL_SPLL (3<<29)
3743
+
#define PORT_CLK_SEL_WRPLL1 (4<<29)
3744
+
#define PORT_CLK_SEL_WRPLL2 (5<<29)
3745
+
3746
+
/* Pipe clock selection */
3747
+
#define PIPE_CLK_SEL_A 0x46140
3748
+
#define PIPE_CLK_SEL_B 0x46144
3749
+
#define PIPE_CLK_SEL_C 0x46148
3750
+
/* For each pipe, we need to select the corresponding port clock */
3751
+
#define PIPE_CLK_SEL_DISABLED (0x0<<29)
3752
+
#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
3753
+
3754
+
/* LCPLL Control */
3755
+
#define LCPLL_CTL 0x130040
3756
+
#define LCPLL_PLL_DISABLE (1<<31)
3757
+
#define LCPLL_PLL_LOCK (1<<30)
3758
+
#define LCPLL_CD_CLOCK_DISABLE (1<<25)
3759
+
#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
3760
+
3761
+
/* Pipe WM_LINETIME - watermark line time */
3762
+
#define WM_PIPE_A 0x45100
3763
+
#define WM_PIPE_B 0x45104
3764
+
#define WM_PIPE_C 0x45200
3765
+
#define WM_LP1 0x45108
3766
+
#define WM_LP2 0x4510C
3767
+
#define WM_LP3 0x45110
3768
+
#define WM_LP1_SPR 0x45120
3769
+
#define WM_LP2_SPR 0x45124
3770
+
#define WM_LP3_SPR 0x45128
3771
+
#define WM_MISC 0x45260
3772
+
#define WM_SR_CNT 0x45264
3773
+
#define WM_DBG 0x45280
3774
+
#define PIPE_WM_LINETIME_A 0x45270
3775
+
#define PIPE_WM_LINETIME_B 0x45274
3776
+
#define PIPE_WM_LINETIME_C 0x45278
3777
+
#define PIPE_WM_LINETIME_MASK (0x1ff)
3778
+
#define PIPE_WM_LINETIME_TIME(x) ((x))
3779
+
#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
3780
+
#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
3781
+
3782
+
/* SFUSE_STRAP */
3783
+
#define SFUSE_STRAP 0xc2014
3784
+
#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
3785
+
#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
3786
+
#define SFUSE_STRAP_DDID_DETECTED (1<<0)
3787
+
3788
+
/* Valleyview related items */
3789
+
3790
+
/* Valleyview DPIO registers */
3791
+
#define VLV_DISPLAY_BASE 0x180000
3792
+
#define DPIO_PKT 0x2100
3793
+
#define DPIO_RID (0 << 24)
3794
+
#define DPIO_OP_WRITE (1 << 16)
3795
+
#define DPIO_OP_READ (0 << 16)
3796
+
#define DPIO_PORTID (0x12 << 8)
3797
+
#define DPIO_BYTE (0xf << 4)
3798
+
#define DPIO_BUSY (1 << 0)
3799
+
#define DPIO_DATA 0x2104
3800
+
#define DPIO_REG 0x2108
3801
+
3802
+
/* VLV IOSF access */
3803
+
#define VLV_IOSF_DOORBELL_REQ 0x182100
3804
+
#define IOSF_DEVFN_SHIFT 24
3805
+
#define IOSF_OPCODE_SHIFT 16
3806
+
#define IOSF_PORT_SHIFT 8
3807
+
#define IOSF_BYTE_ENABLES_SHIFT 4
3808
+
#define IOSF_BAR_SHIFT 1
3809
+
#define IOSF_SB_BUSY (1<<0)
3810
+
#define IOSF_PORT_PUNIT 0x4
3811
+
#define IOSF_PORT_NC 0x11
3812
+
#define VLV_IOSF_DATA 0x182104
3813
+
#define VLV_IOSF_ADDR 0x182108
3814
+
3815
+
#define PUNIT_OPCODE_REG_READ 6
3816
+
#define PUNIT_OPCODE_REG_WRITE 7
3817
+
3818
+
#endif /* _I810_REG_H */
+179
intel_reg_map.c
+179
intel_reg_map.c
···
1
+
/*
2
+
* Copyright � 2011 Intel Corporation
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice (including the next
12
+
* paragraph) shall be included in all copies or substantial portions of the
13
+
* Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20
+
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21
+
* IN THE SOFTWARE.
22
+
*
23
+
* Authors:
24
+
* Ben Widawsky <ben@bwidawsk.net>
25
+
*
26
+
*/
27
+
28
+
#include <stdio.h>
29
+
#include <stdarg.h>
30
+
#include <stdlib.h>
31
+
#include <sys/types.h>
32
+
#include "intel_gpu_tools.h"
33
+
34
+
static struct intel_register_range gen_bwcl_register_map[] = {
35
+
{0x00000000, 0x00000fff, INTEL_RANGE_RW},
36
+
{0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
37
+
{0x00002000, 0x00000fff, INTEL_RANGE_RW},
38
+
{0x00003000, 0x000001ff, INTEL_RANGE_RW},
39
+
{0x00003200, 0x00000dff, INTEL_RANGE_RW},
40
+
{0x00004000, 0x000003ff, INTEL_RANGE_RSVD},
41
+
{0x00004400, 0x00000bff, INTEL_RANGE_RSVD},
42
+
{0x00005000, 0x00000fff, INTEL_RANGE_RW},
43
+
{0x00006000, 0x00000fff, INTEL_RANGE_RW},
44
+
{0x00007000, 0x000003ff, INTEL_RANGE_RW},
45
+
{0x00007400, 0x000014ff, INTEL_RANGE_RW},
46
+
{0x00008900, 0x000006ff, INTEL_RANGE_RSVD},
47
+
{0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
48
+
{0x0000a000, 0x00000fff, INTEL_RANGE_RW},
49
+
{0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
50
+
{0x00010000, 0x00003fff, INTEL_RANGE_RW},
51
+
{0x00014000, 0x0001bfff, INTEL_RANGE_RSVD},
52
+
{0x00030000, 0x0000ffff, INTEL_RANGE_RW},
53
+
{0x00040000, 0x0001ffff, INTEL_RANGE_RSVD},
54
+
{0x00060000, 0x0000ffff, INTEL_RANGE_RW},
55
+
{0x00070000, 0x00002fff, INTEL_RANGE_RW},
56
+
{0x00073000, 0x00000fff, INTEL_RANGE_RW},
57
+
{0x00074000, 0x0000bfff, INTEL_RANGE_RSVD},
58
+
{0x00000000, 0x00000000, INTEL_RANGE_END}
59
+
};
60
+
61
+
static struct intel_register_range gen4_register_map[] = {
62
+
{0x00000000, 0x00000fff, INTEL_RANGE_RW},
63
+
{0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
64
+
{0x00002000, 0x00000fff, INTEL_RANGE_RW},
65
+
{0x00003000, 0x000001ff, INTEL_RANGE_RW},
66
+
{0x00003200, 0x00000dff, INTEL_RANGE_RW},
67
+
{0x00004000, 0x000003ff, INTEL_RANGE_RW},
68
+
{0x00004400, 0x00000bff, INTEL_RANGE_RW},
69
+
{0x00005000, 0x00000fff, INTEL_RANGE_RW},
70
+
{0x00006000, 0x00000fff, INTEL_RANGE_RW},
71
+
{0x00007000, 0x000003ff, INTEL_RANGE_RW},
72
+
{0x00007400, 0x000014ff, INTEL_RANGE_RW},
73
+
{0x00008900, 0x000006ff, INTEL_RANGE_RSVD},
74
+
{0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
75
+
{0x0000a000, 0x00000fff, INTEL_RANGE_RW},
76
+
{0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
77
+
{0x00010000, 0x00003fff, INTEL_RANGE_RW},
78
+
{0x00014000, 0x0001bfff, INTEL_RANGE_RSVD},
79
+
{0x00030000, 0x0000ffff, INTEL_RANGE_RW},
80
+
{0x00040000, 0x0001ffff, INTEL_RANGE_RSVD},
81
+
{0x00060000, 0x0000ffff, INTEL_RANGE_RW},
82
+
{0x00070000, 0x00002fff, INTEL_RANGE_RW},
83
+
{0x00073000, 0x00000fff, INTEL_RANGE_RW},
84
+
{0x00074000, 0x0000bfff, INTEL_RANGE_RSVD},
85
+
{0x00000000, 0x00000000, INTEL_RANGE_END}
86
+
};
87
+
88
+
/* The documentation is a little sketchy on these register ranges. */
89
+
static struct intel_register_range gen6_gt_register_map[] = {
90
+
{0x00000000, 0x00000fff, INTEL_RANGE_RW},
91
+
{0x00001000, 0x00000fff, INTEL_RANGE_RSVD},
92
+
{0x00002000, 0x00000fff, INTEL_RANGE_RW},
93
+
{0x00003000, 0x000001ff, INTEL_RANGE_RW},
94
+
{0x00003200, 0x00000dff, INTEL_RANGE_RW},
95
+
{0x00004000, 0x00000fff, INTEL_RANGE_RW},
96
+
{0x00005000, 0x0000017f, INTEL_RANGE_RW},
97
+
{0x00005180, 0x00000e7f, INTEL_RANGE_RW},
98
+
{0x00006000, 0x00001fff, INTEL_RANGE_RW},
99
+
{0x00008000, 0x000007ff, INTEL_RANGE_RW},
100
+
{0x00008800, 0x000000ff, INTEL_RANGE_RSVD},
101
+
{0x00008900, 0x000006ff, INTEL_RANGE_RW},
102
+
{0x00009000, 0x00000fff, INTEL_RANGE_RSVD},
103
+
{0x0000a000, 0x00000fff, INTEL_RANGE_RW},
104
+
{0x0000b000, 0x00004fff, INTEL_RANGE_RSVD},
105
+
{0x00010000, 0x00001fff, INTEL_RANGE_RW},
106
+
{0x00012000, 0x000003ff, INTEL_RANGE_RW},
107
+
{0x00012400, 0x00000bff, INTEL_RANGE_RW},
108
+
{0x00013000, 0x00000fff, INTEL_RANGE_RW},
109
+
{0x00014000, 0x00000fff, INTEL_RANGE_RW},
110
+
{0x00015000, 0x0000cfff, INTEL_RANGE_RW},
111
+
{0x00022000, 0x00000fff, INTEL_RANGE_RW},
112
+
{0x00023000, 0x00000fff, INTEL_RANGE_RSVD},
113
+
{0x00024000, 0x00000fff, INTEL_RANGE_RW},
114
+
{0x00025000, 0x0000afff, INTEL_RANGE_RSVD},
115
+
{0x00030000, 0x0000ffff, INTEL_RANGE_RW},
116
+
{0x00040000, 0x0000ffff, INTEL_RANGE_RW},
117
+
{0x00050000, 0x0000ffff, INTEL_RANGE_RW},
118
+
{0x00060000, 0x0000ffff, INTEL_RANGE_RW},
119
+
{0x00070000, 0x00003fff, INTEL_RANGE_RW},
120
+
{0x00074000, 0x0008bfff, INTEL_RANGE_RSVD},
121
+
{0x00100000, 0x00007fff, INTEL_RANGE_RW},
122
+
{0x00108000, 0x00037fff, INTEL_RANGE_RSVD},
123
+
{0x00140000, 0x0003ffff, INTEL_RANGE_RW},
124
+
{0x00000000, 0x00000000, INTEL_RANGE_END}
125
+
};
126
+
127
+
struct intel_register_map
128
+
intel_get_register_map(uint32_t devid)
129
+
{
130
+
struct intel_register_map map;
131
+
const int gen = intel_gen(devid);
132
+
133
+
if (gen >= 6) {
134
+
map.map = gen6_gt_register_map;
135
+
map.top = 0x180000;
136
+
} else if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
137
+
map.map = gen_bwcl_register_map;
138
+
map.top = 0x80000;
139
+
} else if (gen >= 4) {
140
+
map.map = gen4_register_map;
141
+
map.top = 0x80000;
142
+
} else {
143
+
fprintf(stderr, "Gen2/3 Ranges are not supported. Please use "
144
+
"unsafe access.");
145
+
abort();
146
+
}
147
+
148
+
map.alignment_mask = 0x3;
149
+
150
+
return map;
151
+
}
152
+
153
+
struct intel_register_range *
154
+
intel_get_register_range(struct intel_register_map map, uint32_t offset, int mode)
155
+
{
156
+
struct intel_register_range *range = map.map;
157
+
uint32_t align = map.alignment_mask;
158
+
159
+
if (offset & map.alignment_mask)
160
+
return NULL;
161
+
162
+
if (offset >= map.top)
163
+
return NULL;
164
+
165
+
while (!(range->flags & INTEL_RANGE_END)) {
166
+
/* list is assumed to be in order */
167
+
if (offset < range->base)
168
+
break;
169
+
170
+
if ( (offset >= range->base) &&
171
+
(offset + align) <= (range->base + range->size)) {
172
+
if ((mode & range->flags) == mode)
173
+
return range;
174
+
}
175
+
range++;
176
+
}
177
+
178
+
return NULL;
179
+
}