Control intel backlight on FreeBSD (and OpenBSD)
openbsd

handle gen9 devices like gen8

works on the skylake hp chromebook 13

+75 -13
+2 -2
intel_backlight.c
··· 75 75 dev = intel_get_pci_device(); 76 76 intel_get_mmio(dev); 77 77 78 - if (IS_GEN8(dev->device_id)) /* broadwell */ 78 + if (IS_GEN8(dev->device_id) || IS_GEN9(dev->device_id)) /* bdw/skl */ 79 79 current = reg_read(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; 80 80 else 81 81 current = reg_read(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; ··· 106 106 else if (v > max) 107 107 v = max; 108 108 109 - if (IS_GEN8(dev->device_id)) { 109 + if (IS_GEN8(dev->device_id) || IS_GEN9(dev->device_id)) { 110 110 reg_write(BLC_PWM_PCH_CTL2, 111 111 (reg_read(BLC_PWM_PCH_CTL2) &~ 112 112 BACKLIGHT_DUTY_CYCLE_MASK) | v);
+73 -11
intel_chipset.h
··· 177 177 #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E 178 178 #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 179 179 #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 180 + #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 180 181 #define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B 181 182 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B 182 183 #define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B 184 + #define PCI_CHIP_SKYLAKE_HALO_GT4 0x193B 183 185 #define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A 184 186 #define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A 185 187 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A 188 + #define PCI_CHIP_SKYLAKE_SRV_GT4 0x193A 186 189 #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D 190 + #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D 191 + 192 + #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 193 + #define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 194 + #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 195 + #define PCI_CHIP_KABYLAKE_ULT_GT3 0x5926 196 + #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 197 + #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 198 + #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E 199 + #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E 200 + #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 201 + #define PCI_CHIP_KABYLAKE_DT_GT1_5 0x5917 202 + #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 203 + #define PCI_CHIP_KABYLAKE_DT_GT4 0x5932 204 + #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B 205 + #define PCI_CHIP_KABYLAKE_HALO_GT3 0x592B 206 + #define PCI_CHIP_KABYLAKE_HALO_GT1 0x590B 207 + #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B 208 + #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A 209 + #define PCI_CHIP_KABYLAKE_SRV_GT3 0x592A 210 + #define PCI_CHIP_KABYLAKE_SRV_GT4 0x593A 211 + #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A 212 + #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D 213 + #define PCI_CHIP_KABYLAKE_WKS_GT4 0x593D 187 214 188 215 #define PCI_CHIP_BROXTON_0 0x0A84 189 216 #define PCI_CHIP_BROXTON_1 0x1A84 190 217 #define PCI_CHIP_BROXTON_2 0x5A84 218 + #define PCI_CHIP_BROXTON_3 0x1A85 219 + #define PCI_CHIP_BROXTON_4 0x5A85 191 220 192 221 #endif /* __GTK_DOC_IGNORE__ */ 193 222 ··· 369 398 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ 370 399 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) 371 400 401 + #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ 402 + (devid) == PCI_CHIP_SKYLAKE_HALO_GT4 || \ 403 + (devid) == PCI_CHIP_SKYLAKE_WKS_GT4 || \ 404 + (devid) == PCI_CHIP_SKYLAKE_SRV_GT4) 405 + 406 + #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \ 407 + (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \ 408 + (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \ 409 + (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \ 410 + (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \ 411 + (devid) == PCI_CHIP_KABYLAKE_DT_GT1|| \ 412 + (devid) == PCI_CHIP_KABYLAKE_HALO_GT1|| \ 413 + (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) 414 + 415 + #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \ 416 + (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \ 417 + (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \ 418 + (devid) == PCI_CHIP_KABYLAKE_DT_GT2|| \ 419 + (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \ 420 + (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \ 421 + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) 422 + 423 + #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3|| \ 424 + (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \ 425 + (devid) == PCI_CHIP_KABYLAKE_SRV_GT3) 426 + 427 + #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \ 428 + (devid) == PCI_CHIP_KABYLAKE_HALO_GT4|| \ 429 + (devid) == PCI_CHIP_KABYLAKE_SRV_GT4|| \ 430 + (devid) == PCI_CHIP_KABYLAKE_WKS_GT4) 431 + 432 + #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ 433 + IS_KBL_GT2(devid) || \ 434 + IS_KBL_GT3(devid) || \ 435 + IS_KBL_GT4(devid)) 436 + 372 437 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ 373 438 IS_SKL_GT2(devid) || \ 374 - IS_SKL_GT3(devid)) 439 + IS_SKL_GT3(devid) || \ 440 + IS_SKL_GT4(devid)) 375 441 376 442 #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ 377 443 (devid) == PCI_CHIP_BROXTON_1 || \ 378 - (devid) == PCI_CHIP_BROXTON_2) 444 + (devid) == PCI_CHIP_BROXTON_2 || \ 445 + (devid) == PCI_CHIP_BROXTON_3 || \ 446 + (devid) == PCI_CHIP_BROXTON_4) 379 447 380 - #define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid)) 448 + #define IS_GEN9(devid) (IS_KABYLAKE(devid) || \ 449 + IS_SKYLAKE(devid) || \ 450 + IS_BROXTON(devid)) 381 451 382 452 #define IS_965(devid) (IS_GEN4(devid) || \ 383 - IS_GEN5(devid) || \ 384 - IS_GEN6(devid) || \ 385 - IS_GEN7(devid) || \ 386 - IS_GEN8(devid) || \ 387 - IS_GEN9(devid)) 388 - 389 - #define IS_9XX(devid) (IS_GEN3(devid) || \ 390 - IS_GEN4(devid) || \ 391 453 IS_GEN5(devid) || \ 392 454 IS_GEN6(devid) || \ 393 455 IS_GEN7(devid) || \