intel_chipset.h at master · jcs.org/intel_backlight

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Control intel backlight on FreeBSD (and OpenBSD)
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intel_backlight_fbsd / intel_chipset.h
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  1/*
  2 * Copyright © 2007 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Eric Anholt <eric@anholt.net>
 25 *
 26 */
 27
 28#ifndef _INTEL_CHIPSET_H
 29#define _INTEL_CHIPSET_H
 30
 31/* Exclude chipset #defines, they just add noise */
 32#ifndef __GTK_DOC_IGNORE__
 33
 34#define PCI_CHIP_I810			0x7121
 35#define PCI_CHIP_I810_DC100		0x7123
 36#define PCI_CHIP_I810_E			0x7125
 37#define PCI_CHIP_I815			0x1132
 38
 39#define PCI_CHIP_I830_M			0x3577
 40#define PCI_CHIP_845_G			0x2562
 41#define PCI_CHIP_I854_G			0x358e
 42#define PCI_CHIP_I855_GM		0x3582
 43#define PCI_CHIP_I865_G			0x2572
 44
 45#define PCI_CHIP_I915_G			0x2582
 46#define PCI_CHIP_E7221_G		0x258A
 47#define PCI_CHIP_I915_GM		0x2592
 48#define PCI_CHIP_I945_G			0x2772
 49#define PCI_CHIP_I945_GM		0x27A2
 50#define PCI_CHIP_I945_GME		0x27AE
 51
 52#define PCI_CHIP_Q35_G			0x29B2
 53#define PCI_CHIP_G33_G			0x29C2
 54#define PCI_CHIP_Q33_G			0x29D2
 55
 56#define PCI_CHIP_IGD_GM			0xA011
 57#define PCI_CHIP_IGD_G			0xA001
 58
 59#define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)
 60#define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)
 61#define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))
 62
 63#define PCI_CHIP_I965_G			0x29A2
 64#define PCI_CHIP_I965_Q			0x2992
 65#define PCI_CHIP_I965_G_1		0x2982
 66#define PCI_CHIP_I946_GZ		0x2972
 67#define PCI_CHIP_I965_GM		0x2A02
 68#define PCI_CHIP_I965_GME		0x2A12
 69
 70#define PCI_CHIP_GM45_GM		0x2A42
 71
 72#define PCI_CHIP_IGD_E_G		0x2E02
 73#define PCI_CHIP_Q45_G			0x2E12
 74#define PCI_CHIP_G45_G			0x2E22
 75#define PCI_CHIP_G41_G			0x2E32
 76
 77#define PCI_CHIP_ILD_G			0x0042
 78#define PCI_CHIP_ILM_G			0x0046
 79
 80#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
 81#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
 82#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
 83#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
 84#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
 85#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
 86#define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
 87
 88#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
 89#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
 90#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
 91#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
 92#define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
 93#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
 94
 95#define PCI_CHIP_HASWELL_GT1		0x0402 /* Desktop */
 96#define PCI_CHIP_HASWELL_GT2		0x0412
 97#define PCI_CHIP_HASWELL_GT3		0x0422
 98#define PCI_CHIP_HASWELL_M_GT1		0x0406 /* Mobile */
 99#define PCI_CHIP_HASWELL_M_GT2		0x0416
100#define PCI_CHIP_HASWELL_M_GT3		0x0426
101#define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
102#define PCI_CHIP_HASWELL_S_GT2		0x041A
103#define PCI_CHIP_HASWELL_S_GT3		0x042A
104#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
105#define PCI_CHIP_HASWELL_B_GT2		0x041B
106#define PCI_CHIP_HASWELL_B_GT3		0x042B
107#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
108#define PCI_CHIP_HASWELL_E_GT2		0x041E
109#define PCI_CHIP_HASWELL_E_GT3		0x042E
110#define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
111#define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
112#define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
113#define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06 /* Mobile */
114#define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
115#define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
116#define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
117#define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
118#define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
119#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
120#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
121#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
122#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
123#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
124#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
125#define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
126#define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
127#define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
128#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06 /* Mobile */
129#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
130#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
131#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
132#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
133#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
134#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
135#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
136#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
137#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
138#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
139#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
140#define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
141#define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
142#define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
143#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
144#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
145#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
146#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
147#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
148#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
149#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
150#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
151#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
152#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
153#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
154#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
155#define BDW_SPARE 0x2
156#define BDW_ULT 0x6
157#define BDW_HALO 0xb
158#define BDW_SERVER 0xa
159#define BDW_WORKSTATION 0xd
160#define BDW_ULX 0xe
161
162#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
163#define PCI_CHIP_VALLEYVIEW_1		0x0f31
164#define PCI_CHIP_VALLEYVIEW_2		0x0f32
165#define PCI_CHIP_VALLEYVIEW_3		0x0f33
166
167#define PCI_CHIP_CHERRYVIEW_0		0x22b0
168#define PCI_CHIP_CHERRYVIEW_1		0x22b1
169#define PCI_CHIP_CHERRYVIEW_2		0x22b2
170#define PCI_CHIP_CHERRYVIEW_3		0x22b3
171
172#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
173#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
174#define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
175#define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
176#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
177#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
178#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
179#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
180#define PCI_CHIP_SKYLAKE_DT_GT4		0x1932
181#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
182#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
183#define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
184#define PCI_CHIP_SKYLAKE_HALO_GT4 	0x193B
185#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
186#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
187#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
188#define PCI_CHIP_SKYLAKE_SRV_GT4	0x193A
189#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
190#define PCI_CHIP_SKYLAKE_WKS_GT4 	0x193D
191
192#define PCI_CHIP_KABYLAKE_ULT_GT2      0x5916
193#define PCI_CHIP_KABYLAKE_ULT_GT1_5    0x5913
194#define PCI_CHIP_KABYLAKE_ULT_GT1      0x5906
195#define PCI_CHIP_KABYLAKE_ULT_GT3      0x5926
196#define PCI_CHIP_KABYLAKE_ULT_GT2F     0x5921
197#define PCI_CHIP_KABYLAKE_ULX_GT1_5    0x5915
198#define PCI_CHIP_KABYLAKE_ULX_GT1      0x590E
199#define PCI_CHIP_KABYLAKE_ULX_GT2      0x591E
200#define PCI_CHIP_KABYLAKE_DT_GT2       0x5912
201#define PCI_CHIP_KABYLAKE_DT_GT1_5     0x5917
202#define PCI_CHIP_KABYLAKE_DT_GT1       0x5902
203#define PCI_CHIP_KABYLAKE_DT_GT4       0x5932
204#define PCI_CHIP_KABYLAKE_HALO_GT2     0x591B
205#define PCI_CHIP_KABYLAKE_HALO_GT3     0x592B
206#define PCI_CHIP_KABYLAKE_HALO_GT1     0x590B
207#define PCI_CHIP_KABYLAKE_HALO_GT4     0x593B
208#define PCI_CHIP_KABYLAKE_SRV_GT2      0x591A
209#define PCI_CHIP_KABYLAKE_SRV_GT3      0x592A
210#define PCI_CHIP_KABYLAKE_SRV_GT4      0x593A
211#define PCI_CHIP_KABYLAKE_SRV_GT1      0x590A
212#define PCI_CHIP_KABYLAKE_WKS_GT2      0x591D
213#define PCI_CHIP_KABYLAKE_WKS_GT4      0x593D
214
215#define PCI_CHIP_BROXTON_0		0x0A84
216#define PCI_CHIP_BROXTON_1		0x1A84
217#define PCI_CHIP_BROXTON_2		0x5A84
218#define PCI_CHIP_BROXTON_3		0x1A85
219#define PCI_CHIP_BROXTON_4		0x5A85
220
221#endif /* __GTK_DOC_IGNORE__ */
222
223#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
224				 (devid) == PCI_CHIP_I915_GM || \
225				 (devid) == PCI_CHIP_I945_GM || \
226				 (devid) == PCI_CHIP_I945_GME || \
227				 (devid) == PCI_CHIP_I965_GM || \
228				 (devid) == PCI_CHIP_I965_GME || \
229				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
230				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
231				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
232
233#define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
234				 (devid) == PCI_CHIP_Q45_G || \
235				 (devid) == PCI_CHIP_G45_G || \
236				 (devid) == PCI_CHIP_G41_G)
237#define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)
238#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
239
240#define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
241#define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
242
243#define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
244				 (devid) == PCI_CHIP_E7221_G || \
245				 (devid) == PCI_CHIP_I915_GM)
246
247#define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
248				 (devid) == PCI_CHIP_I945_GME)
249
250#define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
251				 (devid) == PCI_CHIP_I945_GM || \
252				 (devid) == PCI_CHIP_I945_GME || \
253				 IS_G33(devid))
254
255#define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
256				 (devid) == PCI_CHIP_Q33_G || \
257				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
258
259#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
260				 (devid) == PCI_CHIP_845_G || \
261				 (devid) == PCI_CHIP_I854_G || \
262				 (devid) == PCI_CHIP_I855_GM || \
263				 (devid) == PCI_CHIP_I865_G)
264
265#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
266
267#define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
268				 (devid) == PCI_CHIP_I965_Q || \
269				 (devid) == PCI_CHIP_I965_G_1 || \
270				 (devid) == PCI_CHIP_I965_GM || \
271				 (devid) == PCI_CHIP_I965_GME || \
272				 (devid) == PCI_CHIP_I946_GZ || \
273				 IS_G4X(devid))
274
275#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
276
277#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
278				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
279				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
280				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
281				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
282				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
283				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
284
285#define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
286				 IS_HASWELL(devid) || \
287				 IS_VALLEYVIEW(devid))
288
289#define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
290				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
291				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
292				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
293				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
294				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
295
296#define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
297				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
298				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
299				 (devid) == PCI_CHIP_VALLEYVIEW_3)
300
301#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
302				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
303				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
304				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
305				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
306				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
307				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
308				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
309				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
310				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
311				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
312				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
313				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
314				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
315				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
316				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
317				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
318				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
319				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
320				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
321#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
322				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
323				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
324				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
325				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
326				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
327				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
328				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
329				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
330				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
331				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
332				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
333				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
334				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
335				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
336				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
337				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
338				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
339				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
340				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
341#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
342				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
343				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
344				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
345				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
346				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
347				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
348				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
349				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
350				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
351				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
352				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
353				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
354				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
355				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
356				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
357				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
358				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
359				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
360				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
361
362#define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
363				 IS_HSW_GT2(devid) || \
364				 IS_HSW_GT3(devid))
365
366#define IS_BROADWELL(devid)	((((devid) & 0xff00) != 0x1600) ? 0 : \
367				((((devid) & 0x00f0) >> 4) > 3) ? 0 : \
368				 (((devid) & 0x000f) == BDW_SPARE) ? 1 : \
369				 (((devid) & 0x000f) == BDW_ULT) ? 1 : \
370				 (((devid) & 0x000f) == BDW_HALO) ? 1 : \
371				 (((devid) & 0x000f) == BDW_SERVER) ? 1 : \
372				 (((devid) & 0x000f) == BDW_WORKSTATION) ? 1 : \
373				 (((devid) & 0x000f) == BDW_ULX) ? 1 : 0)
374
375#define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \
376				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
377				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
378				 (devid) == PCI_CHIP_CHERRYVIEW_3)
379
380#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
381				 IS_CHERRYVIEW(devid))
382
383#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
384				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
385				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
386				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
387				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
388
389#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
390				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
391				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
392				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
393				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
394				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
395				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
396
397#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
398				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
399				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
400
401#define IS_SKL_GT4(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT4	|| \
402				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT4	|| \
403				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4	|| \
404				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4)
405
406#define IS_KBL_GT1(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \
407				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \
408				 (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \
409				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \
410				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \
411				 (devid) == PCI_CHIP_KABYLAKE_DT_GT1||	\
412				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1|| \
413				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
414
415#define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \
416				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \
417				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \
418				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2||	\
419				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \
420				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \
421				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
422
423#define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3|| \
424				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT3|| \
425				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT3)
426
427#define IS_KBL_GT4(devid)	((devid) == PCI_CHIP_KABYLAKE_DT_GT4|| \
428				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT4|| \
429				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT4|| \
430				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT4)
431
432#define IS_KABYLAKE(devid)	(IS_KBL_GT1(devid) || \
433 				 IS_KBL_GT2(devid) || \
434 				 IS_KBL_GT3(devid) || \
435 				 IS_KBL_GT4(devid))
436
437#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
438				 IS_SKL_GT2(devid) || \
439				 IS_SKL_GT3(devid) || \
440				 IS_SKL_GT4(devid))
441
442#define IS_BROXTON(devid)	((devid) == PCI_CHIP_BROXTON_0 || \
443				 (devid) == PCI_CHIP_BROXTON_1 || \
444				 (devid) == PCI_CHIP_BROXTON_2 || \
445				 (devid) == PCI_CHIP_BROXTON_3 || \
446				 (devid) == PCI_CHIP_BROXTON_4)
447
448#define IS_GEN9(devid)		(IS_KABYLAKE(devid) || \
449				 IS_SKYLAKE(devid) || \
450				 IS_BROXTON(devid))
451
452#define IS_965(devid)		(IS_GEN4(devid) || \
453				 IS_GEN5(devid) || \
454				 IS_GEN6(devid) || \
455				 IS_GEN7(devid) || \
456				 IS_GEN8(devid) || \
457				 IS_GEN9(devid))
458
459#define IS_INTEL(devid)		(IS_GEN2(devid) || \
460				 IS_GEN3(devid) || \
461				 IS_GEN4(devid) || \
462				 IS_GEN5(devid) || \
463				 IS_GEN6(devid) || \
464				 IS_GEN7(devid) || \
465				 IS_GEN8(devid) || \
466				 IS_GEN9(devid))
467
468#define HAS_PCH_SPLIT(devid)	(IS_GEN5(devid) || \
469				 IS_GEN6(devid) || \
470				 IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
471				 IS_BROADWELL(devid) || \
472				 IS_SKYLAKE(devid))
473
474#define HAS_BLT_RING(devid)	(IS_GEN6(devid) || \
475				 IS_GEN7(devid) || \
476				 IS_GEN8(devid) || \
477				 IS_GEN9(devid))
478
479#define HAS_BSD_RING(devid)	(IS_GEN5(devid) || \
480				 IS_GEN6(devid) || \
481				 IS_GEN7(devid) || \
482				 IS_GEN8(devid) || \
483				 IS_GEN9(devid))
484
485#define IS_BROADWATER(devid)	((devid) == PCI_CHIP_I946_GZ || \
486				 (devid) == PCI_CHIP_I965_G_1 || \
487				 (devid) == PCI_CHIP_I965_Q || \
488				 (devid) == PCI_CHIP_I965_G)
489
490#define IS_CRESTLINE(devid)	((devid) == PCI_CHIP_I965_GM || \
491				 (devid) == PCI_CHIP_I965_GME)
492
493#define HAS_VEBOX_RING(devid)   (IS_HASWELL(devid))
494
495#endif /* _INTEL_CHIPSET_H */