- Add XNOR to 2-input and 3-input allowed gates
- Add 4-input gate synthesis (AND4, OR4, XOR4, XNOR4, NAND4, NOR4)
- Add _try_general_synthesis() for mixed 2/3/4-input gates
- Add parallel search scripts for optimal circuit finding

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

- Add exact_synthesis_mixed() for circuits with both 2-input and 3-input gates
- Add function restriction to limit to real gates (AND, OR, XOR, NAND, NOR)
- Add _decompose_gate_function() for cleaner DOT visualization
- Found 23-input solution: 7x2-input + 3x3-input gates
- Uses: XOR, OR, AND, NAND, OR3, XOR3
- Ties the 23-input record using only standard purchasable gates

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

- Fix segment c truth table (was wrong for digits 2, 3)
- Fix segment f truth table (was wrong for digit 7)
- Fix gate function encoding (bit ordering was inverted)
- Add Verilog, C, and DOT export functions for exact synthesis
- Update CLI to use appropriate export based on result type
- Add exported 12-gate circuit files (verified correct for 0-9)

The corrected truth tables require 12 gates minimum (24 inputs)
compared to 11 gates with the buggy tables.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Adds bcd_optimization/multi_level.py with:
- Gate and Circuit dataclasses for multi-level representation
- Support for arbitrary gate types (AND, OR, NAND, NOR, XOR, XNOR)
- Support for multi-input gates (3+)
- Circuit verification against truth tables
- Optimized synthesis using verified SOP expressions

Results comparison:
SOP (2-input gates): 52 total gate inputs
Multi-level (2-input): 22 total gate inputs (11 gates) <- BEST
Multi-input SOP: 52 total gate inputs (same structure)

The 2-input exact synthesis wins because it uses XOR/XNOR to exploit
segment relationships (a≈d, c≈f, d≈g differ by only 1-2 minterms).

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

- Total cost = AND gate inputs + OR gate inputs
- MaxSAT now optimizes for total cost, not just AND inputs
- Updated default target to 61 (no-sharing baseline)

Results:
No sharing: 61 total (33 AND + 28 OR)
Optimized: 52 total (15 AND + 37 OR)
Savings: 9 gate inputs (15% reduction)

Sharing reduces AND inputs dramatically (33→15) but increases
OR inputs (28→37) since shared terms fan out to more outputs.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

- Single-literal terms (A, B, B', etc.) don't need AND gates - they're
direct wires from inputs to OR gates, cost = 0 AND inputs
- Multi-literal terms still need AND gates with literal count inputs
- Added CostBreakdown showing AND inputs, OR inputs, and totals
- Updated MaxSAT penalty to only count multi-literal terms
- DOT export now shows single-literal terms as direct wires, not AND gates

New cost breakdown for optimized result:
AND gate inputs: 15 (7 gates)
OR gate inputs: 38 (7 gates)
Total: 53 gate inputs

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Input complements (A', B', C', D') are now shown as separate input
nodes rather than through inverter gates, since they're available
for free in the target technology.

- True inputs shown in light blue
- Complement inputs shown in light cyan
- No NOT gates in the diagram

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Adds --format dot option to export circuits as Graphviz DOT files.
Render with: dot -Tpng circuit.dot -o circuit.png

The diagram shows:
- Input nodes (A, B, C, D)
- Inverters for negated signals
- Shared AND gates (product terms) with labels
- OR gates for each segment output
- Output nodes (a-g)

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Implements a multi-output logic synthesis solver that achieves 19 gate
inputs, beating the 23-input baseline by exploiting shared product terms
across the 7 segment outputs.

Features:
- Pure Python Quine-McCluskey with multi-output tagging
- MaxSAT optimization (PySAT RC2) for minimum-cost covering
- SAT-based exact synthesis for provably optimal circuits
- Export to Verilog, C code, and Boolean equations
- Result verification against truth tables

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>