+42

.gitignore

··· 1 1 + # Python 2 2 + __pycache__/ 3 3 + *.py[cod] 4 4 + *$py.class 5 5 + *.so 6 6 + .Python 7 7 + build/ 8 8 + develop-eggs/ 9 9 + dist/ 10 10 + downloads/ 11 11 + eggs/ 12 12 + .eggs/ 13 13 + lib/ 14 14 + lib64/ 15 15 + parts/ 16 16 + sdist/ 17 17 + var/ 18 18 + wheels/ 19 19 + *.egg-info/ 20 20 + .installed.cfg 21 21 + *.egg 22 22 + 23 23 + # Virtual environments 24 24 + .venv/ 25 25 + venv/ 26 26 + ENV/ 27 27 + 28 28 + # IDE 29 29 + .idea/ 30 30 + .vscode/ 31 31 + *.swp 32 32 + *.swo 33 33 + *~ 34 34 + 35 35 + # Testing 36 36 + .pytest_cache/ 37 37 + .coverage 38 38 + htmlcov/ 39 39 + 40 40 + # OS 41 41 + .DS_Store 42 42 + Thumbs.db

+23

bcd_optimization/__init__.py

··· 1 1 + """BCD to 7-segment decoder optimization using SAT-based exact synthesis.""" 2 2 + 3 3 + from .solver import BCDTo7SegmentSolver, SynthesisResult 4 4 + from .truth_tables import SEGMENT_TRUTH_TABLES, SEGMENT_NAMES, SEGMENT_MINTERMS 5 5 + from .quine_mccluskey import Implicant, quine_mccluskey, quine_mccluskey_multi_output 6 6 + from .export import to_verilog, to_c_code, to_equations 7 7 + from .verify import verify_result 8 8 + 9 9 + __all__ = [ 10 10 + "BCDTo7SegmentSolver", 11 11 + "SynthesisResult", 12 12 + "SEGMENT_TRUTH_TABLES", 13 13 + "SEGMENT_NAMES", 14 14 + "SEGMENT_MINTERMS", 15 15 + "Implicant", 16 16 + "quine_mccluskey", 17 17 + "quine_mccluskey_multi_output", 18 18 + "to_verilog", 19 19 + "to_c_code", 20 20 + "to_equations", 21 21 + "verify_result", 22 22 + ] 23 23 + __version__ = "0.1.0"

+112

bcd_optimization/cli.py

··· 1 1 + """Command-line interface for BCD to 7-segment optimization.""" 2 2 + 3 3 + import argparse 4 4 + import sys 5 5 + 6 6 + from .solver import BCDTo7SegmentSolver 7 7 + from .truth_tables import print_truth_table 8 8 + from .export import to_verilog, to_c_code, to_equations 9 9 + 10 10 + 11 11 + def main(): 12 12 + parser = argparse.ArgumentParser( 13 13 + description="Optimize BCD to 7-segment decoder gate inputs", 14 14 + formatter_class=argparse.RawDescriptionHelpFormatter, 15 15 + epilog=""" 16 16 + Examples: 17 17 + bcd-optimize Run with default settings 18 18 + bcd-optimize --target 20 Try to beat 20 gate inputs 19 19 + bcd-optimize --exact Use SAT-based exact synthesis 20 20 + bcd-optimize --truth-table Show the BCD truth table 21 21 + bcd-optimize --format verilog Output as Verilog module 22 22 + bcd-optimize --format c Output as C function 23 23 + """, 24 24 + ) 25 25 + 26 26 + parser.add_argument( 27 27 + "--target", 28 28 + type=int, 29 29 + default=23, 30 30 + help="Target gate input count to beat (default: 23)", 31 31 + ) 32 32 + parser.add_argument( 33 33 + "--exact", 34 34 + action="store_true", 35 35 + help="Use SAT-based exact synthesis (slower but optimal)", 36 36 + ) 37 37 + parser.add_argument( 38 38 + "--truth-table", 39 39 + action="store_true", 40 40 + help="Print the BCD to 7-segment truth table and exit", 41 41 + ) 42 42 + parser.add_argument( 43 43 + "--format", "-f", 44 44 + choices=["text", "verilog", "c", "equations"], 45 45 + default="text", 46 46 + help="Output format (default: text)", 47 47 + ) 48 48 + parser.add_argument( 49 49 + "--verbose", "-v", 50 50 + action="store_true", 51 51 + help="Verbose output", 52 52 + ) 53 53 + 54 54 + args = parser.parse_args() 55 55 + 56 56 + if args.truth_table: 57 57 + print_truth_table() 58 58 + return 0 59 59 + 60 60 + # Suppress progress output for non-text formats 61 61 + quiet = args.format != "text" 62 62 + 63 63 + if not quiet: 64 64 + print("BCD to 7-Segment Decoder Optimizer") 65 65 + print("=" * 40) 66 66 + print(f"Target: < {args.target} gate inputs") 67 67 + print() 68 68 + 69 69 + solver = BCDTo7SegmentSolver() 70 70 + 71 71 + try: 72 72 + # Temporarily redirect stdout for quiet mode 73 73 + if quiet: 74 74 + import io 75 75 + old_stdout = sys.stdout 76 76 + sys.stdout = io.StringIO() 77 77 + 78 78 + result = solver.solve(target_cost=args.target, use_exact=args.exact) 79 79 + 80 80 + if quiet: 81 81 + sys.stdout = old_stdout 82 82 + 83 83 + # Output in requested format 84 84 + if args.format == "verilog": 85 85 + print(to_verilog(result)) 86 86 + elif args.format == "c": 87 87 + print(to_c_code(result)) 88 88 + elif args.format == "equations": 89 89 + print(to_equations(result)) 90 90 + else: 91 91 + print() 92 92 + solver.print_result(result) 93 93 + 94 94 + if result.cost < args.target: 95 95 + print(f"\n✓ SUCCESS: Beat target by {args.target - result.cost} gate inputs!") 96 96 + else: 97 97 + print(f"\n✗ Did not beat target (need {result.cost - args.target + 1} more reduction)") 98 98 + 99 99 + return 0 if result.cost < args.target else 1 100 100 + 101 101 + except Exception as e: 102 102 + if quiet: 103 103 + sys.stdout = old_stdout 104 104 + print(f"Error: {e}", file=sys.stderr) 105 105 + if args.verbose: 106 106 + import traceback 107 107 + traceback.print_exc() 108 108 + return 1 109 109 + 110 110 + 111 111 + if __name__ == "__main__": 112 112 + sys.exit(main())

+237

bcd_optimization/export.py

··· 1 1 + """ 2 2 + Export synthesized circuits to various formats (Verilog, VHDL, etc). 3 3 + """ 4 4 + 5 5 + from .solver import SynthesisResult 6 6 + from .truth_tables import SEGMENT_NAMES 7 7 + from .quine_mccluskey import Implicant 8 8 + 9 9 + 10 10 + def to_verilog(result: SynthesisResult, module_name: str = "bcd_to_7seg") -> str: 11 11 + """ 12 12 + Export synthesis result to Verilog. 13 13 + 14 14 + Args: 15 15 + result: The synthesis result 16 16 + module_name: Name for the Verilog module 17 17 + 18 18 + Returns: 19 19 + Verilog source code as string 20 20 + """ 21 21 + lines = [] 22 22 + lines.append(f"// BCD to 7-segment decoder") 23 23 + lines.append(f"// Synthesized with {result.cost} gate inputs using {result.method}") 24 24 + lines.append(f"// Shared terms: {len(result.shared_implicants)}") 25 25 + lines.append("") 26 26 + lines.append(f"module {module_name} (") 27 27 + lines.append(" input wire [3:0] bcd, // BCD input (0-9 valid)") 28 28 + lines.append(" output wire [6:0] seg // 7-segment output (a=seg[6], g=seg[0])") 29 29 + lines.append(");") 30 30 + lines.append("") 31 31 + lines.append(" // Input aliases") 32 32 + lines.append(" wire A = bcd[3];") 33 33 + lines.append(" wire B = bcd[2];") 34 34 + lines.append(" wire C = bcd[1];") 35 35 + lines.append(" wire D = bcd[0];") 36 36 + lines.append("") 37 37 + 38 38 + # Generate wire declarations for shared terms 39 39 + if result.shared_implicants: 40 40 + lines.append(" // Shared product terms") 41 41 + for i, (impl, outputs) in enumerate(result.shared_implicants): 42 42 + term_name = f"term_{i}" 43 43 + expr = impl_to_verilog(impl) 44 44 + lines.append(f" wire {term_name} = {expr}; // used by {', '.join(outputs)}") 45 45 + lines.append("") 46 46 + 47 47 + # Generate output assignments 48 48 + lines.append(" // Segment outputs") 49 49 + for i, segment in enumerate(SEGMENT_NAMES): 50 50 + if segment in result.implicants_by_output: 51 51 + terms = [] 52 52 + for impl in result.implicants_by_output[segment]: 53 53 + # Check if this is a shared term 54 54 + shared_idx = None 55 55 + for j, (shared_impl, _) in enumerate(result.shared_implicants): 56 56 + if impl == shared_impl: 57 57 + shared_idx = j 58 58 + break 59 59 + 60 60 + if shared_idx is not None: 61 61 + terms.append(f"term_{shared_idx}") 62 62 + else: 63 63 + terms.append(impl_to_verilog(impl)) 64 64 + 65 65 + expr = " | ".join(terms) if terms else "1'b0" 66 66 + seg_idx = 6 - i # a=seg[6], b=seg[5], ..., g=seg[0] 67 67 + lines.append(f" assign seg[{seg_idx}] = {expr}; // {segment}") 68 68 + 69 69 + lines.append("") 70 70 + lines.append("endmodule") 71 71 + 72 72 + return "\n".join(lines) 73 73 + 74 74 + 75 75 + def impl_to_verilog(impl: Implicant) -> str: 76 76 + """Convert an implicant to a Verilog expression.""" 77 77 + var_names = ['A', 'B', 'C', 'D'] 78 78 + terms = [] 79 79 + 80 80 + for i in range(4): 81 81 + bit = 1 << (3 - i) 82 82 + if impl.mask & bit: 83 83 + if (impl.value >> (3 - i)) & 1: 84 84 + terms.append(var_names[i]) 85 85 + else: 86 86 + terms.append(f"~{var_names[i]}") 87 87 + 88 88 + if not terms: 89 89 + return "1'b1" 90 90 + elif len(terms) == 1: 91 91 + return terms[0] 92 92 + else: 93 93 + return "(" + " & ".join(terms) + ")" 94 94 + 95 95 + 96 96 + def to_equations(result: SynthesisResult) -> str: 97 97 + """ 98 98 + Export synthesis result as Boolean equations. 99 99 + 100 100 + Args: 101 101 + result: The synthesis result 102 102 + 103 103 + Returns: 104 104 + Human-readable Boolean equations 105 105 + """ 106 106 + lines = [] 107 107 + lines.append(f"BCD to 7-Segment Decoder Equations") 108 108 + lines.append(f"Method: {result.method}") 109 109 + lines.append(f"Total gate inputs: {result.cost}") 110 110 + lines.append(f"Shared terms: {len(result.shared_implicants)}") 111 111 + lines.append("") 112 112 + 113 113 + if result.shared_implicants: 114 114 + lines.append("Shared product terms:") 115 115 + for impl, outputs in result.shared_implicants: 116 116 + lines.append(f" {impl.to_expr_str():12} -> {', '.join(outputs)}") 117 117 + lines.append("") 118 118 + 119 119 + lines.append("Output equations:") 120 120 + for segment in SEGMENT_NAMES: 121 121 + if segment in result.expressions: 122 122 + lines.append(f" {segment} = {result.expressions[segment]}") 123 123 + 124 124 + return "\n".join(lines) 125 125 + 126 126 + 127 127 + def to_c_code(result: SynthesisResult, func_name: str = "bcd_to_7seg") -> str: 128 128 + """ 129 129 + Export synthesis result as C code. 130 130 + 131 131 + Args: 132 132 + result: The synthesis result 133 133 + func_name: Name for the C function 134 134 + 135 135 + Returns: 136 136 + C source code as string 137 137 + """ 138 138 + lines = [] 139 139 + lines.append("/*") 140 140 + lines.append(" * BCD to 7-segment decoder") 141 141 + lines.append(f" * Synthesized with {result.cost} gate inputs using {result.method}") 142 142 + lines.append(" */") 143 143 + lines.append("") 144 144 + lines.append("#include <stdint.h>") 145 145 + lines.append("") 146 146 + lines.append(f"uint8_t {func_name}(uint8_t bcd) {{") 147 147 + lines.append(" // Extract individual bits") 148 148 + lines.append(" uint8_t A = (bcd >> 3) & 1;") 149 149 + lines.append(" uint8_t B = (bcd >> 2) & 1;") 150 150 + lines.append(" uint8_t C = (bcd >> 1) & 1;") 151 151 + lines.append(" uint8_t D = bcd & 1;") 152 152 + lines.append(" uint8_t nA = !A, nB = !B, nC = !C, nD = !D;") 153 153 + lines.append("") 154 154 + 155 155 + # Generate shared terms 156 156 + if result.shared_implicants: 157 157 + lines.append(" // Shared product terms") 158 158 + for i, (impl, _) in enumerate(result.shared_implicants): 159 159 + expr = impl_to_c(impl) 160 160 + lines.append(f" uint8_t t{i} = {expr};") 161 161 + lines.append("") 162 162 + 163 163 + # Generate output bits 164 164 + lines.append(" // Compute segment outputs") 165 165 + segment_exprs = [] 166 166 + for seg_idx, segment in enumerate(SEGMENT_NAMES): 167 167 + if segment in result.implicants_by_output: 168 168 + terms = [] 169 169 + for impl in result.implicants_by_output[segment]: 170 170 + shared_idx = None 171 171 + for j, (shared_impl, _) in enumerate(result.shared_implicants): 172 172 + if impl == shared_impl: 173 173 + shared_idx = j 174 174 + break 175 175 + 176 176 + if shared_idx is not None: 177 177 + terms.append(f"t{shared_idx}") 178 178 + else: 179 179 + terms.append(impl_to_c(impl)) 180 180 + 181 181 + expr = " | ".join(terms) if terms else "0" 182 182 + lines.append(f" uint8_t {segment} = {expr};") 183 183 + segment_exprs.append(segment) 184 184 + 185 185 + lines.append("") 186 186 + lines.append(" // Pack into result (bit 6 = a, bit 0 = g)") 187 187 + pack_expr = " | ".join( 188 188 + f"({segment} << {6-i})" 189 189 + for i, segment in enumerate(SEGMENT_NAMES) 190 190 + ) 191 191 + lines.append(f" return {pack_expr};") 192 192 + lines.append("}") 193 193 + 194 194 + return "\n".join(lines) 195 195 + 196 196 + 197 197 + def impl_to_c(impl: Implicant) -> str: 198 198 + """Convert an implicant to a C expression.""" 199 199 + var_map = { 200 200 + 'A': 'A', 'B': 'B', 'C': 'C', 'D': 'D', 201 201 + "A'": 'nA', "B'": 'nB', "C'": 'nC', "D'": 'nD', 202 202 + } 203 203 + var_names = ['A', 'B', 'C', 'D'] 204 204 + terms = [] 205 205 + 206 206 + for i in range(4): 207 207 + bit = 1 << (3 - i) 208 208 + if impl.mask & bit: 209 209 + if (impl.value >> (3 - i)) & 1: 210 210 + terms.append(var_names[i]) 211 211 + else: 212 212 + terms.append(f"n{var_names[i]}") 213 213 + 214 214 + if not terms: 215 215 + return "1" 216 216 + elif len(terms) == 1: 217 217 + return terms[0] 218 218 + else: 219 219 + return "(" + " & ".join(terms) + ")" 220 220 + 221 221 + 222 222 + if __name__ == "__main__": 223 223 + from .solver import BCDTo7SegmentSolver 224 224 + 225 225 + solver = BCDTo7SegmentSolver() 226 226 + result = solver.solve() 227 227 + 228 228 + print("=" * 60) 229 229 + print("VERILOG OUTPUT") 230 230 + print("=" * 60) 231 231 + print(to_verilog(result)) 232 232 + 233 233 + print("\n") 234 234 + print("=" * 60) 235 235 + print("C CODE OUTPUT") 236 236 + print("=" * 60) 237 237 + print(to_c_code(result))

+295

bcd_optimization/quine_mccluskey.py

··· 1 1 + """ 2 2 + Pure Python implementation of Quine-McCluskey algorithm for Boolean minimization. 3 3 + 4 4 + This implements multi-output prime implicant generation without requiring PyEDA. 5 5 + """ 6 6 + 7 7 + from dataclasses import dataclass, field 8 8 + from typing import Optional 9 9 + 10 10 + 11 11 + @dataclass(frozen=False) 12 12 + class Implicant: 13 13 + """ 14 14 + Represents a prime implicant with output coverage information. 15 15 + 16 16 + An implicant is represented by its mask and value: 17 17 + - mask: which bit positions matter (1 = matters, 0 = don't care) 18 18 + - value: the required bit values for positions that matter 19 19 + 20 20 + For 4 variables (A, B, C, D): 21 21 + - Bit 3 = A (MSB) 22 22 + - Bit 2 = B 23 23 + - Bit 1 = C 24 24 + - Bit 0 = D (LSB) 25 25 + """ 26 26 + 27 27 + mask: int # Which bits matter (1 = matters) 28 28 + value: int # Required values for bits that matter 29 29 + output_mask: int = field(default=0, compare=False) 30 30 + covered_minterms: dict[str, set[int]] = field(default_factory=dict, compare=False) 31 31 + 32 32 + @property 33 33 + def num_literals(self) -> int: 34 34 + """Count the number of literals (gate inputs) in this implicant.""" 35 35 + return bin(self.mask).count('1') 36 36 + 37 37 + def covers(self, minterm: int) -> bool: 38 38 + """Check if this implicant covers a given minterm.""" 39 39 + return (minterm & self.mask) == (self.value & self.mask) 40 40 + 41 41 + def to_expr_str(self, var_names: list[str] = None) -> str: 42 42 + """Convert to a Boolean expression string (product term).""" 43 43 + if var_names is None: 44 44 + var_names = ['A', 'B', 'C', 'D'] 45 45 + 46 46 + literals = [] 47 47 + for i in range(4): 48 48 + bit = 1 << (3 - i) 49 49 + if self.mask & bit: 50 50 + if (self.value >> (3 - i)) & 1: 51 51 + literals.append(var_names[i]) 52 52 + else: 53 53 + literals.append(f"{var_names[i]}'") 54 54 + 55 55 + return "".join(literals) if literals else "1" 56 56 + 57 57 + def __hash__(self): 58 58 + return hash((self.mask, self.value)) 59 59 + 60 60 + def __eq__(self, other): 61 61 + if not isinstance(other, Implicant): 62 62 + return False 63 63 + return self.mask == other.mask and self.value == other.value 64 64 + 65 65 + def __repr__(self): 66 66 + return f"Implicant({self.to_expr_str()})" 67 67 + 68 68 + 69 69 + def try_merge(impl1: Implicant, impl2: Implicant) -> Optional[Implicant]: 70 70 + """ 71 71 + Try to merge two implicants differing in exactly one variable. 72 72 + 73 73 + Two implicants can merge if: 74 74 + 1. They have the same mask 75 75 + 2. They differ in exactly one bit position (within the mask) 76 76 + 77 77 + Returns new implicant with one less literal, or None if can't merge. 78 78 + """ 79 79 + if impl1.mask != impl2.mask: 80 80 + return None 81 81 + 82 82 + diff = (impl1.value ^ impl2.value) & impl1.mask 83 83 + 84 84 + if bin(diff).count('1') != 1: 85 85 + return None 86 86 + 87 87 + new_mask = impl1.mask & ~diff 88 88 + new_value = impl1.value & new_mask 89 89 + 90 90 + return Implicant(mask=new_mask, value=new_value) 91 91 + 92 92 + 93 93 + def quine_mccluskey( 94 94 + on_set: set[int], 95 95 + dc_set: set[int] = None, 96 96 + n_vars: int = 4 97 97 + ) -> list[Implicant]: 98 98 + """ 99 99 + Run Quine-McCluskey algorithm to find all prime implicants. 100 100 + 101 101 + Args: 102 102 + on_set: Set of minterms where function is 1 103 103 + dc_set: Set of don't-care minterms (can be used for expansion) 104 104 + n_vars: Number of input variables 105 105 + 106 106 + Returns: 107 107 + List of prime implicants that cover at least one on-set minterm 108 108 + """ 109 109 + if dc_set is None: 110 110 + dc_set = set() 111 111 + 112 112 + full_mask = (1 << n_vars) - 1 113 113 + 114 114 + # Start with on-set + don't-cares as initial implicants 115 115 + all_minterms = on_set | dc_set 116 116 + 117 117 + current = {} 118 118 + for m in all_minterms: 119 119 + impl = Implicant(mask=full_mask, value=m) 120 120 + current[(impl.mask, impl.value)] = impl 121 121 + 122 122 + prime_implicants = [] 123 123 + 124 124 + while current: 125 125 + next_gen = {} 126 126 + used = set() 127 127 + 128 128 + impl_list = list(current.values()) 129 129 + 130 130 + for i, impl1 in enumerate(impl_list): 131 131 + for j in range(i + 1, len(impl_list)): 132 132 + impl2 = impl_list[j] 133 133 + merged = try_merge(impl1, impl2) 134 134 + if merged: 135 135 + key = (merged.mask, merged.value) 136 136 + if key not in next_gen: 137 137 + next_gen[key] = merged 138 138 + used.add((impl1.mask, impl1.value)) 139 139 + used.add((impl2.mask, impl2.value)) 140 140 + 141 141 + for key, impl in current.items(): 142 142 + if key not in used: 143 143 + # Only keep if it covers at least one on-set minterm 144 144 + covers_on = any(impl.covers(m) for m in on_set) 145 145 + if covers_on: 146 146 + prime_implicants.append(impl) 147 147 + 148 148 + current = next_gen 149 149 + 150 150 + return prime_implicants 151 151 + 152 152 + 153 153 + def quine_mccluskey_multi_output( 154 154 + minterms_by_output: dict[str, set[int]], 155 155 + dc_set: set[int] = None, 156 156 + n_vars: int = 4 157 157 + ) -> list[Implicant]: 158 158 + """ 159 159 + Generate prime implicants for multiple outputs with sharing tags. 160 160 + 161 161 + Generates primes for each output separately, then deduplicates and tags 162 162 + with output coverage. This correctly handles the case where different 163 163 + outputs have different on-sets. 164 164 + 165 165 + Args: 166 166 + minterms_by_output: Dict mapping output name to its on-set minterms 167 167 + dc_set: Set of don't-care minterms (shared across all outputs) 168 168 + n_vars: Number of input variables 169 169 + 170 170 + Returns: 171 171 + List of unique prime implicants with output coverage information 172 172 + """ 173 173 + if dc_set is None: 174 174 + dc_set = set() 175 175 + 176 176 + # Generate prime implicants for each output separately 177 177 + all_primes = {} # (mask, value) -> Implicant 178 178 + 179 179 + for output_name, on_set in minterms_by_output.items(): 180 180 + primes = quine_mccluskey(on_set, dc_set, n_vars) 181 181 + for impl in primes: 182 182 + key = (impl.mask, impl.value) 183 183 + if key not in all_primes: 184 184 + all_primes[key] = Implicant(mask=impl.mask, value=impl.value) 185 185 + 186 186 + # Tag each prime with which outputs it can cover 187 187 + output_names = list(minterms_by_output.keys()) 188 188 + result = [] 189 189 + 190 190 + for impl in all_primes.values(): 191 191 + impl.output_mask = 0 192 192 + impl.covered_minterms = {} 193 193 + 194 194 + for i, (name, minterms) in enumerate(minterms_by_output.items()): 195 195 + # An implicant can cover an output if: 196 196 + # 1. It covers some minterms in that output's on-set 197 197 + # 2. It doesn't cover any minterms in that output's off-set 198 198 + covered = {m for m in minterms if impl.covers(m)} 199 199 + 200 200 + # Check it doesn't cover any off-set minterms (0-9 that are not in on-set) 201 201 + off_set = set(range(10)) - minterms 202 202 + covers_off = any(impl.covers(m) for m in off_set) 203 203 + 204 204 + if covered and not covers_off: 205 205 + impl.covered_minterms[name] = covered 206 206 + impl.output_mask |= (1 << i) 207 207 + 208 208 + if impl.output_mask > 0: 209 209 + result.append(impl) 210 210 + 211 211 + return result 212 212 + 213 213 + 214 214 + def greedy_cover( 215 215 + primes: list[Implicant], 216 216 + minterms_by_output: dict[str, set[int]] 217 217 + ) -> tuple[list[Implicant], int]: 218 218 + """ 219 219 + Greedy set cover to select minimum-cost implicants. 220 220 + 221 221 + Returns: 222 222 + Tuple of (selected implicants, total cost) 223 223 + """ 224 224 + uncovered = { 225 225 + (out, m) 226 226 + for out, minterms in minterms_by_output.items() 227 227 + for m in minterms 228 228 + } 229 229 + 230 230 + selected = [] 231 231 + total_cost = 0 232 232 + 233 233 + while uncovered: 234 234 + best_impl = None 235 235 + best_ratio = -1 236 236 + best_covers = set() 237 237 + 238 238 + for impl in primes: 239 239 + if impl in selected: 240 240 + continue 241 241 + 242 242 + covers = set() 243 243 + for out, minterms in impl.covered_minterms.items(): 244 244 + for m in minterms: 245 245 + if (out, m) in uncovered: 246 246 + covers.add((out, m)) 247 247 + 248 248 + if not covers: 249 249 + continue 250 250 + 251 251 + cost = impl.num_literals if impl.num_literals > 0 else 1 252 252 + ratio = len(covers) / cost 253 253 + 254 254 + if ratio > best_ratio: 255 255 + best_ratio = ratio 256 256 + best_impl = impl 257 257 + best_covers = covers 258 258 + 259 259 + if best_impl is None: 260 260 + remaining = [(o, m) for o, m in uncovered] 261 261 + raise RuntimeError(f"Cannot cover: {remaining[:5]}...") 262 262 + 263 263 + selected.append(best_impl) 264 264 + total_cost += best_impl.num_literals 265 265 + uncovered -= best_covers 266 266 + 267 267 + return selected, total_cost 268 268 + 269 269 + 270 270 + def print_prime_implicants(primes: list[Implicant]): 271 271 + """Debug helper to print all prime implicants.""" 272 272 + print(f"Prime implicants ({len(primes)}):") 273 273 + for p in sorted(primes, key=lambda x: (-bin(x.output_mask).count('1'), x.num_literals)): 274 274 + outputs = list(p.covered_minterms.keys()) 275 275 + print(f" {p.to_expr_str():8} ({p.num_literals} lit) -> {', '.join(outputs)}") 276 276 + 277 277 + 278 278 + if __name__ == "__main__": 279 279 + from .truth_tables import SEGMENT_MINTERMS, DONT_CARES, SEGMENT_NAMES 280 280 + 281 281 + minterms = {s: set(SEGMENT_MINTERMS[s]) for s in SEGMENT_NAMES} 282 282 + 283 283 + primes = quine_mccluskey_multi_output( 284 284 + minterms, 285 285 + set(DONT_CARES), 286 286 + n_vars=4 287 287 + ) 288 288 + 289 289 + print_prime_implicants(primes) 290 290 + 291 291 + print("\nGreedy cover:") 292 292 + selected, cost = greedy_cover(primes, minterms) 293 293 + print(f"Selected {len(selected)} implicants, cost = {cost}") 294 294 + for impl in selected: 295 295 + print(f" {impl.to_expr_str()}")

+418

bcd_optimization/solver.py

··· 1 1 + """ 2 2 + BCD to 7-segment decoder solver using SAT-based exact synthesis. 3 3 + 4 4 + This module implements a multi-output logic synthesis solver that minimizes 5 5 + gate inputs through shared term extraction and SAT/MaxSAT optimization. 6 6 + """ 7 7 + 8 8 + from dataclasses import dataclass, field 9 9 + from typing import Optional 10 10 + from pysat.formula import WCNF, CNF 11 11 + from pysat.examples.rc2 import RC2 12 12 + from pysat.solvers import Solver 13 13 + 14 14 + from .truth_tables import SEGMENT_NAMES, SEGMENT_MINTERMS, DONT_CARES 15 15 + from .quine_mccluskey import ( 16 16 + Implicant, 17 17 + quine_mccluskey_multi_output, 18 18 + greedy_cover, 19 19 + ) 20 20 + 21 21 + 22 22 + @dataclass 23 23 + class SynthesisResult: 24 24 + """Result of logic synthesis optimization.""" 25 25 + 26 26 + cost: int # Total gate inputs 27 27 + implicants_by_output: dict[str, list[Implicant]] 28 28 + shared_implicants: list[tuple[Implicant, list[str]]] 29 29 + method: str 30 30 + expressions: dict[str, str] = field(default_factory=dict) 31 31 + 32 32 + 33 33 + class BCDTo7SegmentSolver: 34 34 + """ 35 35 + Multi-output logic synthesis solver for BCD to 7-segment decoders. 36 36 + 37 37 + Uses a combination of: 38 38 + 1. Quine-McCluskey with greedy cover for baseline 39 39 + 2. MaxSAT optimization for minimum-cost covering with sharing 40 40 + 3. SAT-based exact synthesis for provably optimal circuits 41 41 + """ 42 42 + 43 43 + def __init__(self): 44 44 + self.prime_implicants: list[Implicant] = [] 45 45 + self.minterms = {s: set(SEGMENT_MINTERMS[s]) for s in SEGMENT_NAMES} 46 46 + self.dc_set = set(DONT_CARES) 47 47 + 48 48 + def greedy_baseline(self) -> SynthesisResult: 49 49 + """ 50 50 + Phase 1: Establish baseline using greedy set cover. 51 51 + 52 52 + Returns the baseline cost and selected implicants. 53 53 + """ 54 54 + if not self.prime_implicants: 55 55 + self.generate_prime_implicants() 56 56 + 57 57 + selected, cost = greedy_cover(self.prime_implicants, self.minterms) 58 58 + 59 59 + # Organize by output 60 60 + implicants_by_output = {s: [] for s in SEGMENT_NAMES} 61 61 + shared = [] 62 62 + 63 63 + for impl in selected: 64 64 + outputs_using = list(impl.covered_minterms.keys()) 65 65 + if len(outputs_using) > 1: 66 66 + shared.append((impl, outputs_using)) 67 67 + for out in outputs_using: 68 68 + implicants_by_output[out].append(impl) 69 69 + 70 70 + # Build expressions 71 71 + expressions = {} 72 72 + for segment in SEGMENT_NAMES: 73 73 + terms = [impl.to_expr_str() for impl in implicants_by_output[segment]] 74 74 + expressions[segment] = " + ".join(terms) if terms else "0" 75 75 + 76 76 + return SynthesisResult( 77 77 + cost=cost, 78 78 + implicants_by_output=implicants_by_output, 79 79 + shared_implicants=shared, 80 80 + method="greedy", 81 81 + expressions=expressions, 82 82 + ) 83 83 + 84 84 + def generate_prime_implicants(self) -> list[Implicant]: 85 85 + """Generate all prime implicants with multi-output coverage tags.""" 86 86 + self.prime_implicants = quine_mccluskey_multi_output( 87 87 + self.minterms, 88 88 + self.dc_set, 89 89 + n_vars=4 90 90 + ) 91 91 + return self.prime_implicants 92 92 + 93 93 + def maxsat_optimize(self, target_cost: int = 22) -> SynthesisResult: 94 94 + """ 95 95 + Phase 2: MaxSAT optimization for minimum-cost covering with sharing. 96 96 + 97 97 + Formulates the covering problem as weighted MaxSAT where: 98 98 + - Hard clauses: every minterm of every output must be covered 99 99 + - Soft clauses: minimize total literals (penalize each implicant) 100 100 + """ 101 101 + if not self.prime_implicants: 102 102 + self.generate_prime_implicants() 103 103 + 104 104 + wcnf = WCNF() 105 105 + 106 106 + # Variable mapping: implicant index -> SAT variable (1-indexed) 107 107 + impl_vars = {i: i + 1 for i in range(len(self.prime_implicants))} 108 108 + 109 109 + # Hard constraints: every (output, minterm) pair must be covered 110 110 + for segment in SEGMENT_NAMES: 111 111 + for minterm in SEGMENT_MINTERMS[segment]: 112 112 + covering = [] 113 113 + for i, impl in enumerate(self.prime_implicants): 114 114 + if segment in impl.covered_minterms: 115 115 + if minterm in impl.covered_minterms[segment]: 116 116 + covering.append(impl_vars[i]) 117 117 + 118 118 + if covering: 119 119 + wcnf.append(covering) # Hard: at least one must be selected 120 120 + else: 121 121 + raise RuntimeError( 122 122 + f"No implicant covers {segment}:{minterm}" 123 123 + ) 124 124 + 125 125 + # Soft constraints: penalize each implicant by its literal count 126 126 + for i, impl in enumerate(self.prime_implicants): 127 127 + wcnf.append([-impl_vars[i]], weight=impl.num_literals) 128 128 + 129 129 + # Solve 130 130 + with RC2(wcnf) as solver: 131 131 + model = solver.compute() 132 132 + if model is None: 133 133 + raise RuntimeError("MaxSAT solver found no solution") 134 134 + 135 135 + # Extract selected implicants 136 136 + selected = [] 137 137 + for i, impl in enumerate(self.prime_implicants): 138 138 + if impl_vars[i] in model: 139 139 + selected.append(impl) 140 140 + 141 141 + # Calculate actual cost 142 142 + cost = sum(impl.num_literals for impl in selected) 143 143 + 144 144 + # Organize by output 145 145 + implicants_by_output = {s: [] for s in SEGMENT_NAMES} 146 146 + shared = [] 147 147 + 148 148 + for impl in selected: 149 149 + outputs_using = list(impl.covered_minterms.keys()) 150 150 + if len(outputs_using) > 1: 151 151 + shared.append((impl, outputs_using)) 152 152 + for out in outputs_using: 153 153 + implicants_by_output[out].append(impl) 154 154 + 155 155 + # Build expressions 156 156 + expressions = {} 157 157 + for segment in SEGMENT_NAMES: 158 158 + terms = [impl.to_expr_str() for impl in implicants_by_output[segment]] 159 159 + expressions[segment] = " + ".join(terms) if terms else "0" 160 160 + 161 161 + return SynthesisResult( 162 162 + cost=cost, 163 163 + implicants_by_output=implicants_by_output, 164 164 + shared_implicants=shared, 165 165 + method="maxsat", 166 166 + expressions=expressions, 167 167 + ) 168 168 + 169 169 + def exact_synthesis(self, max_gates: int = 15) -> SynthesisResult: 170 170 + """ 171 171 + Phase 3: SAT-based exact synthesis for provably optimal circuits. 172 172 + 173 173 + Encodes the circuit synthesis problem as SAT and iteratively searches 174 174 + for the minimum number of gates. 175 175 + """ 176 176 + for num_gates in range(1, max_gates + 1): 177 177 + print(f" Trying {num_gates} gates...") 178 178 + result = self._try_exact_synthesis(num_gates) 179 179 + if result is not None: 180 180 + return result 181 181 + 182 182 + raise RuntimeError(f"No solution found with up to {max_gates} gates") 183 183 + 184 184 + def _try_exact_synthesis(self, num_gates: int) -> Optional[SynthesisResult]: 185 185 + """ 186 186 + Try to find a circuit with exactly num_gates gates. 187 187 + 188 188 + Uses a SAT encoding where: 189 189 + - Variables encode gate structure (which inputs each gate uses) 190 190 + - Variables encode gate function (AND, OR, NAND, NOR, etc.) 191 191 + - Constraints ensure functional correctness on all valid inputs 192 192 + """ 193 193 + n_inputs = 4 # A, B, C, D 194 194 + n_outputs = 7 # a, b, c, d, e, f, g 195 195 + n_nodes = n_inputs + num_gates 196 196 + 197 197 + # Only verify on valid BCD inputs (0-9) 198 198 + truth_rows = list(range(10)) 199 199 + n_rows = len(truth_rows) 200 200 + 201 201 + cnf = CNF() 202 202 + var_counter = [1] 203 203 + 204 204 + def new_var(): 205 205 + v = var_counter[0] 206 206 + var_counter[0] += 1 207 207 + return v 208 208 + 209 209 + # Variables: 210 210 + # x[i][t] = output of node i on row t 211 211 + # s[i][j][k] = gate i uses inputs j and k 212 212 + # f[i][p][q] = gate i output when inputs are (p, q) 213 213 + # g[h][i] = output h comes from node i 214 214 + 215 215 + x = {} 216 216 + s = {} 217 217 + f = {} 218 218 + g = {} 219 219 + 220 220 + for i in range(n_nodes): 221 221 + x[i] = {t: new_var() for t in range(n_rows)} 222 222 + 223 223 + for i in range(n_inputs, n_nodes): 224 224 + s[i] = {} 225 225 + for j in range(i): 226 226 + s[i][j] = {k: new_var() for k in range(j + 1, i)} 227 227 + f[i] = {p: {q: new_var() for q in range(2)} for p in range(2)} 228 228 + 229 229 + for h in range(n_outputs): 230 230 + g[h] = {i: new_var() for i in range(n_nodes)} 231 231 + 232 232 + # Constraint 1: Primary inputs are fixed by truth table 233 233 + for t_idx, t in enumerate(truth_rows): 234 234 + for i in range(n_inputs): 235 235 + bit = (t >> (n_inputs - 1 - i)) & 1 236 236 + cnf.append([x[i][t_idx] if bit else -x[i][t_idx]]) 237 237 + 238 238 + # Constraint 2: Each gate has exactly one input pair 239 239 + for i in range(n_inputs, n_nodes): 240 240 + all_sels = [s[i][j][k] for j in range(i) for k in range(j + 1, i)] 241 241 + # At least one 242 242 + cnf.append(all_sels) 243 243 + # At most one 244 244 + for idx1, sel1 in enumerate(all_sels): 245 245 + for sel2 in all_sels[idx1 + 1:]: 246 246 + cnf.append([-sel1, -sel2]) 247 247 + 248 248 + # Constraint 3: Gate function consistency 249 249 + for i in range(n_inputs, n_nodes): 250 250 + for j in range(i): 251 251 + for k in range(j + 1, i): 252 252 + for t_idx in range(n_rows): 253 253 + for pv in range(2): 254 254 + for qv in range(2): 255 255 + for outv in range(2): 256 256 + # If s[i][j][k] ∧ x[j][t]=pv ∧ x[k][t]=qv ∧ f[i][pv][qv]=outv 257 257 + # then x[i][t]=outv 258 258 + clause = [-s[i][j][k]] 259 259 + clause.append(-x[j][t_idx] if pv else x[j][t_idx]) 260 260 + clause.append(-x[k][t_idx] if qv else x[k][t_idx]) 261 261 + clause.append(-f[i][pv][qv] if outv else f[i][pv][qv]) 262 262 + clause.append(x[i][t_idx] if outv else -x[i][t_idx]) 263 263 + cnf.append(clause) 264 264 + 265 265 + # Constraint 4: Each output assigned to exactly one node 266 266 + for h in range(n_outputs): 267 267 + cnf.append([g[h][i] for i in range(n_nodes)]) 268 268 + for i in range(n_nodes): 269 269 + for j in range(i + 1, n_nodes): 270 270 + cnf.append([-g[h][i], -g[h][j]]) 271 271 + 272 272 + # Constraint 5: Output correctness 273 273 + for h, segment in enumerate(SEGMENT_NAMES): 274 274 + for t_idx, t in enumerate(truth_rows): 275 275 + expected = 1 if t in SEGMENT_MINTERMS[segment] else 0 276 276 + for i in range(n_nodes): 277 277 + if expected: 278 278 + cnf.append([-g[h][i], x[i][t_idx]]) 279 279 + else: 280 280 + cnf.append([-g[h][i], -x[i][t_idx]]) 281 281 + 282 282 + # Solve 283 283 + with Solver(bootstrap_with=cnf) as solver: 284 284 + if solver.solve(): 285 285 + model = set(solver.get_model()) 286 286 + return self._decode_exact_solution( 287 287 + model, num_gates, n_inputs, n_nodes, x, s, f, g 288 288 + ) 289 289 + return None 290 290 + 291 291 + def _decode_exact_solution( 292 292 + self, model, num_gates, n_inputs, n_nodes, x, s, f, g 293 293 + ) -> SynthesisResult: 294 294 + """Decode SAT solution into readable circuit description.""" 295 295 + 296 296 + def is_true(var): 297 297 + return var in model 298 298 + 299 299 + node_names = ['A', 'B', 'C', 'D'] + [f'g{i}' for i in range(num_gates)] 300 300 + gate_exprs = {} 301 301 + 302 302 + for i in range(n_inputs, n_nodes): 303 303 + for j in range(i): 304 304 + for k in range(j + 1, i): 305 305 + if is_true(s[i][j][k]): 306 306 + # Decode gate function 307 307 + func = 0 308 308 + for p in range(2): 309 309 + for q in range(2): 310 310 + if is_true(f[i][p][q]): 311 311 + func |= (1 << (p * 2 + q)) 312 312 + 313 313 + op = self._decode_gate_function(func) 314 314 + gate_exprs[i] = f"({node_names[j]} {op} {node_names[k]})" 315 315 + node_names[i] = gate_exprs[i] 316 316 + break 317 317 + 318 318 + expressions = {} 319 319 + for h, segment in enumerate(SEGMENT_NAMES): 320 320 + for i in range(n_nodes): 321 321 + if is_true(g[h][i]): 322 322 + expressions[segment] = node_names[i] 323 323 + break 324 324 + 325 325 + return SynthesisResult( 326 326 + cost=num_gates * 2, # 2 inputs per 2-input gate 327 327 + implicants_by_output={}, 328 328 + shared_implicants=[], 329 329 + method=f"exact_{num_gates}gates", 330 330 + expressions=expressions, 331 331 + ) 332 332 + 333 333 + def _decode_gate_function(self, func: int) -> str: 334 334 + """Decode 4-bit function to gate type name.""" 335 335 + # func[pq] gives output for inputs (p, q) 336 336 + # Bit 0: f(0,0), Bit 1: f(0,1), Bit 2: f(1,0), Bit 3: f(1,1) 337 337 + names = { 338 338 + 0b0000: "0", 339 339 + 0b0001: "AND", 340 340 + 0b0010: "A>B", # A AND NOT B 341 341 + 0b0011: "A", 342 342 + 0b0100: "B>A", # B AND NOT A 343 343 + 0b0101: "B", 344 344 + 0b0110: "XOR", 345 345 + 0b0111: "OR", 346 346 + 0b1000: "NOR", 347 347 + 0b1001: "XNOR", 348 348 + 0b1010: "!B", 349 349 + 0b1011: "A+!B", # A OR NOT B 350 350 + 0b1100: "!A", 351 351 + 0b1101: "!A+B", # NOT A OR B 352 352 + 0b1110: "NAND", 353 353 + 0b1111: "1", 354 354 + } 355 355 + return names.get(func, f"F{func:04b}") 356 356 + 357 357 + def solve(self, target_cost: int = 22, use_exact: bool = False) -> SynthesisResult: 358 358 + """ 359 359 + Run the complete optimization pipeline. 360 360 + 361 361 + Args: 362 362 + target_cost: Target gate input count to beat 363 363 + use_exact: If True, use SAT-based exact synthesis (slower) 364 364 + 365 365 + Returns: 366 366 + Best synthesis result found 367 367 + """ 368 368 + results = [] 369 369 + 370 370 + # Phase 1: Generate primes and greedy baseline 371 371 + print("Phase 1: Generating prime implicants...") 372 372 + self.generate_prime_implicants() 373 373 + print(f" Found {len(self.prime_implicants)} prime implicants") 374 374 + 375 375 + print("\nPhase 1b: Greedy set cover baseline...") 376 376 + greedy_result = self.greedy_baseline() 377 377 + results.append(greedy_result) 378 378 + print(f" Greedy cost: {greedy_result.cost} gate inputs") 379 379 + 380 380 + # Phase 2: MaxSAT optimization 381 381 + print("\nPhase 2: MaxSAT optimization with sharing...") 382 382 + maxsat_result = self.maxsat_optimize(target_cost) 383 383 + results.append(maxsat_result) 384 384 + print(f" MaxSAT cost: {maxsat_result.cost} gate inputs") 385 385 + print(f" Shared terms: {len(maxsat_result.shared_implicants)}") 386 386 + 387 387 + # Phase 3: Exact synthesis (optional) 388 388 + if use_exact: 389 389 + print("\nPhase 3: SAT-based exact synthesis...") 390 390 + try: 391 391 + exact_result = self.exact_synthesis(max_gates=12) 392 392 + results.append(exact_result) 393 393 + print(f" Exact cost: {exact_result.cost} gate inputs") 394 394 + except RuntimeError as e: 395 395 + print(f" Exact synthesis failed: {e}") 396 396 + 397 397 + # Return best result 398 398 + best = min(results, key=lambda r: r.cost) 399 399 + print(f"\nBest result: {best.cost} gate inputs ({best.method})") 400 400 + 401 401 + return best 402 402 + 403 403 + def print_result(self, result: SynthesisResult): 404 404 + """Pretty-print a synthesis result.""" 405 405 + print(f"\n{'=' * 60}") 406 406 + print(f"Synthesis Result: {result.method}") 407 407 + print(f"{'=' * 60}") 408 408 + print(f"Total gate inputs: {result.cost}") 409 409 + 410 410 + if result.shared_implicants: 411 411 + print(f"\nShared terms ({len(result.shared_implicants)}):") 412 412 + for impl, outputs in result.shared_implicants: 413 413 + print(f" {impl.to_expr_str():12} -> {', '.join(outputs)}") 414 414 + 415 415 + print("\nExpressions:") 416 416 + for segment in SEGMENT_NAMES: 417 417 + if segment in result.expressions: 418 418 + print(f" {segment} = {result.expressions[segment]}")

+85

bcd_optimization/truth_tables.py

··· 1 1 + """ 2 2 + Truth tables for BCD to 7-segment decoder. 3 3 + 4 4 + BCD inputs: 4 bits (A, B, C, D) representing digits 0-9 5 5 + - Positions 0-9: valid BCD digits 6 6 + - Positions 10-15: don't care (invalid BCD) 7 7 + 8 8 + 7-segment display layout: 9 9 + aaa 10 10 + f b 11 11 + f b 12 12 + ggg 13 13 + e c 14 14 + e c 15 15 + ddd 16 16 + 17 17 + Each segment's truth table: 1 = ON, 0 = OFF, - = don't care 18 18 + """ 19 19 + 20 20 + # Truth tables as strings (index 0-15, positions 10-15 are don't cares) 21 21 + # Format: digit 0 at index 0, digit 9 at index 9, don't cares at 10-15 22 22 + SEGMENT_TRUTH_TABLES = { 23 23 + 'a': "1011011111------", # ON for 0,2,3,5,6,7,8,9 24 24 + 'b': "1111100111------", # ON for 0,1,2,3,4,7,8,9 25 25 + 'c': "1110111111------", # ON for 0,1,2,4,5,6,7,8,9 26 26 + 'd': "1011011011------", # ON for 0,2,3,5,6,8,9 27 27 + 'e': "1010001010------", # ON for 0,2,6,8 28 28 + 'f': "1000111111------", # ON for 0,4,5,6,7,8,9 29 29 + 'g': "0011111011------", # ON for 2,3,4,5,6,8,9 30 30 + } 31 31 + 32 32 + SEGMENT_NAMES = ['a', 'b', 'c', 'd', 'e', 'f', 'g'] 33 33 + 34 34 + # Minterms (ON-set) for each segment - these are the BCD digit indices where segment is ON 35 35 + SEGMENT_MINTERMS = { 36 36 + 'a': [0, 2, 3, 5, 6, 7, 8, 9], 37 37 + 'b': [0, 1, 2, 3, 4, 7, 8, 9], 38 38 + 'c': [0, 1, 2, 4, 5, 6, 7, 8, 9], 39 39 + 'd': [0, 2, 3, 5, 6, 8, 9], 40 40 + 'e': [0, 2, 6, 8], 41 41 + 'f': [0, 4, 5, 6, 7, 8, 9], 42 42 + 'g': [2, 3, 4, 5, 6, 8, 9], 43 43 + } 44 44 + 45 45 + # Don't care positions (invalid BCD values 10-15) 46 46 + DONT_CARES = [10, 11, 12, 13, 14, 15] 47 47 + 48 48 + # Input variable names (MSB to LSB) 49 49 + INPUT_VARS = ['A', 'B', 'C', 'D'] 50 50 + 51 51 + 52 52 + def minterm_to_bits(minterm: int) -> tuple[int, int, int, int]: 53 53 + """Convert a minterm index to its 4-bit representation (A, B, C, D).""" 54 54 + return ( 55 55 + (minterm >> 3) & 1, # A (MSB) 56 56 + (minterm >> 2) & 1, # B 57 57 + (minterm >> 1) & 1, # C 58 58 + minterm & 1, # D (LSB) 59 59 + ) 60 60 + 61 61 + 62 62 + def bits_to_minterm(a: int, b: int, c: int, d: int) -> int: 63 63 + """Convert 4-bit representation to minterm index.""" 64 64 + return (a << 3) | (b << 2) | (c << 1) | d 65 65 + 66 66 + 67 67 + def print_truth_table(): 68 68 + """Print the complete truth table for all segments.""" 69 69 + print("BCD to 7-Segment Truth Table") 70 70 + print("=" * 50) 71 71 + print(f"{'Digit':>5} | {'A':>2} {'B':>2} {'C':>2} {'D':>2} | ", end="") 72 72 + print(" ".join(f"{s}" for s in SEGMENT_NAMES)) 73 73 + print("-" * 50) 74 74 + 75 75 + for i in range(16): 76 76 + a, b, c, d = minterm_to_bits(i) 77 77 + digit = str(i) if i < 10 else "X" 78 78 + segments = " ".join( 79 79 + SEGMENT_TRUTH_TABLES[s][i] for s in SEGMENT_NAMES 80 80 + ) 81 81 + print(f"{digit:>5} | {a} {b} {c} {d} | {segments}") 82 82 + 83 83 + 84 84 + if __name__ == "__main__": 85 85 + print_truth_table()

+118

bcd_optimization/verify.py

··· 1 1 + """ 2 2 + Verification module for BCD to 7-segment decoder synthesis results. 3 3 + 4 4 + Ensures synthesized expressions produce correct outputs for all valid BCD inputs. 5 5 + """ 6 6 + 7 7 + from .truth_tables import SEGMENT_MINTERMS, SEGMENT_NAMES 8 8 + from .quine_mccluskey import Implicant 9 9 + from .solver import SynthesisResult 10 10 + 11 11 + 12 12 + def evaluate_implicant(impl: Implicant, a: int, b: int, c: int, d: int) -> bool: 13 13 + """Evaluate an implicant on a specific input.""" 14 14 + minterm = (a << 3) | (b << 2) | (c << 1) | d 15 15 + return impl.covers(minterm) 16 16 + 17 17 + 18 18 + def evaluate_sop(implicants: list[Implicant], a: int, b: int, c: int, d: int) -> bool: 19 19 + """Evaluate a sum-of-products on a specific input (OR of AND terms).""" 20 20 + return any(evaluate_implicant(impl, a, b, c, d) for impl in implicants) 21 21 + 22 22 + 23 23 + def verify_result(result: SynthesisResult) -> tuple[bool, list[str]]: 24 24 + """ 25 25 + Verify that a synthesis result produces correct outputs for all BCD inputs. 26 26 + 27 27 + Args: 28 28 + result: The synthesis result to verify 29 29 + 30 30 + Returns: 31 31 + Tuple of (all_correct, list of error messages) 32 32 + """ 33 33 + errors = [] 34 34 + 35 35 + for segment in SEGMENT_NAMES: 36 36 + if segment not in result.implicants_by_output: 37 37 + continue 38 38 + 39 39 + implicants = result.implicants_by_output[segment] 40 40 + expected_on = set(SEGMENT_MINTERMS[segment]) 41 41 + 42 42 + for digit in range(10): # Valid BCD: 0-9 43 43 + a = (digit >> 3) & 1 44 44 + b = (digit >> 2) & 1 45 45 + c = (digit >> 1) & 1 46 46 + d = digit & 1 47 47 + 48 48 + actual = evaluate_sop(implicants, a, b, c, d) 49 49 + expected = digit in expected_on 50 50 + 51 51 + if actual != expected: 52 52 + errors.append( 53 53 + f"Segment {segment}, digit {digit}: " 54 54 + f"expected {expected}, got {actual}" 55 55 + ) 56 56 + 57 57 + return len(errors) == 0, errors 58 58 + 59 59 + 60 60 + def print_truth_table_comparison(result: SynthesisResult): 61 61 + """Print truth table comparing expected vs actual outputs.""" 62 62 + print("Truth Table Verification") 63 63 + print("=" * 60) 64 64 + print(f"{'Digit':>5} | {'ABCD':>4} | Expected | Actual | Match") 65 65 + print("-" * 60) 66 66 + 67 67 + all_match = True 68 68 + 69 69 + for digit in range(10): 70 70 + a = (digit >> 3) & 1 71 71 + b = (digit >> 2) & 1 72 72 + c = (digit >> 1) & 1 73 73 + d = digit & 1 74 74 + 75 75 + expected = "" 76 76 + actual = "" 77 77 + match_str = "" 78 78 + 79 79 + for segment in SEGMENT_NAMES: 80 80 + exp = "1" if digit in SEGMENT_MINTERMS[segment] else "0" 81 81 + expected += exp 82 82 + 83 83 + if segment in result.implicants_by_output: 84 84 + implicants = result.implicants_by_output[segment] 85 85 + act = "1" if evaluate_sop(implicants, a, b, c, d) else "0" 86 86 + else: 87 87 + act = "?" 88 88 + 89 89 + actual += act 90 90 + match_str += "." if exp == act else "X" 91 91 + if exp != act: 92 92 + all_match = False 93 93 + 94 94 + print(f"{digit:>5} | {a}{b}{c}{d} | {expected:>9} | {actual:>9} | {match_str}") 95 95 + 96 96 + print("-" * 60) 97 97 + print(f"All correct: {all_match}") 98 98 + return all_match 99 99 + 100 100 + 101 101 + if __name__ == "__main__": 102 102 + from .solver import BCDTo7SegmentSolver 103 103 + 104 104 + solver = BCDTo7SegmentSolver() 105 105 + result = solver.solve() 106 106 + 107 107 + print("\n") 108 108 + correct, errors = verify_result(result) 109 109 + 110 110 + if correct: 111 111 + print("Verification PASSED: All outputs correct!") 112 112 + else: 113 113 + print("Verification FAILED:") 114 114 + for err in errors: 115 115 + print(f" {err}") 116 116 + 117 117 + print("\n") 118 118 + print_truth_table_comparison(result)

+25

pyproject.toml

··· 1 1 + [project] 2 2 + name = "bcd-optimization" 3 3 + version = "0.1.0" 4 4 + description = "Multi-output logic synthesis solver for BCD to 7-segment decoders" 5 5 + readme = "README.md" 6 6 + requires-python = ">=3.10" 7 7 + license = "MIT" 8 8 + authors = [ 9 9 + { name = "Kieran Klukas", email = "kieran@dunkirk.sh" } 10 10 + ] 11 11 + dependencies = [ 12 12 + "python-sat>=0.1.8", 13 13 + ] 14 14 + 15 15 + [project.optional-dependencies] 16 16 + dev = [ 17 17 + "pytest>=8.0.0", 18 18 + ] 19 19 + 20 20 + [project.scripts] 21 21 + bcd-optimize = "bcd_optimization.cli:main" 22 22 + 23 23 + [build-system] 24 24 + requires = ["hatchling"] 25 25 + build-backend = "hatchling.build"

+218

spec.md

··· 1 1 + # Beating 23 gate inputs: Multi-output logic synthesis for BCD to 7-segment decoders 2 2 + 3 3 + A custom multi-output logic synthesis solver can achieve **18-21 total gate inputs** for the BCD to 7-segment decoder, substantially beating the 23-input baseline. The key insight is that SAT-based exact synthesis combined with aggressive shared term extraction is tractable for this 4-input, 7-output problem size, enabling provably optimal or near-optimal solutions. This report provides concrete algorithms, encodings, and implementation strategies to build such a solver. 4 4 + 5 5 + ## The BCD to 7-segment optimization landscape 6 6 + 7 7 + The decoder maps 4-bit BCD inputs (0-9 valid, 10-15 don't-care) to 7 segment outputs. Standard K-map minimization yields **27-35 gate inputs** without sharing; the theoretical minimum with full multi-output sharing is approximately **18-20 gate inputs**. The 6 don't-care conditions per output and significant overlap between segment functions create substantial optimization opportunities. 8 8 + 9 9 + The truth table reveals clear sharing patterns. Segments a, c, d, e, f, and g all activate for digit 0, suggesting common logic. Segment e (active only for 0, 2, 6, 8) is simplest with just **2 product terms**: `B'D' + CD'`. Segment c (nearly always active) simplifies to `B + C' + D`. The segments share subexpressions like `B'D'` (used in a, d, e), `CD'` (used in d, e, g), and `BC'` (used in f, g). A solver that identifies and exploits these shared terms will dramatically outperform single-output optimization. 10 10 + 11 11 + ## Algorithm selection: SAT-based exact synthesis wins for this problem size 12 12 + 13 13 + Three algorithmic approaches are viable for multi-output logic synthesis, each with distinct tradeoffs. For the BCD to 7-segment decoder specifically, **SAT-based exact synthesis** is the recommended approach because the problem size (4 inputs, 7 outputs) falls within the tractable range for exact methods. 14 14 + 15 15 + **Classical two-level minimization** using Espresso-MV or BOOM runs in polynomial time and handles multi-output functions by encoding outputs as an additional multiple-valued variable. Product terms shared across outputs appear naturally when the MVL encoding's output sets intersect during cube expansion. Espresso's MAKE_SPARSE pass then removes unnecessary output connections. While fast, these methods optimize literal count rather than gate input count directly, and produce two-level (SOP) circuits rather than optimal multi-level implementations. 16 16 + 17 17 + **SAT-based exact synthesis** encodes the question "does an r-gate circuit exist implementing these functions?" as a satisfiability problem. For circuits with ≤8 inputs, this approach finds provably optimal solutions. The Kojevnikov-Kulikov-Yaroslavtsev encoding (SAT 2009) and the Haaswijk-Soeken-Mishchenko formulation (TCAD 2020) both enable multi-output optimization with shared gates. Performance data shows 4-input functions average **225ms** for exact synthesis—well within practical limits. 18 18 + 19 19 + **Heuristic multi-level synthesis** via ABC's DAG-aware rewriting scales to large designs but provides no optimality guarantees. The `resyn2` script typically achieves 10-15% area reduction through iterative rewriting, refactoring, and resubstitution. For small functions like BCD decoders, exact methods outperform these heuristics. 20 20 + 21 21 + ## SAT encoding for multi-output gate input minimization 22 22 + 23 23 + The core encoding creates Boolean variables representing circuit structure, then adds constraints ensuring functional correctness. For a circuit with n primary inputs and r gates computing m outputs: 24 24 + 25 25 + **Variable types define the search space:** 26 26 + - `x_{i,t}`: Simulation variable—gate i's output on truth table row t 27 27 + - `s_{i,j,k}`: Selection variable—gate i takes inputs from nodes j and k 28 28 + - `f_{i,p,q}`: Function variable—gate i's output when inputs are (p,q) 29 29 + - `g_{h,i}`: Output assignment—output h is computed by gate i 30 30 + 31 31 + **Functional correctness constraints** ensure each gate computes consistent values across all input combinations. For each gate i, input pair (j,k), truth table row t, and input/output pattern (a,b,c): 32 32 + 33 33 + ``` 34 34 + (¬s_{i,j,k} ∨ (x_{i,t} ⊕ a) ∨ (x_{j,t} ⊕ b) ∨ (x_{k,t} ⊕ c) ∨ (f_{i,b,c} ⊕ ā)) 35 35 + ``` 36 36 + 37 37 + This clause fires when selection s_{i,j,k} is true and the simulation values match pattern (a,b,c), forcing the function variable to be consistent. 38 38 + 39 39 + **Output constraints** connect internal gates to external outputs. For each output h and gate i, if the specification requires output h to be 1 on input row t: 40 40 + ``` 41 41 + (¬g_{h,i} ∨ x_{i,t}) 42 42 + ``` 43 43 + 44 44 + **Multi-output sharing** emerges naturally: multiple g_{h,i} variables can point to the same gate i, and that gate is counted only once in the cost function. This is the mechanism that enables beating single-output optimization. 45 45 + 46 46 + **Optimization via iterative SAT or MaxSAT:** 47 47 + The simplest approach iterates r from 1 upward, asking "is there an r-gate solution?" until finding the minimum. For gate input minimization specifically, **Weighted MaxSAT** is more direct: hard clauses encode correctness, soft clauses penalize each selection variable s_{i,j,k} by its input cost (typically 2 for 2-input gates). The RC2 MaxSAT solver in PySAT won MaxSAT Evaluations 2018-2019 and handles this formulation efficiently. 48 48 + 49 49 + ## Shared subcircuit extraction algorithms 50 50 + 51 51 + Before or alongside SAT search, identifying candidate shared terms accelerates optimization. Three techniques are most effective: 52 52 + 53 53 + **Kernel extraction** finds common algebraic divisors. A kernel is a cube-free quotient when dividing a function by a cube (the co-kernel). The fundamental theorem states: if functions F and G share a multi-cube common divisor, their kernels must intersect in more than one cube. The algorithm recursively divides expressions by literals, collecting all kernels and co-kernels, then searches for rectangles in the co-kernel/cube matrix where all entries are non-empty. 54 54 + 55 55 + **Structural hashing** in AIG-based tools like ABC provides automatic CSE. When constructing an And-Inverter Graph, each new AND node is hash-table checked against existing nodes with identical fanins. This guarantees no structural duplicates within one logic level, though functionally equivalent but structurally different circuits can still exist. 56 56 + 57 57 + **FRAIG construction** extends structural hashing with functional equivalence checking. During circuit construction, random simulation identifies candidate equivalent node pairs, then SAT queries verify true equivalence. Merging functionally equivalent nodes reduces circuit size beyond what structural hashing achieves. 58 58 + 59 59 + For the BCD decoder, pre-computing all prime implicants across the 7 outputs, then identifying which implicants cover minterms in multiple outputs, creates a covering problem where selecting shared implicants has lower cost-per-coverage than output-specific terms. 60 60 + 61 61 + ## Implementation architecture: PySAT with PyEDA preprocessing 62 62 + 63 63 + For a custom solver targeting the 23-input baseline, the recommended stack is **PySAT** for SAT/MaxSAT solving combined with **PyEDA** for Boolean function manipulation and Espresso-based preprocessing. Both libraries are pip-installable and provide production-quality implementations. 64 64 + 65 65 + **Phase 1: Generate prime implicants and baseline** 66 66 + ```python 67 67 + from pyeda.inter import * 68 68 + from pyeda.boolalg.minimization import espresso_tts 69 69 + 70 70 + # Define all 7 segments with don't cares (positions 10-15) 71 71 + X = exprvars('x', 4) 72 72 + segments = { 73 73 + 'a': truthtable(X, "1011011111------"), 74 74 + 'b': truthtable(X, "1111100111------"), 75 75 + 'c': truthtable(X, "1110111111------"), 76 76 + 'd': truthtable(X, "1011011011------"), 77 77 + 'e': truthtable(X, "1010001010------"), 78 78 + 'f': truthtable(X, "1000111111------"), 79 79 + 'g': truthtable(X, "0011111011------"), 80 80 + } 81 81 + 82 82 + # Joint minimization finds shared terms 83 83 + minimized = espresso_tts(*segments.values()) 84 84 + baseline_cost = sum(count_literals(expr) for expr in minimized) 85 85 + ``` 86 86 + 87 87 + **Phase 2: MaxSAT formulation for gate input minimization** 88 88 + ```python 89 89 + from pysat.formula import WCNF 90 90 + from pysat.examples.rc2 import RC2 91 91 + 92 92 + def minimize_gate_inputs(prime_implicants, minterms_per_output): 93 93 + wcnf = WCNF() 94 94 + var_counter = 1 95 95 + p_var = {} # p_var[i] = "implicant i is selected" 96 96 + 97 97 + # Create variables for each prime implicant 98 98 + for i, impl in enumerate(prime_implicants): 99 99 + p_var[i] = var_counter 100 100 + var_counter += 1 101 101 + 102 102 + # Hard constraints: every minterm of every output must be covered 103 103 + for output_idx, minterms in enumerate(minterms_per_output): 104 104 + for m in minterms: 105 105 + covering = [p_var[i] for i, impl in enumerate(prime_implicants) 106 106 + if impl.covers(m, output_idx)] 107 107 + if covering: 108 108 + wcnf.append(covering) # At least one must be selected 109 109 + 110 110 + # Soft constraints: minimize total literals (gate inputs) 111 111 + for i, impl in enumerate(prime_implicants): 112 112 + literal_count = impl.num_literals() 113 113 + # Penalize selecting this implicant by its literal cost 114 114 + wcnf.append([-p_var[i]], weight=literal_count) 115 115 + 116 116 + with RC2(wcnf) as solver: 117 117 + model = solver.compute() 118 118 + return solver.cost, extract_solution(model, prime_implicants, p_var) 119 119 + ``` 120 120 + 121 121 + **Phase 3: SAT-based exact synthesis for sub-problems** 122 122 + For individual segments or small groups, exact synthesis can find provably optimal implementations: 123 123 + 124 124 + ```python 125 125 + def exact_synthesis_segment(truth_table, max_gates=10): 126 126 + """Find minimum-gate circuit for single output.""" 127 127 + for r in range(1, max_gates + 1): 128 128 + cnf = encode_circuit(truth_table, num_gates=r) 129 129 + with Solver(bootstrap_with=cnf) as s: 130 130 + if s.solve(): 131 131 + return decode_circuit(s.get_model(), r) 132 132 + return None 133 133 + ``` 134 134 + 135 135 + ## Cardinality constraints for bounding gate inputs 136 136 + 137 137 + When encoding "total gate inputs ≤ k" as CNF, **Sinz's sequential counter** is optimal in practice. For at-most-k constraints over n variables: 138 138 + 139 139 + ``` 140 140 + Auxiliary variables: s_{i,j} for i=1..n, j=1..k 141 141 + Meaning: s_{i,j} = "sum of x_1..x_i >= j" 142 142 + 143 143 + Clauses: 144 144 + ¬x_1 ∨ s_{1,1} (initialize counter) 145 145 + ¬s_{i-1,j} ∨ s_{i,j} (monotonicity) 146 146 + ¬x_i ∨ ¬s_{i-1,j-1} ∨ s_{i,j} (increment counter) 147 147 + ¬x_i ∨ ¬s_{i-1,k} (overflow = UNSAT) 148 148 + ``` 149 149 + 150 150 + This encoding uses O(n·k) clauses and auxiliary variables, enabling efficient propagation. PySAT's `pysat.card` module provides built-in implementations. 151 151 + 152 152 + ## Concrete pseudocode for the complete solver 153 153 + 154 154 + ```python 155 155 + class BCDTo7SegmentSolver: 156 156 + def __init__(self): 157 157 + self.implicants = [] 158 158 + self.outputs = ['a', 'b', 'c', 'd', 'e', 'f', 'g'] 159 159 + 160 160 + def solve(self, target_cost=22): 161 161 + # Step 1: Generate all prime implicants with output tags 162 162 + self.generate_multi_output_primes() 163 163 + 164 164 + # Step 2: Compute shared coverage matrix 165 165 + coverage = self.build_coverage_matrix() 166 166 + 167 167 + # Step 3: MaxSAT optimization for minimum cost cover 168 168 + solution, cost = self.maxsat_cover(coverage, target_cost) 169 169 + 170 170 + # Step 4: If still above target, try multi-level factoring 171 171 + if cost > target_cost: 172 172 + solution = self.factor_common_subexpressions(solution) 173 173 + cost = self.compute_cost(solution) 174 174 + 175 175 + return solution, cost 176 176 + 177 177 + def generate_multi_output_primes(self): 178 178 + """Generate prime implicants tagged with output membership.""" 179 179 + # Use Quine-McCluskey with output tags 180 180 + # Each implicant carries 7-bit tag indicating which outputs it covers 181 181 + for minterm_idx in range(10): # BCD 0-9 182 182 + for output_idx, segment in enumerate(self.outputs): 183 183 + if self.segment_active(segment, minterm_idx): 184 184 + # Add to on-set for this output 185 185 + pass 186 186 + # Merge compatible minterms, tracking output tags 187 187 + # Stop when no more merging possible (prime implicants) 188 188 + 189 189 + def maxsat_cover(self, coverage, target): 190 190 + """Weighted MaxSAT: minimize sum of selected implicant costs.""" 191 191 + wcnf = WCNF() 192 192 + 193 193 + # Hard: each (output, minterm) pair must be covered 194 194 + for out_idx in range(7): 195 195 + for minterm in self.on_set[out_idx]: 196 196 + clause = [self.impl_var(i) for i in coverage[out_idx][minterm]] 197 197 + wcnf.append(clause) 198 198 + 199 199 + # Soft: penalty for each implicant = its literal count 200 200 + for i, impl in enumerate(self.implicants): 201 201 + wcnf.append([-self.impl_var(i)], weight=impl.cost) 202 202 + 203 203 + with RC2(wcnf) as solver: 204 204 + model = solver.compute() 205 205 + return self.decode(model), solver.cost 206 206 + ``` 207 207 + 208 208 + ## Known bounds and what to expect 209 209 + 210 210 + Standard two-level implementations achieve **27-35 gate inputs** without sharing. Espresso joint minimization typically reaches **22-25 inputs**. SAT-based exact synthesis with full multi-output sharing has achieved **18-21 inputs** for this problem in synthesis competitions. The theoretical lower bound based on information content and required discriminations is approximately **15-17 inputs**, though achieving this may require exotic gate types (XOR, majority gates) not available in standard AND/OR/NOT libraries. 211 211 + 212 212 + For a solver using AND, OR, NOT gates with full sharing optimization, expect to achieve **19-21 gate inputs**—comfortably beating the 23-input baseline by 10-15%. Adding XOR gates to the library can potentially save 2-3 additional inputs due to the checkerboard patterns in some segment truth tables. 213 213 + 214 214 + ## Recommended development sequence 215 215 + 216 216 + Start with PyEDA's Espresso wrapper to establish a working baseline in under 50 lines of Python. This validates the truth table encoding and provides a cost reference. Next, implement the MaxSAT covering formulation using PySAT's WCNF and RC2—this typically achieves 2-4 input reduction over Espresso alone. Finally, for provable optimality, implement the full SAT encoding with selection variables for gate topology. The 4-input, 7-output size makes exhaustive search tractable in seconds to minutes. 217 217 + 218 218 + The combination of algebraic preprocessing (kernel extraction for identifying shared terms), MaxSAT optimization (selecting minimum-cost covers), and optional SAT-based exact synthesis (for critical sub-circuits) provides a robust architecture that consistently beats heuristic-only approaches on small multi-output functions like the BCD to 7-segment decoder.

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