dunkirk.sh
optimizing a gate level bcm to the end of the earth and back
Show complementary inputs as free in gate diagram
Input complements (A', B', C', D') are now shown as separate input
nodes rather than through inverter gates, since they're available
for free in the target technology.
- True inputs shown in light blue
- Complement inputs shown in light cyan
- No NOT gates in the diagram
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
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bcd_optimization/export.py
+32
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bcd_optimization/export.py
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Render with: dot -Tpng circuit.dot -o circuit.png
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Or: dot -Tsvg circuit.dot -o circuit.svg
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Args:
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result: The synthesis result
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title: Title for the diagram
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lines.append(' fontsize=16;')
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lines.append(' rankdir=LR;')
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lines.append(' splines=ortho;')
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lines.append(' nodesep=0.4;')
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lines.append(' ranksep=0.8;')
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lines.append("")
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# Input nodes
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lines.append(" // Inputs")
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lines.append(' subgraph cluster_inputs {')
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lines.append(' label="Inputs";')
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lines.append(' style=dashed;')
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lines.append(' color=gray;')
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for var in ['A', 'B', 'C', 'D']:
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lines.append(f' {var} [shape=circle, style=filled, fillcolor=lightblue, label="{var}"];')
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lines.append(' }')
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lines.append("")
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# Inverters for negated inputs
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lines.append(" // Inverters")
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used_negations = set()
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for impl, _ in result.shared_implicants:
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for i, var in enumerate(['A', 'B', 'C', 'D']):
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bit = 1 << (3 - i)
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if impl.mask & bit and not ((impl.value >> (3 - i)) & 1):
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used_negations.add(var)
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# Check non-shared implicants too
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for segment in SEGMENT_NAMES:
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if segment not in result.implicants_by_output:
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continue
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for impl in result.implicants_by_output[segment]:
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is_shared = any(impl == si for si, _ in result.shared_implicants)
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if is_shared:
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continue
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for i, var in enumerate(['A', 'B', 'C', 'D']):
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bit = 1 << (3 - i)
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if impl.mask & bit and not ((impl.value >> (3 - i)) & 1):
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used_negations.add(var)
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for var in sorted(used_negations):
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lines.append(f' not_{var} [shape=invtriangle, style=filled, fillcolor=lightyellow, label="NOT", width=0.4, height=0.4];')
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lines.append(f' {var} -> not_{var};')
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lines.append("")
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# AND gates for shared product terms
···
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for i, (impl, outputs) in enumerate(result.shared_implicants):
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term_label = impl.to_expr_str()
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outputs_str = ",".join(outputs)
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lines.append(f' and_{i} [shape=polygon, sides=4, style=filled, fillcolor=lightgreen, label="AND\\n{term_label}"];')
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lines.append(' }')
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lines.append("")
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if (impl.value >> (3 - j)) & 1:
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lines.append(f' {var} -> and_{i};')
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else:
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lines.append(f' not_{var} -> and_{i};')
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lines.append("")
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# OR gates for outputs
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if is_shared:
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continue
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# Single literal - direct connection
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if impl.num_literals == 1:
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for j, var in enumerate(['A', 'B', 'C', 'D']):
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bit = 1 << (3 - j)
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if (impl.value >> (3 - j)) & 1:
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lines.append(f' {var} -> or_{segment};')
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else:
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lines.append(f' not_{var} -> or_{segment};')
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else:
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# Multi-literal non-shared AND
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term_label = impl.to_expr_str()
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if (impl.value >> (3 - j)) & 1:
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lines.append(f' {var} -> {and_name};')
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else:
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lines.append(f' not_{var} -> {and_name};')
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lines.append(f' {and_name} -> or_{segment};')
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nonshared_idx += 1
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lines.append("")
···
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Render with: dot -Tpng circuit.dot -o circuit.png
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Or: dot -Tsvg circuit.dot -o circuit.svg
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Note: Inputs and their complements (A, A', B, B', C, C', D, D') are
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shown as free inputs - no inverter gates are needed.
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Args:
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result: The synthesis result
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title: Title for the diagram
···
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lines.append(' fontsize=16;')
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lines.append(' rankdir=LR;')
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lines.append(' splines=ortho;')
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lines.append(' nodesep=0.3;')
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lines.append(' ranksep=0.8;')
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lines.append("")
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# Determine which inputs (true and complement) are actually used
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used_inputs = set() # Will contain 'A', 'nA', 'B', 'nB', etc.
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for impl, _ in result.shared_implicants:
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for i, var in enumerate(['A', 'B', 'C', 'D']):
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bit = 1 << (3 - i)
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if impl.mask & bit:
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if (impl.value >> (3 - i)) & 1:
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used_inputs.add(var)
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else:
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used_inputs.add(f"n{var}")
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for segment in SEGMENT_NAMES:
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if segment not in result.implicants_by_output:
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continue
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for impl in result.implicants_by_output[segment]:
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for i, var in enumerate(['A', 'B', 'C', 'D']):
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bit = 1 << (3 - i)
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if impl.mask & bit:
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if (impl.value >> (3 - i)) & 1:
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used_inputs.add(var)
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else:
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used_inputs.add(f"n{var}")
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# Input nodes (true and complement forms are free)
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lines.append(" // Inputs (active high and low available for free)")
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lines.append(' subgraph cluster_inputs {')
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lines.append(' label="Inputs";')
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lines.append(' style=dashed;')
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lines.append(' color=gray;')
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for var in ['A', 'B', 'C', 'D']:
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if var in used_inputs:
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lines.append(f' {var} [shape=circle, style=filled, fillcolor=lightblue, label="{var}"];')
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if f"n{var}" in used_inputs:
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lines.append(f' n{var} [shape=circle, style=filled, fillcolor=lightcyan, label="{var}\'"];')
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lines.append(' }')
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lines.append("")
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# AND gates for shared product terms
···
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for i, (impl, outputs) in enumerate(result.shared_implicants):
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term_label = impl.to_expr_str()
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lines.append(f' and_{i} [shape=polygon, sides=4, style=filled, fillcolor=lightgreen, label="AND\\n{term_label}"];')
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lines.append(' }')
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lines.append("")
···
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if (impl.value >> (3 - j)) & 1:
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lines.append(f' {var} -> and_{i};')
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else:
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lines.append(f' n{var} -> and_{i};')
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lines.append("")
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# OR gates for outputs
···
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if is_shared:
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continue
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# Single literal - direct connection from input
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if impl.num_literals == 1:
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for j, var in enumerate(['A', 'B', 'C', 'D']):
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bit = 1 << (3 - j)
···
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if (impl.value >> (3 - j)) & 1:
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lines.append(f' {var} -> or_{segment};')
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else:
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lines.append(f' n{var} -> or_{segment};')
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else:
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# Multi-literal non-shared AND
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term_label = impl.to_expr_str()
···
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if (impl.value >> (3 - j)) & 1:
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lines.append(f' {var} -> {and_name};')
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else:
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lines.append(f' n{var} -> {and_name};')
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lines.append(f' {and_name} -> or_{segment};')
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nonshared_idx += 1
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lines.append("")