tsiry-sandratraina.com
A modern Music Player Daemon based on Rockbox open source high quality audio player
libadwaita
audio
rust
zig
deno
mpris
rockbox
mpd
Add beginning of DSP code (done by Catalin Patulea), but don't enable it yet as there's no C54xx compiler in the toolchain yet..
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17547 a1c6a512-1295-4272-9138-f99709370657
+55
firmware/target/arm/tms320dm320/dsp/Makefile
+55
firmware/target/arm/tms320dm320/dsp/Makefile
···
1
+
# __________ __ ___.
2
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# Open \______ \ ____ ____ | | _\_ |__ _______ ___
3
+
# Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
4
+
# Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
5
+
# Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
6
+
# \/ \/ \/ \/ \/
7
+
# $Id: Makefile 12058 2007-01-18 00:46:52Z dave $
8
+
#
9
+
10
+
# http://daniel.haxx.se/blog/2007/11/18/free-to-use-compiler-from-ti/
11
+
CC = cl500
12
+
LD = lnk500
13
+
CFLAGS = $(BUILDDATE)
14
+
# There's more in linker.cmd.
15
+
LDFLAGS = -w
16
+
17
+
OBJS = arm.obj main.obj vectors.obj dma.obj
18
+
19
+
ifeq ($(findstring -DCREATIVE_ZV,$(TARGET)), -DCREATIVE_ZV)
20
+
OBJS += aic23.obj
21
+
else
22
+
OBJS += tsc2100.obj
23
+
endif
24
+
25
+
OBJS := $(patsubst %.obj, $(OBJDIR)/%.obj, $(OBJS))
26
+
27
+
all: $(BUILDDIR)/dsp-image.h
28
+
29
+
clean:
30
+
$(call PRINTS,cleaning DSP firmware)rm -f $(OBJS) $(OBJDIR)/dsp-image.out $(OBJDIR)/dsp-image.xml
31
+
32
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$(BUILDDIR)/dsp-image.h: $(OBJS) linker.cmd
33
+
$(call PRINTS,LNK500 dsp-image.out)lnk500 $(LDFLAGS) -o $(OBJDIR)/dsp-image.out $^
34
+
$(call PRINTS,OFD500+XML2H $(@F))ofd500 -x -o /dev/stdout $(OBJDIR)/dsp-image.out | python $(TOOLSDIR)/xml2h.py $(OBJDIR)/dsp-image.xml > $@
35
+
36
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$(OBJDIR)/%.obj: %.asm
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$(SILENT)mkdir -p $(dir $@)
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+
$(call PRINTS,CL500 $<)$(CC) $(CFLAGS) -fr $(dir $@) $<
39
+
40
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$(OBJDIR)/%.obj: %.c
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$(SILENT)mkdir -p $(dir $@)
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+
$(call PRINTS,CL500 $<)$(CC) $(CFLAGS) -fr $(dir $@) $<
43
+
44
+
$(OBJDIR)/arm.obj: arm.c arm.h registers.h ipc.h
45
+
46
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$(OBJDIR)/main.obj: main.c arm.h registers.h ipc.h dma.h audio.h
47
+
48
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$(OBJDIR)/aic23.obj: aic23.c audio.h registers.h
49
+
50
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$(OBJDIR)/tsc2100.obj: tsc2100.c audio.h registers.h
51
+
52
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$(OBJDIR)/dma.obj: dma.c dma.h registers.h ipc.h
53
+
54
+
# For PRINTS.
55
+
include $(TOOLSDIR)/make.inc
+58
firmware/target/arm/tms320dm320/dsp/aic23.c
+58
firmware/target/arm/tms320dm320/dsp/aic23.c
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Maurus Cuelenaere
11
+
*
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* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#include "audio.h"
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+
#include "registers.h"
22
+
23
+
/* based on http://archopen.svn.sourceforge.net/viewvc/archopen/ArchOpen/trunk/libdsp/aic23.c?revision=213&view=markup */
24
+
void audiohw_init(void)
25
+
{
26
+
/* port config */
27
+
#if 0
28
+
SPCR10 = 0; /* DLB = 0 ** RJUST = 0 ** CLKSTP = 0 ** DXENA = 0 ** ABIS = 0 ** RINTM = 0 ** RSYNCER = 0 ** RFULL = 0 ** RRDY = 0 ** RRST = 0 */
29
+
SPCR20 = (1 << 9); /* FREE = 1 ** SOFT = 0 ** FRST = 0 ** GRST = 0 ** XINTM = 0 ** XSYNCER = 0 ** XEMPTY = 0 ** XRDY = 0 ** XRST = 0 */
30
+
RCR10 = (1 << 8) | (2 << 5); /* RFRLEN1 = 1 ** RWDLEN1 = 2 */
31
+
RCR20 = 0; /* RPHASE = 0 ** RFRLEN2 = 0 ** RWDLEN2 = 0 ** RCOMPAND = 0 ** RFIG = 0 ** RDATDLY = 0 */
32
+
XCR10 = (1 << 8) | (2 << 5); /* XFRLEN1 = 1 ** XWDLEN1 = 2 */
33
+
XCR20 = 0; /* XPHASE = 0 ** XFRLEN2 = 0 ** XWDLEN2 = 0 ** XCOMPAND = 0 ** XFIG = 0 ** XDATDLY = 0 */
34
+
SRGR10 = 0; /* FWID = 0 ** CLKGDV = 0 */
35
+
SRGR20 = 0; /* FREE = 0 ** CLKSP = 0 ** CLKSM = 0 ** FSGM = 0 ** FPER = 0 */
36
+
PCR0 = (1 << 1) | 1; /* IDLEEN = 0 ** XIOEN = 0 ** RIOEN = 0 ** FSXM = 0 ** FSRM = 0 ** SCLKME = 0 ** CLKSSTAT = 0 ** DXSTAT = 0 ** DRSTAT = 0 ** CLKXM = 0 ** CLKRM = 0 ** FSXP = 0 ** FSRP = 0 ** CLKXP = 1 ** CLKRP = 1 */
37
+
#else
38
+
SPCR10 = 0;
39
+
SPCR20 = 0x0200; /* SPCR : free running mode */
40
+
41
+
RCR10 = 0x00A0;
42
+
RCR20 = 0x00A1; /* RCR : 32 bit receive data length */
43
+
44
+
XCR10 = 0x00A0;
45
+
XCR20 = 0x00A0; /* XCR : 32 bit transmit data length */
46
+
47
+
SRGR10 = 0;
48
+
SRGR20 = 0x3000; /* SRGR 1 & 2 */
49
+
50
+
PCR0 = 0x000E - 8; /* PCR : FSX, FSR active low, external FS/CLK source */
51
+
#endif
52
+
}
53
+
54
+
void audiohw_postinit(void)
55
+
{
56
+
/* Trigger first XEVT0 */
57
+
SPCR20 |= 1;
58
+
}
+49
firmware/target/arm/tms320dm320/dsp/arm.c
+49
firmware/target/arm/tms320dm320/dsp/arm.c
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#include <stdio.h>
21
+
#include "arm.h"
22
+
#include "registers.h"
23
+
#include "ipc.h"
24
+
25
+
volatile struct ipc_message status;
26
+
27
+
volatile int acked;
28
+
interrupt void handle_int0(void) {
29
+
IFR = 1;
30
+
acked = 1;
31
+
}
32
+
33
+
void debugf(const char *fmt, ...) {
34
+
va_list args;
35
+
va_start(args, fmt);
36
+
status.msg = MSG_DEBUGF;
37
+
vsnprintf((char *)status.payload.debugf.buffer, sizeof(status), fmt, args);
38
+
va_end(args);
39
+
40
+
/* Wait until ARM has picked up data. */
41
+
acked = 0;
42
+
int_arm();
43
+
while (!acked) {
44
+
/* IDLE alone never seems to wake up :( */
45
+
asm(" IDLE 1");
46
+
asm(" NOP");
47
+
}
48
+
acked = 2;
49
+
}
+32
firmware/target/arm/tms320dm320/dsp/arm.h
+32
firmware/target/arm/tms320dm320/dsp/arm.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#ifndef ARM_H
21
+
#define ARM_H
22
+
#include "registers.h"
23
+
24
+
extern volatile struct ipc_message status;
25
+
26
+
void debugf(const char *fmt, ...);
27
+
28
+
inline void int_arm(void) {
29
+
CP_INTC = 1 << 3;
30
+
}
31
+
32
+
#endif
+26
firmware/target/arm/tms320dm320/dsp/audio.h
+26
firmware/target/arm/tms320dm320/dsp/audio.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Maurus Cuelenaere
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#ifndef AUDIO_H
21
+
#define AUDIO_H
22
+
23
+
void audiohw_init(void);
24
+
void audiohw_postinit(void);
25
+
26
+
#endif
+87
firmware/target/arm/tms320dm320/dsp/dma.c
+87
firmware/target/arm/tms320dm320/dsp/dma.c
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
* Copyright (C) 2008 by Maurus Cuelenaere
12
+
*
13
+
* All files in this archive are subject to the GNU General Public License.
14
+
* See the file COPYING in the source tree root for full license agreement.
15
+
*
16
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
17
+
* KIND, either express or implied.
18
+
*
19
+
****************************************************************************/
20
+
21
+
#include "registers.h"
22
+
#include "arm.h"
23
+
#include "dma.h"
24
+
25
+
/* This is placed at the right (aligned) address using linker.cmd. */
26
+
#pragma DATA_SECTION (data, ".dma")
27
+
signed short data[PCM_SIZE / 2];
28
+
29
+
/* Filled in by loader. */
30
+
unsigned short sdem_addrh;
31
+
unsigned short sdem_addrl;
32
+
33
+
interrupt void handle_dma0(void) {
34
+
unsigned long sdem_addr;
35
+
/* Byte offset to half-buffer locked by DMA0.
36
+
0 for top, PCM_SIZE/2(0x4000) for bottom */
37
+
unsigned short dma0_locked;
38
+
unsigned short dma0_unlocked;
39
+
40
+
IFR = 1 << 6;
41
+
42
+
/* DMSRC0 is the beginning of the DMA0-locked SARAM half-buffer. */
43
+
DMSA = 0x00 /* DMSRC0 */;
44
+
dma0_locked = (DMSDN << 1) & (PCM_SIZE / 2);
45
+
dma0_unlocked = dma0_locked ^ (PCM_SIZE / 2);
46
+
47
+
/* ARM, decode into same half, in SDRAM. */
48
+
status.msg = MSG_REFILL;
49
+
status.payload.refill.topbottom = dma0_locked;
50
+
int_arm();
51
+
52
+
/* DMAC, copy opposite halves from SDRAM to SARAM. */
53
+
sdem_addr = ((unsigned long)sdem_addrh << 16 | sdem_addrl) + dma0_unlocked;
54
+
SDEM_ADDRL = sdem_addr & 0xffff;
55
+
SDEM_ADDRH = sdem_addr >> 16;
56
+
DSP_ADDRL = (unsigned short)data + (dma0_unlocked >> 1);
57
+
DSP_ADDRH = 0;
58
+
DMA_SIZE = PCM_SIZE / 2;
59
+
DMA_CTRL = 0;
60
+
61
+
status.payload.refill._DMA_TRG = DMA_TRG;
62
+
status.payload.refill._SDEM_ADDRH = SDEM_ADDRH;
63
+
status.payload.refill._SDEM_ADDRL = SDEM_ADDRL;
64
+
status.payload.refill._DSP_ADDRH = DSP_ADDRH;
65
+
status.payload.refill._DSP_ADDRL = DSP_ADDRL;
66
+
67
+
DMA_TRG = 1;
68
+
}
69
+
70
+
interrupt void handle_dmac(void) {
71
+
IFR = 1 << 11;
72
+
}
73
+
74
+
void dma_init(void) {
75
+
/* Configure DMA */
76
+
DMSFC0 = 2 << 12 | 1 << 11; /* Event XEVT0, 32-bit transfers, 0 frame count */
77
+
DMMCR0 = 1 << 14 | 1 << 13 | /* Interrupts generated, Half and full buffer */
78
+
1 << 12 | 1 << 8 | 1 << 6 | 1; /* ABU mode,
79
+
From data space with postincrement,
80
+
To data space with no mod */
81
+
DMSRC0 = (unsigned short)&data;
82
+
DMDST0 = (unsigned short)&DXR20; /* First of two-word register pair */
83
+
DMCTR0 = sizeof(data);
84
+
85
+
/* Run, Rudolf, run! (with DMA0 interrupts) */
86
+
DMPREC = 2 << 6 | 1;
87
+
}
+28
firmware/target/arm/tms320dm320/dsp/dma.h
+28
firmware/target/arm/tms320dm320/dsp/dma.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Maurus Cuelenaere
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#ifndef DMA_H
21
+
#define DMA_H
22
+
23
+
#include "ipc.h"
24
+
25
+
extern signed short data[PCM_SIZE / 2];
26
+
void dma_init(void);
27
+
28
+
#endif
+69
firmware/target/arm/tms320dm320/dsp/ipc.h
+69
firmware/target/arm/tms320dm320/dsp/ipc.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#ifndef IPC_H
21
+
#define IPC_H
22
+
23
+
/* Inter-Processor Communication */
24
+
25
+
/* Meant to be included by both DSP and ARM code. */
26
+
#ifdef __GNUC__
27
+
/* aligned(2) is VERY IMPORTANT. It ensures gcc generates code with "STRH"
28
+
instead of with "STRB". STRB in the DSP memory range is broken because
29
+
the HPI is in 16-bit mode. */
30
+
#define PACKED __attribute__((packed)) __attribute__((aligned (2)))
31
+
#else
32
+
#define PACKED
33
+
#endif
34
+
35
+
#define PCM_SIZE 32768 /* bytes */
36
+
37
+
struct sdram_buffer {
38
+
unsigned long addr;
39
+
unsigned short bytes;
40
+
} PACKED;
41
+
42
+
#define SDRAM_BUFFERS 4
43
+
44
+
struct ipc_message {
45
+
unsigned short msg;
46
+
union {
47
+
#define MSG_INIT 1
48
+
struct msg_init {
49
+
unsigned short sdem_addrl;
50
+
unsigned short sdem_addrh;
51
+
} init PACKED;
52
+
#define MSG_DEBUGF 2
53
+
struct {
54
+
short buffer[80];
55
+
} debugf PACKED;
56
+
#define MSG_REFILL 3
57
+
struct {
58
+
unsigned short topbottom; /* byte offset to unlocked half-buffer */
59
+
60
+
unsigned short _DMA_TRG;
61
+
unsigned short _SDEM_ADDRH;
62
+
unsigned short _SDEM_ADDRL;
63
+
unsigned short _DSP_ADDRH;
64
+
unsigned short _DSP_ADDRL;
65
+
unsigned short _DMA_SIZE;
66
+
} refill PACKED;
67
+
} payload PACKED;
68
+
} PACKED;
69
+
#endif
+29
firmware/target/arm/tms320dm320/dsp/linker.cmd
+29
firmware/target/arm/tms320dm320/dsp/linker.cmd
···
1
+
-c
2
+
-x
3
+
-stack 0x1000
4
+
-heap 0x100
5
+
-l rts500.lib
6
+
7
+
MEMORY
8
+
{
9
+
PAGE 0:
10
+
DARAM: origin = 80h, length = 7F80h
11
+
SARAM: origin = 8000h, length = 4000h
12
+
}
13
+
14
+
SECTIONS
15
+
{
16
+
.text PAGE 0
17
+
.cinit PAGE 0
18
+
.switch PAGE 0
19
+
20
+
.bss PAGE 0
21
+
.const PAGE 0
22
+
.sysmem PAGE 0
23
+
.stack PAGE 0
24
+
25
+
.vectors : PAGE 0 load = 7F80h
26
+
27
+
/* DMA buffers for ABU mode must start on a 2*size boundary. */
28
+
.dma : PAGE 0 load = 0x8000
29
+
}
+145
firmware/target/arm/tms320dm320/dsp/main.c
+145
firmware/target/arm/tms320dm320/dsp/main.c
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#include "registers.h"
21
+
#include "arm.h"
22
+
#include "ipc.h"
23
+
#include "dma.h"
24
+
#include "audio.h"
25
+
#include <math.h>
26
+
27
+
void main(void) {
28
+
register int i;
29
+
register signed short *p;
30
+
31
+
TCR = 1 << 4; /* Stop the timer. */
32
+
IMR = 0xffff; /* Unmask all interrupts. */
33
+
IFR = IFR; /* Clear all pending interrupts. */
34
+
asm(" rsbx INTM"); /* Globally enable interrupts. */
35
+
36
+
audiohw_init();
37
+
38
+
dma_init();
39
+
40
+
audiohw_postinit();
41
+
42
+
#if 0
43
+
for (i = 0; i < 32; i++)
44
+
{
45
+
double ratio = ((double)i)/32.0;
46
+
double rad = 3.0*3.141592*ratio;
47
+
double normal = sin(rad);
48
+
double scaled = 32767.0*(normal);
49
+
data[2*i + 0] = -(signed short)scaled;
50
+
data[2*i + 1] = (signed short)scaled;
51
+
}
52
+
53
+
debugf("starting write");
54
+
55
+
i = 0;
56
+
p = data;
57
+
SPSA0 = 0x01;
58
+
for (;;) {
59
+
while ((SPSD0 & (1 << 1)) == 0);
60
+
DXR20 = *p++; // left channel
61
+
DXR10 = *p++; // right channel
62
+
if (++i == 32)
63
+
{
64
+
p = data;
65
+
i = 0;
66
+
}
67
+
}
68
+
#endif
69
+
debugf("DSP inited...");
70
+
71
+
for (;;) {
72
+
asm(" IDLE 1");
73
+
asm(" NOP");
74
+
}
75
+
}
76
+
77
+
/* Obsoleted/testing snippets: */
78
+
#ifdef REMAP_VECTORS
79
+
/* Remap vectors to 0x3F80 (set in linker.cmd). */
80
+
PMST = (PMST & 0x7f) | 0x3F80;
81
+
82
+
/* Make sure working interrupts aren't a fluke. */
83
+
memset((unsigned short *)0x7f80, 0, 0x80);
84
+
#endif
85
+
86
+
#ifdef DATA_32_SINE
87
+
for (i = 0; i < 32; i++) {
88
+
double ratio = ((double)i)/32.0;
89
+
double rad = 3.0*3.141592*ratio;
90
+
double normal = sin(rad);
91
+
double scaled = 32767.0*(normal);
92
+
data[2*i + 0] = -(signed short)scaled;
93
+
data[2*i + 1] = (signed short)scaled;
94
+
}
95
+
#endif
96
+
97
+
#ifdef MANUAL_TRANSFER
98
+
register signed short *p;
99
+
100
+
debugf("starting write");
101
+
102
+
i = 0;
103
+
p = data;
104
+
SPSA0 = 0x01;
105
+
for (;;) {
106
+
while ((SPSD0 & (1 << 1)) == 0);
107
+
DXR20 = *p++; // left channel
108
+
DXR10 = *p++; // right channel
109
+
if (++i == 32) {
110
+
p = data;
111
+
i = 0;
112
+
}
113
+
}
114
+
#endif
115
+
116
+
#ifdef INIT_MSG
117
+
/* Copy codec init data (before debugf, which clobbers status). */
118
+
if (status.msg != MSG_INIT) {
119
+
debugf("No init message (%04x: %04x %04x %04x %04x instead)",
120
+
(unsigned short)&status,
121
+
((unsigned short *)&status)[0],
122
+
((unsigned short *)&status)[1],
123
+
((unsigned short *)&status)[2],
124
+
((unsigned short *)&status)[3]);
125
+
return;
126
+
}
127
+
128
+
memcpy(&init, (void *)&status.payload.init, sizeof(init));
129
+
#endif
130
+
131
+
#ifdef IPC_SIZES
132
+
debugf("sizeof(ipc_message)=%uw offset(ipc_message.payload)=%uw",
133
+
sizeof(struct ipc_message), (int)&((struct ipc_message*)0)->payload);
134
+
#endif
135
+
136
+
#ifdef VERBOSE_INIT
137
+
debugf("codec started with PCM at SDRAM offset %04x:%04x",
138
+
sdem_addrh, sdem_addrl);
139
+
#endif
140
+
141
+
#ifdef SPIKE_DATA
142
+
for (i = 0; i < 0x2000; i++) {
143
+
data[2*i ] = data[2*i+1] = ((i % 32) == 0) * 32767;
144
+
}
145
+
#endif
+93
firmware/target/arm/tms320dm320/dsp/registers.h
+93
firmware/target/arm/tms320dm320/dsp/registers.h
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#ifndef REGISTERS_H
21
+
#define REGISTERS_H
22
+
23
+
#define C5409_REG(addr) (*(volatile unsigned short *)(addr))
24
+
25
+
/* This is NOT good for reading, only for writing. */
26
+
#define BANKED_REG(spsa, spsd, subaddr) spsa = (subaddr), spsd
27
+
28
+
#define IMR C5409_REG(0x00)
29
+
#define IFR C5409_REG(0x01)
30
+
31
+
#define PMST C5409_REG(0x1D)
32
+
33
+
#define TCR C5409_REG(0x26)
34
+
35
+
/* McBSP 0 (SPRU302 Chapter 2) */
36
+
#define DXR20 C5409_REG(0x22)
37
+
#define DXR10 C5409_REG(0x23)
38
+
#define SPSA0 C5409_REG(0x38)
39
+
#define SPSD0 C5409_REG(0x39)
40
+
#define SPCR10 BANKED_REG(SPSA0, SPSD0, 0x00)
41
+
#define SPCR20 BANKED_REG(SPSA0, SPSD0, 0x01)
42
+
#define RCR10 BANKED_REG(SPSA0, SPSD0, 0x02)
43
+
#define RCR20 BANKED_REG(SPSA0, SPSD0, 0x03)
44
+
#define XCR10 BANKED_REG(SPSA0, SPSD0, 0x04)
45
+
#define XCR20 BANKED_REG(SPSA0, SPSD0, 0x05)
46
+
#define SRGR10 BANKED_REG(SPSA0, SPSD0, 0x06)
47
+
#define SRGR20 BANKED_REG(SPSA0, SPSD0, 0x07)
48
+
#define PCR0 BANKED_REG(SPSA0, SPSD0, 0x0e)
49
+
50
+
/* McBSP 1 */
51
+
#define DXR21 C5409_REG(0x42)
52
+
#define DXR11 C5409_REG(0x43)
53
+
#define SPSA1 C5409_REG(0x48)
54
+
#define SPSD1 C5409_REG(0x49)
55
+
#define SPCR11 BANKED_REG(SPSA1, SPSD1, 0x00)
56
+
#define SPCR21 BANKED_REG(SPSA1, SPSD1, 0x01)
57
+
#define XCR11 BANKED_REG(SPSA1, SPSD1, 0x04)
58
+
#define XCR21 BANKED_REG(SPSA1, SPSD1, 0x05)
59
+
#define PCR1 BANKED_REG(SPSA1, SPSD1, 0x0e)
60
+
61
+
/* DMA */
62
+
#define DMPREC C5409_REG(0x54)
63
+
#define DMSA C5409_REG(0x55)
64
+
#define DMSDI C5409_REG(0x56)
65
+
#define DMSDN C5409_REG(0x57)
66
+
#define DMSRC0 BANKED_REG(DMSA, DMSDN, 0x00)
67
+
#define DMDST0 BANKED_REG(DMSA, DMSDN, 0x01)
68
+
#define DMCTR0 BANKED_REG(DMSA, DMSDN, 0x02)
69
+
#define DMSFC0 BANKED_REG(DMSA, DMSDN, 0x03)
70
+
#define DMMCR0 BANKED_REG(DMSA, DMSDN, 0x04)
71
+
72
+
73
+
/* DM320 */
74
+
ioport unsigned short port280;
75
+
#define CP_INTC port280
76
+
ioport unsigned short port8000;
77
+
#define SDEM_ADDRL port8000
78
+
ioport unsigned short port8001;
79
+
#define SDEM_ADDRH port8001
80
+
ioport unsigned short port8002;
81
+
#define DSP_ADDRL port8002
82
+
ioport unsigned short port8003;
83
+
#define DSP_ADDRH port8003
84
+
ioport unsigned short port8004;
85
+
#define DMA_SIZE port8004
86
+
ioport unsigned short port8005;
87
+
#define DMA_CTRL port8005
88
+
ioport unsigned short port8006;
89
+
#define DMA_TRG port8006
90
+
ioport unsigned short port8007;
91
+
#define DMA_REST port8007
92
+
93
+
#endif
+40
firmware/target/arm/tms320dm320/dsp/tsc2100.c
+40
firmware/target/arm/tms320dm320/dsp/tsc2100.c
···
1
+
/***************************************************************************
2
+
* __________ __ ___.
3
+
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
* \/ \/ \/ \/ \/
8
+
* $Id$
9
+
*
10
+
* Copyright (C) 2008 by Catalin Patulea
11
+
*
12
+
* All files in this archive are subject to the GNU General Public License.
13
+
* See the file COPYING in the source tree root for full license agreement.
14
+
*
15
+
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
* KIND, either express or implied.
17
+
*
18
+
****************************************************************************/
19
+
20
+
#include "audio.h"
21
+
#include "registers.h"
22
+
23
+
void audiohw_init(void)
24
+
{
25
+
/* Configure McBSP */
26
+
SPCR10 = 0; /* Receiver reset */
27
+
SPCR20 = 3 << 4; /* Rate gen disabled, RINT=XSYNCERR, TX disabled for now */
28
+
PCR0 = 1 << 1; /* Serial port pins, external frame sync, external clock,
29
+
frame sync FSX is active-high,
30
+
TX data sampled on falling clock */
31
+
XCR10 = 0x00a0; /* 1 word per frame, 32 bits per word */
32
+
XCR20 = 0; /* Single-phase, unexpected frame pulse restarts xfer,
33
+
0-bit data delay */
34
+
}
35
+
36
+
void audiohw_postinit(void)
37
+
{
38
+
/* Trigger first XEVT0 */
39
+
SPCR20 |= 1;
40
+
}
+143
firmware/target/arm/tms320dm320/dsp/vectors.asm
+143
firmware/target/arm/tms320dm320/dsp/vectors.asm
···
1
+
;* Copyright (c) 2007, C.P.R. Baaij
2
+
;* All rights reserved.
3
+
;*
4
+
;* Redistribution and use in source and binary forms, with or without
5
+
;* modification, are permitted provided that the following conditions are met:
6
+
;* * Redistributions of source code must retain the above copyright
7
+
;* notice, this list of conditions and the following disclaimer.
8
+
;* * Redistributions in binary form must reproduce the above copyright
9
+
;* notice, this list of conditions and the following disclaimer in the
10
+
;* documentation and/or other materials provided with the distribution.
11
+
;*
12
+
;* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
13
+
;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
14
+
;* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15
+
;* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16
+
;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17
+
;* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
18
+
;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
19
+
;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20
+
;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21
+
;* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22
+
23
+
;*-----------------------------------------------------------------------------*
24
+
;* Interrupt Vectors *
25
+
;*-----------------------------------------------------------------------------*
26
+
.mmregs
27
+
28
+
; External Functions
29
+
.global _handle_int0
30
+
.global _c_int00
31
+
.global _handle_dma0
32
+
.global _handle_dmac
33
+
34
+
.sect ".vectors"
35
+
; Reset Interrupt
36
+
RS_V: BD _c_int00
37
+
NOP
38
+
NOP
39
+
40
+
; Non-Maskable Interrupt
41
+
NMI_V: RETE
42
+
NOP
43
+
NOP
44
+
NOP
45
+
46
+
; Software Interrupts
47
+
SINt17_V: .space 4*16
48
+
SINt18_V: .space 4*16
49
+
SINt19_V: .space 4*16
50
+
SINt20_V: .space 4*16
51
+
SINt21_V: .space 4*16
52
+
SINt22_V: .space 4*16
53
+
SINt23_V: .space 4*16
54
+
SINt24_V: .space 4*16
55
+
SINt25_V: .space 4*16
56
+
SINt26_V: .space 4*16
57
+
SINt27_V: .space 4*16
58
+
SINt28_V: .space 4*16
59
+
SINt29_V: .space 4*16
60
+
SINt30_V: .space 4*16
61
+
; INT0 - ARM Interrupting DSP via HPIB
62
+
INT0_V: BD _handle_int0
63
+
NOP
64
+
NOP
65
+
; INT1 - Interrupt is generated based on the settings of DSP_SYNC_STATE and
66
+
; DSP_SYNC_MASK register of the coprocessor subsystem or when DSPINT1 bit in
67
+
; CP_INTC is set.
68
+
INT1_V: RETE
69
+
NOP
70
+
NOP
71
+
NOP
72
+
; INT2 - Interrupt is generated when DSPINT2 bit in CP_INTC register of the
73
+
; coprocessor subsystem is set.
74
+
INT2_V: RETE
75
+
NOP
76
+
NOP
77
+
NOP
78
+
; Timer Interrupt
79
+
TINT_V: RETE
80
+
NOP
81
+
NOP
82
+
NOP
83
+
; McBSP0 receive interrupt
84
+
BRINT0_V: RETE
85
+
NOP
86
+
NOP
87
+
NOP
88
+
; McBSP0 transmit interrupt
89
+
BXINT0_V: RETE
90
+
NOP
91
+
NOP
92
+
NOP
93
+
; DMA Channel-0 interrupt
94
+
DMAC0_V: BD _handle_dma0
95
+
NOP
96
+
NOP
97
+
; DMA Channel-1 interrupt
98
+
DMAC1_V: RETE
99
+
NOP
100
+
NOP
101
+
NOP
102
+
; INT3 - Interrupt is generated when DSPINT3 bit in CP_INTC register of the
103
+
; coprocessor subsystem is set or on write of any value to BRKPT_TRG
104
+
INT3_V: RETE
105
+
NOP
106
+
NOP
107
+
NOP
108
+
; HPIB HINT to DSP
109
+
HINT_V: RETE
110
+
NOP
111
+
NOP
112
+
NOP
113
+
; BRINT1/DMAC2 McBSP1 receive interrupt
114
+
BRINT1_V: RETE
115
+
NOP
116
+
NOP
117
+
NOP
118
+
; BXINT1/DMAC3 McBSP1 transmit interrupt
119
+
BXINT1_V: RETE
120
+
NOP
121
+
NOP
122
+
NOP
123
+
; DMA Channel-4 interrupt
124
+
DMAC4_V: RETE
125
+
NOP
126
+
NOP
127
+
NOP
128
+
; DMA Channel-5 interrupt
129
+
DMAC5_V: RETE
130
+
NOP
131
+
NOP
132
+
NOP
133
+
; HPIB DMAC interrupt
134
+
HPIB_DMA_V: BD _handle_dmac
135
+
NOP
136
+
NOP
137
+
138
+
; EHIF interrupt to DSP
139
+
EHIV_V: RETE
140
+
NOP
141
+
NOP
142
+
NOP
143
+
.end
+1
-3
tools/scramble.c
+1
-3
tools/scramble.c
···
119
119
"\t-add=X Rockbox generic \"add-up\" checksum format\n"
120
120
"\t (X values: h100, h120, h140, h300, ipco, nano, ipvd, mn2g\n"
121
121
"\t ip3g, ip4g, mini, iax5, iam5, iam3, h10, h10_5gb,\n"
122
-
"\t tpj2, c200, e200, giga, gigs, m100, m500, d2, zvm)\n");
122
+
"\t tpj2, c200, e200, giga, gigs, m100, m500, d2)\n");
123
123
printf("\nNo option results in Archos standard player/recorder format.\n");
124
124
125
125
exit(1);
···
271
271
modelnum = 24;
272
272
else if(!strcmp(&argv[1][5], "iam3"))
273
273
modelnum = 25;
274
-
else if(!strcmp(&argv[1][5], "zvm"))
275
-
modelnum = 26;
276
274
else {
277
275
fprintf(stderr, "unsupported model: %s\n", &argv[1][5]);
278
276
return 2;
+191
tools/xml2h.py
+191
tools/xml2h.py
···
1
+
#!/usr/bin/python
2
+
# __________ __ ___.
3
+
# Open \______ \ ____ ____ | | _\_ |__ _______ ___
4
+
# Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5
+
# Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6
+
# Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7
+
# \/ \/ \/ \/ \/
8
+
# $Id$
9
+
#
10
+
# Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca>
11
+
#
12
+
# All files in this archive are subject to the GNU General Public License.
13
+
# See the file COPYING in the source tree root for full license agreement.
14
+
#
15
+
# This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
16
+
# KIND, either express or implied.
17
+
#
18
+
import sys, os.path, array, re
19
+
from xml.dom import Node
20
+
from xml.dom.minidom import parse
21
+
22
+
23
+
C_IDENT_RE = re.compile('^[0-9a-zA-Z_]+$')
24
+
25
+
26
+
def getText(nodelist):
27
+
rc = ""
28
+
for node in nodelist:
29
+
if node.nodeType == node.TEXT_NODE:
30
+
rc = rc + node.data
31
+
return rc
32
+
33
+
34
+
def descendAll(root, tagname):
35
+
for child in root.childNodes:
36
+
if child.nodeType == Node.ELEMENT_NODE and child.tagName == tagname:
37
+
yield child
38
+
39
+
40
+
def descend(root, tagname):
41
+
return descendAll(root, tagname).next()
42
+
43
+
44
+
def getTagText(root, tagname):
45
+
try:
46
+
tag = descend(root, tagname)
47
+
except StopIteration:
48
+
return None
49
+
return getText(tag.childNodes)
50
+
51
+
52
+
def main():
53
+
dom = parse(sys.stdin)
54
+
55
+
ofd = descend(dom, "ofd")
56
+
object_file = descend(ofd, "object_file")
57
+
object_file_name = descend(object_file, "name")
58
+
59
+
out_filepath = getText(object_file_name.childNodes)
60
+
sys.stderr.write("*.out filename (input): %s\n" % out_filepath)
61
+
62
+
out_file = open(out_filepath, "rb")
63
+
h_file = sys.stdout
64
+
65
+
h_file.write("""#ifndef DSP_IMAGE
66
+
#define DSP_IMAGE
67
+
/*
68
+
* Automatically generated by xml2h.py from %s.
69
+
*
70
+
* This program is free software; you can redistribute it and/or
71
+
* modify it under the terms of the GNU General Public License as
72
+
* published by the Free Software Foundation; either version 2 of
73
+
* the License, or (at your option) any later version.
74
+
*
75
+
* This program is distributed in the hope that it will be useful,
76
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
77
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
78
+
* GNU General Public License for more details.
79
+
*
80
+
* You should have received a copy of the GNU General Public License
81
+
* along with this program; if not, write to the Free Software
82
+
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
83
+
* MA 02111-1307 USA
84
+
*
85
+
*/
86
+
""" % out_filepath)
87
+
88
+
# Section data and directory.
89
+
h_directory = ["""
90
+
static const struct dsp_section dsp_image[] = {"""]
91
+
92
+
ti_coff = descend(object_file, "ti_coff")
93
+
for section in descendAll(ti_coff, "section"):
94
+
page = int(getTagText(section, "page") or "0", 16)
95
+
name = getTagText(section, "name")
96
+
physical_addr = int(getTagText(section, "physical_addr"), 16)
97
+
raw_data_size = int(getTagText(section, "raw_data_size"), 16)
98
+
copy = getTagText(section, "copy")
99
+
data = getTagText(section, "data")
100
+
regular = getTagText(section, "regular")
101
+
text = getTagText(section, "text")
102
+
bss = getTagText(section, "bss")
103
+
104
+
file_offsets = descend(section, "file_offsets")
105
+
raw_data_ptr = int(getTagText(file_offsets, "raw_data_ptr"), 16)
106
+
107
+
if copy:
108
+
# Empirically, .debug* sections have this attribute set.
109
+
sys.stderr.write(
110
+
"%s: didn't copy debug section ('copy' attribute set)\n" %
111
+
name)
112
+
continue
113
+
114
+
if raw_data_size == 0:
115
+
sys.stderr.write("%s: not copying empty section\n" % name)
116
+
continue
117
+
118
+
if raw_data_size % 2 != 0:
119
+
sys.stderr.write("%s: error, raw_data_size 0x%04x not a multiple "
120
+
"of word size (2 bytes)\n" % (name, raw_data_size))
121
+
break
122
+
123
+
if data or regular or text:
124
+
sys.stderr.write("%s: placing 0x%04x words at 0x%04x from offset "
125
+
"0x%08x\n" % (
126
+
name, raw_data_size >> 1, physical_addr, raw_data_ptr))
127
+
128
+
sanitized_name = name.replace(".", "_")
129
+
h_file.write(("static const unsigned short _section%s[] = {\n" %
130
+
sanitized_name))
131
+
132
+
out_file.seek(raw_data_ptr)
133
+
data = array.array('H')
134
+
data.fromfile(out_file, raw_data_size >> 1)
135
+
h_file.write("\t")
136
+
for word in data:
137
+
h_file.write("0x%04x, " % word)
138
+
h_file.write("""
139
+
};
140
+
""")
141
+
142
+
h_directory.append("\t{_section%s, 0x%04x, 0x%04x}," % (
143
+
sanitized_name, physical_addr, raw_data_size >> 1))
144
+
145
+
continue
146
+
147
+
if bss:
148
+
sys.stderr.write("%s: bss section, 0x%04x words at 0x%04x\n" % (
149
+
name, raw_data_size >> 1, physical_addr))
150
+
151
+
h_directory.append("\t{NULL /* %s */, 0x%04x, 0x%04x}," % (
152
+
name, physical_addr, raw_data_size >> 1))
153
+
continue
154
+
155
+
sys.stderr.write("%s: error, unprocessed section\n" % name)
156
+
157
+
h_file.write("\n")
158
+
159
+
h_directory.append("\t{NULL, 0, 0}")
160
+
h_directory.append("};")
161
+
162
+
h_file.write("\n".join(h_directory))
163
+
h_file.write("\n")
164
+
165
+
# Symbols.
166
+
symbol_table = descend(ti_coff, "symbol_table")
167
+
h_file.write("""
168
+
/* Symbol table, usable with the DSP_() macro (see dsp-target.h). */
169
+
""")
170
+
for symbol in descendAll(symbol_table, "symbol"):
171
+
name = getTagText(symbol, "name")
172
+
kind = getTagText(symbol, "kind")
173
+
value = int(getTagText(symbol, "value"), 16)
174
+
175
+
if kind != "defined":
176
+
continue
177
+
178
+
if not C_IDENT_RE.match(name):
179
+
continue
180
+
181
+
h_file.write("#define %s 0x%04x\n" % (name, value))
182
+
183
+
h_file.write("\n#endif\n")
184
+
h_file.close()
185
+
out_file.close()
186
+
187
+
dom.unlink()
188
+
189
+
190
+
if __name__ == "__main__":
191
+
main()