tsiry-sandratraina.com
A modern Music Player Daemon based on Rockbox open source high quality audio player
libadwaita
audio
rust
zig
deno
mpris
rockbox
mpd
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2004 by Thom Johansen
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef __PP5002_H__
22#define __PP5002_H__
23
24/* Much info gleaned and/or copied from the iPodLinux project. */
25
26#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
27
28#define DRAM_START 0x28000000
29
30/* LCD bridge */
31#define LCD1_BASE 0xc0001000
32
33#define LCD1_CONTROL (*(volatile unsigned long *)(0xc0001000))
34#define LCD1_CMD (*(volatile unsigned long *)(0xc0001008))
35#define LCD1_DATA (*(volatile unsigned long *)(0xc0001010))
36
37#define LCD1_BUSY_MASK 0x8000
38
39/* I2S controller */
40
41/* FIFO slot bits 7-0 are not implemented and so use of packed samples
42 * appears to be impossible. */
43#define IISCONFIG (*(volatile unsigned long *)(0xc0002500))
44#define IISFIFO_CFG (*(volatile unsigned long *)(0xc000251c))
45#define IISFIFO_WR (*(volatile unsigned long *)(0xc0002540))
46#define IISFIFO_WRH (*(volatile unsigned short *)(0xc0002540))
47#define IISFIFO_RD (*(volatile unsigned long *)(0xc0002580))
48#define IISFIFO_RDH (*(volatile unsigned short *)(0xc0002540))
49
50/**
51 * IISCONFIG bits:
52 * | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
53 * | | | | | | | | |
54 * | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
55 * | | | | | | | | |
56 * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
57 * | | | | | | | | |
58 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
59 * | rw | rw | rw | MS | rw |TXFENB# | rw | ENB |
60 *
61 * # No effect observed on iPod 3g
62 */
63#define IIS_ENABLE (1 << 0)
64#define IIS_TXFIFOEN (1 << 2)
65#define IIS_MASTER (1 << 4)
66
67/**
68 * IISFIFO_CFG bits:
69 * | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
70 * | | RXFull[3:0]$ | TXFree[3:1] >
71 * | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
72 * >TXFre[0]| | | | | | RXCLR | TXCLR |
73 * | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
74 * | rw | rw | rw | rw | rw | rw | IRQTX | rw |
75 * | 7* | 6* | 5* | 4* | 3 | 2 | 1 | 0 |
76 * |RXEMPTY | RXSAFE | RXDNGR | RXFULL | TXFULL | TXSAFE | TXDNGR |TXEMPTY |
77 *
78 * $Could be RXFree
79 * *Meaning isn't certain yet.
80 * More concerted recording work will reveal.
81 */
82#define IIS_IRQTX_REG IISFIFO_CFG
83#define IIS_IRQRX_REG IISFIFO_CFG
84
85#define IIS_RX_FULL_MASK (0xf << 27)
86#define IIS_RX_FULL_COUNT ((IISFIFO_CFG & IIS_RX_FULL_MASK) >> 27)
87#define IIS_TX_FREE_MASK (0xf << 23) /* 0xf = 16 or 15 free */
88#define IIS_TX_FREE_COUNT ((IISFIFO_CFG & IIS_TX_FREE_MASK) >> 23)
89#define IIS_TX_IS_EMPTY ((IISFIFO_CFG & IIS_TXEMPTY) != 0)
90
91#define IIS_RXCLR (1 << 17) /* Resets *could* be reversed */
92#define IIS_TXCLR (1 << 16)
93#define IIS_IRQTX (1 << 9)
94#define IIS_TXFULL (1 << 3) /* All slots occupied */
95#define IIS_TXSAFE (1 << 2) /* FIFO >= 3/4 full */
96#define IIS_TXDANGER (1 << 1) /* FIFO <= 1/4 full */
97#define IIS_TXEMPTY (1 << 0) /* No samples in FIFO */
98
99#define IIS_RXEMPTY (1 << 4) /* FIFO is empty */
100
101#define IDE_BASE 0xc0003000
102
103#define IDE_CFG_STATUS (*(volatile unsigned long *)(0xc0003024))
104
105#define USB_BASE 0xc0005000
106
107#define I2C_BASE 0xc0008000
108
109/* Processor ID */
110#define PROCESSOR_ID (*(volatile unsigned long *)(0xc4000000))
111
112#define PROC_ID_CPU 0x55
113#define PROC_ID_COP 0xaa
114
115#define GPIOA_ENABLE (*(volatile unsigned char *)(0xcf000000))
116#define GPIOB_ENABLE (*(volatile unsigned char *)(0xcf000004))
117#define GPIOC_ENABLE (*(volatile unsigned char *)(0xcf000008))
118#define GPIOD_ENABLE (*(volatile unsigned char *)(0xcf00000c))
119#define GPIOA_OUTPUT_EN (*(volatile unsigned char *)(0xcf000010))
120#define GPIOB_OUTPUT_EN (*(volatile unsigned char *)(0xcf000014))
121#define GPIOC_OUTPUT_EN (*(volatile unsigned char *)(0xcf000018))
122#define GPIOD_OUTPUT_EN (*(volatile unsigned char *)(0xcf00001c))
123#define GPIOA_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000020))
124#define GPIOB_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000024))
125#define GPIOC_OUTPUT_VAL (*(volatile unsigned char *)(0xcf000028))
126#define GPIOD_OUTPUT_VAL (*(volatile unsigned char *)(0xcf00002c))
127#define GPIOA_INPUT_VAL (*(volatile unsigned char *)(0xcf000030))
128#define GPIOB_INPUT_VAL (*(volatile unsigned char *)(0xcf000034))
129#define GPIOC_INPUT_VAL (*(volatile unsigned char *)(0xcf000038))
130#define GPIOD_INPUT_VAL (*(volatile unsigned char *)(0xcf00003c))
131#define GPIOA_INT_STAT (*(volatile unsigned char *)(0xcf000040))
132#define GPIOB_INT_STAT (*(volatile unsigned char *)(0xcf000044))
133#define GPIOC_INT_STAT (*(volatile unsigned char *)(0xcf000048))
134#define GPIOD_INT_STAT (*(volatile unsigned char *)(0xcf00004c))
135#define GPIOA_INT_EN (*(volatile unsigned char *)(0xcf000050))
136#define GPIOB_INT_EN (*(volatile unsigned char *)(0xcf000054))
137#define GPIOC_INT_EN (*(volatile unsigned char *)(0xcf000058))
138#define GPIOD_INT_EN (*(volatile unsigned char *)(0xcf00005c))
139#define GPIOA_INT_LEV (*(volatile unsigned char *)(0xcf000060))
140#define GPIOB_INT_LEV (*(volatile unsigned char *)(0xcf000064))
141#define GPIOC_INT_LEV (*(volatile unsigned char *)(0xcf000068))
142#define GPIOD_INT_LEV (*(volatile unsigned char *)(0xcf00006c))
143#define GPIOA_INT_CLR (*(volatile unsigned char *)(0xcf000070))
144#define GPIOB_INT_CLR (*(volatile unsigned char *)(0xcf000074))
145#define GPIOC_INT_CLR (*(volatile unsigned char *)(0xcf000078))
146#define GPIOD_INT_CLR (*(volatile unsigned char *)(0xcf00007c))
147
148#define CPU_INT_STAT (*(volatile unsigned long *)(0xcf001000))
149#define COP_INT_STAT (*(volatile unsigned long *)(0xcf001004))
150#define CPU_FIQ_STAT (*(volatile unsigned long *)(0xcf001008))
151#define COP_FIQ_STAT (*(volatile unsigned long *)(0xcf00100c))
152
153#define INT_STAT (*(volatile unsigned long *)(0xcf001010))
154#define INT_FORCED_STAT (*(volatile unsigned long *)(0xcf001014))
155#define INT_FORCED_SET (*(volatile unsigned long *)(0xcf001018))
156#define INT_FORCED_CLR (*(volatile unsigned long *)(0xcf00101c))
157
158#define CPU_INT_EN_STAT (*(volatile unsigned long *)(0xcf001020))
159#define CPU_INT_EN (*(volatile unsigned long *)(0xcf001024))
160#define CPU_INT_DIS (*(volatile unsigned long *)(0xcf001028))
161#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
162
163#define COP_INT_EN_STAT (*(volatile unsigned long *)(0xcf001030))
164#define COP_INT_EN (*(volatile unsigned long *)(0xcf001034))
165#define COP_INT_DIS (*(volatile unsigned long *)(0xcf001038))
166#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
167
168#define IDE_IRQ 1
169#define SER0_IRQ 4
170#define I2S_IRQ 5
171#define SER1_IRQ 7
172#define TIMER1_IRQ 11
173#define TIMER2_IRQ 12
174#define GPIO_IRQ 14
175#define DMA_OUT_IRQ 30
176#define DMA_IN_IRQ 31
177
178#define IDE_MASK (1 << IDE_IRQ)
179#define SER0_MASK (1 << SER0_IRQ)
180#define I2S_MASK (1 << I2S_IRQ)
181#define SER1_MASK (1 << SER1_IRQ)
182#define TIMER1_MASK (1 << TIMER1_IRQ)
183#define TIMER2_MASK (1 << TIMER2_IRQ)
184#define GPIO_MASK (1 << GPIO_IRQ)
185#define DMA_OUT_MASK (1 << DMA_OUT_IRQ)
186#define DMA_IN_MASK (1 << DMA_IN_IRQ)
187
188/* Yes, there is I2S_MASK but this cleans up the pcm code */
189#define IIS_MASK DMA_OUT_MASK
190
191#define TIMER1_CFG (*(volatile unsigned long *)(0xcf001100))
192#define TIMER1_VAL (*(volatile unsigned long *)(0xcf001104))
193#define TIMER2_CFG (*(volatile unsigned long *)(0xcf001108))
194#define TIMER2_VAL (*(volatile unsigned long *)(0xcf00110c))
195
196#define USEC_TIMER (*(volatile unsigned long *)(0xcf001110))
197
198#define TIMING1_CTL (*(volatile unsigned long *)(0xcf004000))
199#define TIMING2_CTL (*(volatile unsigned long *)(0xcf004008))
200
201#define PP_VER1 (*(volatile unsigned long *)(0xcf004030))
202#define PP_VER2 (*(volatile unsigned long *)(0xcf004034))
203#define PP_VER3 (*(volatile unsigned long *)(0xcf004038))
204#define PP_VER4 (*(volatile unsigned long *)(0xcf00403c))
205
206/* Processors Control */
207#define PROC_STAT (*(volatile unsigned long *)(0xcf004050))
208#define CPU_CTL (*(volatile unsigned char *)(0xcf004054))
209#define COP_CTL (*(volatile unsigned char *)(0xcf004058))
210
211#define CPU_SLEEPING 0x8000
212#define COP_SLEEPING 0x4000
213#define PROC_SLEEPING(core) (0x8000 >> (core))
214
215#define PROC_CTL(core) ((&CPU_CTL)[(core)*4])
216
217#define PROC_SLEEP 0xca
218#define PROC_WAKE 0xce
219
220/* Cache Control */
221#define CACHE_CTL (*(volatile unsigned long *)(0xcf004024))
222#define CACHE_CTL_DISABLE 0x0
223#define CACHE_CTL_RUN 0x1
224#define CACHE_CTL_INIT 0x2
225
226#define CACHE_MASK (*(volatile unsigned long *)(0xf000f020))
227#define CACHE_OPERATION (*(volatile unsigned long *)(0xf000f024))
228#define CACHE_FLUSH_BASE (*(volatile unsigned long *)(0xf000c000))
229#define CACHE_INVALIDATE_BASE (*(volatile unsigned long *)(0xf0004000))
230#define CACHE_SIZE 0x2000 /* PP5002 has 8KB cache */
231
232#define CACHE_OP_UNKNOWN1 (1<<11) /* 0x800 */
233
234#define DEV_EN (*(volatile unsigned long *)(0xcf005000))
235#define DEV_RS (*(volatile unsigned long *)(0xcf005030))
236
237#define DEV_I2C (1<<8)
238#define DEV_I2S (1<<7)
239#define DEV_USB 0x400000
240
241#define CLOCK_ENABLE (*(volatile unsigned long *)(0xcf005008))
242#define CLOCK_SOURCE (*(volatile unsigned long *)(0xcf00500c))
243#define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010))
244#define PLL_DIV (*(volatile unsigned long *)(0xcf005018))
245#define PLL_MULT (*(volatile unsigned long *)(0xcf00501c))
246#define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038))
247
248#define MMAP_FIRST (*(volatile unsigned long *)(0xf000f000))
249#define MMAP_LAST (*(volatile unsigned long *)(0xf000f01c))
250#define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000))
251#define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004))
252#define MMAP1_LOGICAL (*(volatile unsigned long *)(0xf000f008))
253#define MMAP1_PHYSICAL (*(volatile unsigned long *)(0xf000f00c))
254#define MMAP2_LOGICAL (*(volatile unsigned long *)(0xf000f010))
255#define MMAP2_PHYSICAL (*(volatile unsigned long *)(0xf000f014))
256#define MMAP3_LOGICAL (*(volatile unsigned long *)(0xf000f018))
257#define MMAP3_PHYSICAL (*(volatile unsigned long *)(0xf000f01c))
258
259/* Timer frequency */
260/* Portalplayer chips use a microsecond timer. */
261#define TIMER_FREQ 1000000
262
263#endif