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1#/* $begin seq-all-hcl */
2####################################################################
3# HCL Description of Control for Single Cycle Y86-64 Processor SEQ #
4# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2010 #
5####################################################################
6
7####################################################################
8# C Include's. Don't alter these #
9####################################################################
10
11quote '#include <stdio.h>'
12quote '#include "isa.h"'
13quote '#include "sim.h"'
14quote 'int sim_main(int argc, char *argv[]);'
15quote 'word_t gen_pc(){return 0;}'
16quote 'int main(int argc, char *argv[])'
17quote ' {plusmode=0;return sim_main(argc,argv);}'
18
19####################################################################
20# Declarations. Do not change/remove/delete any of these #
21####################################################################
22
23##### Symbolic representation of Y86-64 Instruction Codes #############
24wordsig INOP 'I_NOP'
25wordsig IHALT 'I_HALT'
26wordsig IRRMOVQ 'I_RRMOVQ'
27wordsig IIRMOVQ 'I_IRMOVQ'
28wordsig IRMMOVQ 'I_RMMOVQ'
29wordsig IMRMOVQ 'I_MRMOVQ'
30wordsig IOPQ 'I_ALU'
31wordsig IJXX 'I_JMP'
32wordsig ICALL 'I_CALL'
33wordsig IRET 'I_RET'
34wordsig IPUSHQ 'I_PUSHQ'
35wordsig IPOPQ 'I_POPQ'
36
37##### Symbolic represenations of Y86-64 function codes #####
38wordsig FNONE 'F_NONE' # Default function code
39
40##### Symbolic representation of Y86-64 Registers referenced explicitly #####
41wordsig RRSP 'REG_RSP' # Stack Pointer
42wordsig RNONE 'REG_NONE' # Special value indicating "no register"
43
44##### ALU Functions referenced explicitly #####
45wordsig ALUADD 'A_ADD' # ALU should add its arguments
46
47##### Possible instruction status values #####
48wordsig SAOK 'STAT_AOK' # Normal execution
49wordsig SADR 'STAT_ADR' # Invalid memory address
50wordsig SINS 'STAT_INS' # Invalid instruction
51wordsig SHLT 'STAT_HLT' # Halt instruction encountered
52
53##### Signals that can be referenced by control logic ####################
54
55##### Fetch stage inputs #####
56wordsig pc 'pc' # Program counter
57##### Fetch stage computations #####
58wordsig imem_icode 'imem_icode' # icode field from instruction memory
59wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
60wordsig icode 'icode' # Instruction control code
61wordsig ifun 'ifun' # Instruction function
62wordsig rA 'ra' # rA field from instruction
63wordsig rB 'rb' # rB field from instruction
64wordsig valC 'valc' # Constant from instruction
65wordsig valP 'valp' # Address of following instruction
66boolsig imem_error 'imem_error' # Error signal from instruction memory
67boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
68
69##### Decode stage computations #####
70wordsig valA 'vala' # Value from register A port
71wordsig valB 'valb' # Value from register B port
72
73##### Execute stage computations #####
74wordsig valE 'vale' # Value computed by ALU
75boolsig Cnd 'cond' # Branch test
76
77##### Memory stage computations #####
78wordsig valM 'valm' # Value read from memory
79boolsig dmem_error 'dmem_error' # Error signal from data memory
80
81
82####################################################################
83# Control Signal Definitions. #
84####################################################################
85
86################ Fetch Stage ###################################
87
88# Determine instruction code
89word icode = [
90 imem_error: INOP;
91 1: imem_icode; # Default: get from instruction memory
92];
93
94# Determine instruction function
95word ifun = [
96 imem_error: FNONE;
97 1: imem_ifun; # Default: get from instruction memory
98];
99
100bool instr_valid = icode in
101 { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,
102 IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
103
104# Does fetched instruction require a regid byte?
105bool need_regids =
106 icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ,
107 IIRMOVQ, IRMMOVQ, IMRMOVQ };
108
109# Does fetched instruction require a constant word?
110bool need_valC =
111 icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
112
113################ Decode Stage ###################################
114
115## What register should be used as the A source?
116word srcA = [
117 icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA;
118 icode in { IPOPQ, IRET } : RRSP;
119 1 : RNONE; # Don't need register
120];
121
122## What register should be used as the B source?
123word srcB = [
124 icode in { IOPQ, IRMMOVQ, IMRMOVQ } : rB;
125 icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
126 1 : RNONE; # Don't need register
127];
128
129## What register should be used as the E destination?
130word dstE = [
131 icode in { IRRMOVQ } && Cnd : rB;
132 icode in { IIRMOVQ, IOPQ} : rB;
133 icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
134 1 : RNONE; # Don't write any register
135];
136
137## What register should be used as the M destination?
138word dstM = [
139 icode in { IMRMOVQ, IPOPQ } : rA;
140 1 : RNONE; # Don't write any register
141];
142
143################ Execute Stage ###################################
144
145## Select input A to ALU
146word aluA = [
147 icode in { IRRMOVQ, IOPQ } : valA;
148 icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : valC;
149 icode in { ICALL, IPUSHQ } : -8;
150 icode in { IRET, IPOPQ } : 8;
151 # Other instructions don't need ALU
152];
153
154## Select input B to ALU
155word aluB = [
156 icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,
157 IPUSHQ, IRET, IPOPQ } : valB;
158 icode in { IRRMOVQ, IIRMOVQ } : 0;
159 # Other instructions don't need ALU
160];
161
162## Set the ALU function
163word alufun = [
164 icode == IOPQ : ifun;
165 1 : ALUADD;
166];
167
168## Should the condition codes be updated?
169bool set_cc = icode in { IOPQ };
170
171################ Memory Stage ###################################
172
173## Set read control signal
174bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };
175
176## Set write control signal
177bool mem_write = icode in { IRMMOVQ, IPUSHQ, ICALL };
178
179## Select memory address
180word mem_addr = [
181 icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;
182 icode in { IPOPQ, IRET } : valA;
183 # Other instructions don't need address
184];
185
186## Select memory input data
187word mem_data = [
188 # Value from register
189 icode in { IRMMOVQ, IPUSHQ } : valA;
190 # Return PC
191 icode == ICALL : valP;
192 # Default: Don't write anything
193];
194
195## Determine instruction status
196word Stat = [
197 imem_error || dmem_error : SADR;
198 !instr_valid: SINS;
199 icode == IHALT : SHLT;
200 1 : SAOK;
201];
202
203################ Program Counter Update ############################
204
205## What address should instruction be fetched at
206
207word new_pc = [
208 # Call. Use instruction constant
209 icode == ICALL : valC;
210 # Taken branch. Use instruction constant
211 icode == IJXX && Cnd : valC;
212 # Completion of RET instruction. Use value from stack
213 icode == IRET : valM;
214 # Default: Use incremented PC
215 1 : valP;
216];
217#/* $end seq-all-hcl */