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1#/* $begin seq-all-hcl */
2####################################################################
3# HCL Description of Control for Single Cycle Y86-64 Processor SEQ+ #
4# Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2010 #
5####################################################################
6
7####################################################################
8# C Include's. Don't alter these #
9####################################################################
10
11quote '#include <stdio.h>'
12quote '#include "isa.h"'
13quote '#include "sim.h"'
14quote 'int sim_main(int argc, char *argv[]);'
15quote 'word_t gen_new_pc(){return 0;}'
16quote 'int main(int argc, char *argv[])'
17quote ' {plusmode=1;return sim_main(argc,argv);}'
18
19####################################################################
20# Declarations. Do not change/remove/delete any of these #
21####################################################################
22
23##### Symbolic representation of Y86-64 Instruction Codes #############
24wordsig INOP 'I_NOP'
25wordsig IHALT 'I_HALT'
26wordsig IRRMOVQ 'I_RRMOVQ'
27wordsig IIRMOVQ 'I_IRMOVQ'
28wordsig IRMMOVQ 'I_RMMOVQ'
29wordsig IMRMOVQ 'I_MRMOVQ'
30wordsig IOPQ 'I_ALU'
31wordsig IJXX 'I_JMP'
32wordsig ICALL 'I_CALL'
33wordsig IRET 'I_RET'
34wordsig IPUSHQ 'I_PUSHQ'
35wordsig IPOPQ 'I_POPQ'
36
37##### Symbolic represenations of Y86-64 function codes #####
38wordsig FNONE 'F_NONE' # Default function code
39
40##### Symbolic representation of Y86-64 Registers referenced explicitly #####
41wordsig RRSP 'REG_RSP' # Stack Pointer
42wordsig RNONE 'REG_NONE' # Special value indicating "no register"
43
44##### ALU Functions referenced explicitly #####
45wordsig ALUADD 'A_ADD' # ALU should add its arguments
46
47##### Possible instruction status values #####
48wordsig SAOK 'STAT_AOK' # Normal execution
49wordsig SADR 'STAT_ADR' # Invalid memory address
50wordsig SINS 'STAT_INS' # Invalid instruction
51wordsig SHLT 'STAT_HLT' # Halt instruction encountered
52
53##### Signals that can be referenced by control logic ####################
54
55##### PC stage inputs #####
56
57## All of these values are based on those from previous instruction
58wordsig pIcode 'prev_icode' # Instr. control code
59wordsig pValC 'prev_valc' # Constant from instruction
60wordsig pValM 'prev_valm' # Value read from memory
61wordsig pValP 'prev_valp' # Incremented program counter
62boolsig pCnd 'prev_bcond' # Condition flag
63
64##### Fetch stage computations #####
65wordsig imem_icode 'imem_icode' # icode field from instruction memory
66wordsig imem_ifun 'imem_ifun' # ifun field from instruction memory
67wordsig icode 'icode' # Instruction control code
68wordsig ifun 'ifun' # Instruction function
69wordsig rA 'ra' # rA field from instruction
70wordsig rB 'rb' # rB field from instruction
71wordsig valC 'valc' # Constant from instruction
72wordsig valP 'valp' # Address of following instruction
73boolsig imem_error 'imem_error' # Error signal from instruction memory
74boolsig instr_valid 'instr_valid' # Is fetched instruction valid?
75
76##### Decode stage computations #####
77wordsig valA 'vala' # Value from register A port
78wordsig valB 'valb' # Value from register B port
79
80##### Execute stage computations #####
81wordsig valE 'vale' # Value computed by ALU
82boolsig Cnd 'cond' # Branch test
83
84##### Memory stage computations #####
85wordsig valM 'valm' # Value read from memory
86boolsig dmem_error 'dmem_error' # Error signal from data memory
87
88
89####################################################################
90# Control Signal Definitions. #
91####################################################################
92
93################ Program Counter Computation #######################
94
95# Compute fetch location for this instruction based on results from
96# previous instruction.
97
98word pc = [
99 # Call. Use instruction constant
100 pIcode == ICALL : pValC;
101 # Taken branch. Use instruction constant
102 pIcode == IJXX && pCnd : pValC;
103 # Completion of RET instruction. Use value from stack
104 pIcode == IRET : pValM;
105 # Default: Use incremented PC
106 1 : pValP;
107];
108#/* $end seq-plus-pc-hcl */
109
110################ Fetch Stage ###################################
111
112# Determine instruction code
113word icode = [
114 imem_error: INOP;
115 1: imem_icode; # Default: get from instruction memory
116];
117
118# Determine instruction function
119word ifun = [
120 imem_error: FNONE;
121 1: imem_ifun; # Default: get from instruction memory
122];
123
124bool instr_valid = icode in
125 { INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,
126 IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
127
128# Does fetched instruction require a regid byte?
129bool need_regids =
130 icode in { IRRMOVQ, IOPQ, IPUSHQ, IPOPQ,
131 IIRMOVQ, IRMMOVQ, IMRMOVQ };
132
133# Does fetched instruction require a constant word?
134bool need_valC =
135 icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
136
137################ Decode Stage ###################################
138
139## What register should be used as the A source?
140word srcA = [
141 icode in { IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ } : rA;
142 icode in { IPOPQ, IRET } : RRSP;
143 1 : RNONE; # Don't need register
144];
145
146## What register should be used as the B source?
147word srcB = [
148 icode in { IOPQ, IRMMOVQ, IMRMOVQ } : rB;
149 icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
150 1 : RNONE; # Don't need register
151];
152
153## What register should be used as the E destination?
154word dstE = [
155 icode in { IRRMOVQ } && Cnd : rB;
156 icode in { IIRMOVQ, IOPQ} : rB;
157 icode in { IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
158 1 : RNONE; # Don't write any register
159];
160
161## What register should be used as the M destination?
162word dstM = [
163 icode in { IMRMOVQ, IPOPQ } : rA;
164 1 : RNONE; # Don't write any register
165];
166
167################ Execute Stage ###################################
168
169## Select input A to ALU
170word aluA = [
171 icode in { IRRMOVQ, IOPQ } : valA;
172 icode in { IIRMOVQ, IRMMOVQ, IMRMOVQ } : valC;
173 icode in { ICALL, IPUSHQ } : -8;
174 icode in { IRET, IPOPQ } : 8;
175 # Other instructions don't need ALU
176];
177
178## Select input B to ALU
179word aluB = [
180 icode in { IRMMOVQ, IMRMOVQ, IOPQ, ICALL,
181 IPUSHQ, IRET, IPOPQ } : valB;
182 icode in { IRRMOVQ, IIRMOVQ } : 0;
183 # Other instructions don't need ALU
184];
185
186## Set the ALU function
187word alufun = [
188 icode == IOPQ : ifun;
189 1 : ALUADD;
190];
191
192## Should the condition codes be updated?
193bool set_cc = icode in { IOPQ };
194
195################ Memory Stage ###################################
196
197## Set read control signal
198bool mem_read = icode in { IMRMOVQ, IPOPQ, IRET };
199
200## Set write control signal
201bool mem_write = icode in { IRMMOVQ, IPUSHQ, ICALL };
202
203## Select memory address
204word mem_addr = [
205 icode in { IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;
206 icode in { IPOPQ, IRET } : valA;
207 # Other instructions don't need address
208];
209
210## Select memory input data
211word mem_data = [
212 # Value from register
213 icode in { IRMMOVQ, IPUSHQ } : valA;
214 # Return PC
215 icode == ICALL : valP;
216 # Default: Don't write anything
217];
218
219## Determine instruction status
220word Stat = [
221 imem_error || dmem_error : SADR;
222 !instr_valid: SINS;
223 icode == IHALT : SHLT;
224 1 : SAOK;
225];
226#/* $end seq-all-hcl */