nonbinary.computer
OR-1 dataflow CPU sketch
1; ==========================================
2; dfasm syntax highlighting test program
3; ==========================================
4
5; --- System pragma ---
6@system pe=3, sm=1, iram=128, ctx=2
7
8; --- Data definitions ---
9@val|sm0:5 = 0x42
10@msg|sm0:0 = 'h', 'e', 'l', 'l', 'o'
11@greeting = #str "hello\nworld"
12@path = r"no\escapes\here"
13@raw = b"\x01\x02\x03"
14
15; --- Location directive ---
16@data_section|sm0:
17
18; --- Instruction definitions ---
19&c1|pe0 <| const, 3
20&c2|pe0 <| const, 0xFF
21&result|pe0 <| add
22&output|pe1 <| pass
23&branch|pe2 <| sweq
24&serial|pe0 <| ior, dest=0x45, addr=0x91, data=0x43
25&reader|pe1 <| read, 5
26
27; --- Plain edges ---
28&c1|pe0 |> &result|pe0:L
29&c2|pe0 |> &result|pe0:R
30&result|pe0 |> &output|pe1:L
31&result|pe0 |> &branch|pe2:L
32
33; --- Strong inline edge ---
34add &c1, &c2 |> &output, &branch
35
36; --- Weak inline edge ---
37&output, &branch sub <| &c1, &c2
38
39; --- Function definition ---
40$fib |> {
41 &const_n <| const, 10
42 &sub1 <| sub
43 &branch <| sweq
44 &const_n |> &branch:L
45 &sub1 |> &branch:R
46}
47
48; --- All opcodes ---
49&op_add <| add
50&op_sub <| sub
51&op_inc <| inc
52&op_dec <| dec
53&op_shiftl <| shiftl
54&op_shiftr <| shiftr
55&op_ashiftr <| ashiftr
56&op_and <| and
57&op_or <| or
58&op_xor <| xor
59&op_not <| not
60&op_eq <| eq
61&op_lt <| lt
62&op_lte <| lte
63&op_gt <| gt
64&op_gte <| gte
65&op_breq <| breq
66&op_brgt <| brgt
67&op_brge <| brge
68&op_brof <| brof
69&op_brty <| brty
70&op_sweq <| sweq
71&op_swgt <| swgt
72&op_swge <| swge
73&op_swof <| swof
74&op_swty <| swty
75&op_gate <| gate
76&op_sel <| sel
77&op_merge <| merge
78&op_pass <| pass
79&op_const <| const, 0
80&op_free_ctx <| free_ctx
81&op_read <| read
82&op_write <| write
83&op_clear <| clear
84&op_alloc <| alloc
85&op_free <| free
86&op_rd_inc <| rd_inc
87&op_rd_dec <| rd_dec
88&op_cmp_sw <| cmp_sw
89&op_ior <| ior
90&op_iow <| iow
91&op_iorw <| iorw
92&op_load <| load_inst
93&op_route <| route_set