jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * m68k virtual CPU header
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef M68K_CPU_H
22#define M68K_CPU_H
23
24#include "exec/cpu-defs.h"
25#include "cpu-qom.h"
26
27#define OS_BYTE 0
28#define OS_WORD 1
29#define OS_LONG 2
30#define OS_SINGLE 3
31#define OS_DOUBLE 4
32#define OS_EXTENDED 5
33#define OS_PACKED 6
34#define OS_UNSIZED 7
35
36#define MAX_QREGS 32
37
38#define EXCP_ACCESS 2 /* Access (MMU) error. */
39#define EXCP_ADDRESS 3 /* Address error. */
40#define EXCP_ILLEGAL 4 /* Illegal instruction. */
41#define EXCP_DIV0 5 /* Divide by zero */
42#define EXCP_CHK 6 /* CHK, CHK2 Instructions */
43#define EXCP_TRAPCC 7 /* FTRAPcc, TRAPcc, TRAPV Instructions */
44#define EXCP_PRIVILEGE 8 /* Privilege violation. */
45#define EXCP_TRACE 9
46#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */
47#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */
48#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */
49#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */
50#define EXCP_FORMAT 14 /* RTE format error. */
51#define EXCP_UNINITIALIZED 15
52#define EXCP_SPURIOUS 24 /* Spurious interrupt */
53#define EXCP_INT_LEVEL_1 25 /* Level 1 Interrupt autovector */
54#define EXCP_INT_LEVEL_7 31 /* Level 7 Interrupt autovector */
55#define EXCP_TRAP0 32 /* User trap #0. */
56#define EXCP_TRAP15 47 /* User trap #15. */
57#define EXCP_FP_BSUN 48 /* Branch Set on Unordered */
58#define EXCP_FP_INEX 49 /* Inexact result */
59#define EXCP_FP_DZ 50 /* Divide by Zero */
60#define EXCP_FP_UNFL 51 /* Underflow */
61#define EXCP_FP_OPERR 52 /* Operand Error */
62#define EXCP_FP_OVFL 53 /* Overflow */
63#define EXCP_FP_SNAN 54 /* Signaling Not-A-Number */
64#define EXCP_FP_UNIMP 55 /* Unimplemented Data type */
65#define EXCP_MMU_CONF 56 /* MMU Configuration Error */
66#define EXCP_MMU_ILLEGAL 57 /* MMU Illegal Operation Error */
67#define EXCP_MMU_ACCESS 58 /* MMU Access Level Violation Error */
68
69#define EXCP_RTE 0x100
70#define EXCP_HALT_INSN 0x101
71
72#define M68K_DTTR0 0
73#define M68K_DTTR1 1
74#define M68K_ITTR0 2
75#define M68K_ITTR1 3
76
77#define M68K_MAX_TTR 2
78#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
79
80#define TARGET_INSN_START_EXTRA_WORDS 1
81
82typedef CPU_LDoubleU FPReg;
83
84typedef struct CPUM68KState {
85 uint32_t dregs[8];
86 uint32_t aregs[8];
87 uint32_t pc;
88 uint32_t sr;
89
90 /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
91 int current_sp;
92 uint32_t sp[3];
93
94 /* Condition flags. */
95 uint32_t cc_op;
96 uint32_t cc_x; /* always 0/1 */
97 uint32_t cc_n; /* in bit 31 (i.e. negative) */
98 uint32_t cc_v; /* in bit 31, unused, or computed from cc_n and cc_v */
99 uint32_t cc_c; /* either 0/1, unused, or computed from cc_n and cc_v */
100 uint32_t cc_z; /* == 0 or unused */
101
102 FPReg fregs[8];
103 FPReg fp_result;
104 uint32_t fpcr;
105 uint32_t fpsr;
106 float_status fp_status;
107
108 uint64_t mactmp;
109 /*
110 * EMAC Hardware deals with 48-bit values composed of one 32-bit and
111 * two 8-bit parts. We store a single 64-bit value and
112 * rearrange/extend this when changing modes.
113 */
114 uint64_t macc[4];
115 uint32_t macsr;
116 uint32_t mac_mask;
117
118 /* MMU status. */
119 struct {
120 uint32_t ar;
121 uint32_t ssw;
122 /* 68040 */
123 uint16_t tcr;
124 uint32_t urp;
125 uint32_t srp;
126 bool fault;
127 uint32_t ttr[4];
128 uint32_t mmusr;
129 } mmu;
130
131 /* Control registers. */
132 uint32_t vbr;
133 uint32_t mbar;
134 uint32_t rambar0;
135 uint32_t cacr;
136 uint32_t sfc;
137 uint32_t dfc;
138
139 int pending_vector;
140 int pending_level;
141
142 uint32_t qregs[MAX_QREGS];
143
144 /* Fields up to this point are cleared by a CPU reset */
145 struct {} end_reset_fields;
146
147 /* Fields from here on are preserved across CPU reset. */
148 uint32_t features;
149} CPUM68KState;
150
151/*
152 * M68kCPU:
153 * @env: #CPUM68KState
154 *
155 * A Motorola 68k CPU.
156 */
157struct M68kCPU {
158 /*< private >*/
159 CPUState parent_obj;
160 /*< public >*/
161
162 CPUNegativeOffsetState neg;
163 CPUM68KState env;
164};
165
166
167void m68k_cpu_do_interrupt(CPUState *cpu);
168bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
169void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
170hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
171int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
172int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
173
174void m68k_tcg_init(void);
175void m68k_cpu_init_gdb(M68kCPU *cpu);
176/*
177 * you can call this signal handler from your SIGBUS and SIGSEGV
178 * signal handlers to inform the virtual CPU of exceptions. non zero
179 * is returned if the signal was handled by the virtual CPU.
180 */
181int cpu_m68k_signal_handler(int host_signum, void *pinfo,
182 void *puc);
183uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
184void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);
185void cpu_m68k_set_sr(CPUM68KState *env, uint32_t);
186void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val);
187
188
189/*
190 * Instead of computing the condition codes after each m68k instruction,
191 * QEMU just stores one operand (called CC_SRC), the result
192 * (called CC_DEST) and the type of operation (called CC_OP). When the
193 * condition codes are needed, the condition codes can be calculated
194 * using this information. Condition codes are not generated if they
195 * are only needed for conditional branches.
196 */
197typedef enum {
198 /* Translator only -- use env->cc_op. */
199 CC_OP_DYNAMIC,
200
201 /* Each flag bit computed into cc_[xcnvz]. */
202 CC_OP_FLAGS,
203
204 /* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
205 CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
206 CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
207
208 /* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
209 CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
210
211 /* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
212 CC_OP_LOGIC,
213
214 CC_OP_NB
215} CCOp;
216
217#define CCF_C 0x01
218#define CCF_V 0x02
219#define CCF_Z 0x04
220#define CCF_N 0x08
221#define CCF_X 0x10
222
223#define SR_I_SHIFT 8
224#define SR_I 0x0700
225#define SR_M 0x1000
226#define SR_S 0x2000
227#define SR_T_SHIFT 14
228#define SR_T 0xc000
229
230#define M68K_SSP 0
231#define M68K_USP 1
232#define M68K_ISP 2
233
234/* bits for 68040 special status word */
235#define M68K_CP_040 0x8000
236#define M68K_CU_040 0x4000
237#define M68K_CT_040 0x2000
238#define M68K_CM_040 0x1000
239#define M68K_MA_040 0x0800
240#define M68K_ATC_040 0x0400
241#define M68K_LK_040 0x0200
242#define M68K_RW_040 0x0100
243#define M68K_SIZ_040 0x0060
244#define M68K_TT_040 0x0018
245#define M68K_TM_040 0x0007
246
247#define M68K_TM_040_DATA 0x0001
248#define M68K_TM_040_CODE 0x0002
249#define M68K_TM_040_SUPER 0x0004
250
251/* bits for 68040 write back status word */
252#define M68K_WBV_040 0x80
253#define M68K_WBSIZ_040 0x60
254#define M68K_WBBYT_040 0x20
255#define M68K_WBWRD_040 0x40
256#define M68K_WBLNG_040 0x00
257#define M68K_WBTT_040 0x18
258#define M68K_WBTM_040 0x07
259
260/* bus access size codes */
261#define M68K_BA_SIZE_MASK 0x60
262#define M68K_BA_SIZE_BYTE 0x20
263#define M68K_BA_SIZE_WORD 0x40
264#define M68K_BA_SIZE_LONG 0x00
265#define M68K_BA_SIZE_LINE 0x60
266
267/* bus access transfer type codes */
268#define M68K_BA_TT_MOVE16 0x08
269
270/* bits for 68040 MMU status register (mmusr) */
271#define M68K_MMU_B_040 0x0800
272#define M68K_MMU_G_040 0x0400
273#define M68K_MMU_U1_040 0x0200
274#define M68K_MMU_U0_040 0x0100
275#define M68K_MMU_S_040 0x0080
276#define M68K_MMU_CM_040 0x0060
277#define M68K_MMU_M_040 0x0010
278#define M68K_MMU_WP_040 0x0004
279#define M68K_MMU_T_040 0x0002
280#define M68K_MMU_R_040 0x0001
281
282#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
283 M68K_MMU_U0_040 | M68K_MMU_S_040 | \
284 M68K_MMU_CM_040 | M68K_MMU_M_040 | \
285 M68K_MMU_WP_040)
286
287/* bits for 68040 MMU Translation Control Register */
288#define M68K_TCR_ENABLED 0x8000
289#define M68K_TCR_PAGE_8K 0x4000
290
291/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
292#define M68K_DESC_WRITEPROT 0x00000004
293#define M68K_DESC_USED 0x00000008
294#define M68K_DESC_MODIFIED 0x00000010
295#define M68K_DESC_CACHEMODE 0x00000060
296#define M68K_DESC_CM_WRTHRU 0x00000000
297#define M68K_DESC_CM_COPYBK 0x00000020
298#define M68K_DESC_CM_SERIAL 0x00000040
299#define M68K_DESC_CM_NCACHE 0x00000060
300#define M68K_DESC_SUPERONLY 0x00000080
301#define M68K_DESC_USERATTR 0x00000300
302#define M68K_DESC_USERATTR_SHIFT 8
303#define M68K_DESC_GLOBAL 0x00000400
304#define M68K_DESC_URESERVED 0x00000800
305
306#define M68K_ROOT_POINTER_ENTRIES 128
307#define M68K_4K_PAGE_MASK (~0xff)
308#define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
309#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
310#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
311#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
312#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
313#define M68K_8K_PAGE_MASK (~0x7f)
314#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
315#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
316#define M68K_UDT_VALID(entry) (entry & 2)
317#define M68K_PDT_VALID(entry) (entry & 3)
318#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
319#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
320#define M68K_TTS_POINTER_SHIFT 18
321#define M68K_TTS_ROOT_SHIFT 25
322
323/* bits for 68040 MMU Transparent Translation Registers */
324#define M68K_TTR_ADDR_BASE 0xff000000
325#define M68K_TTR_ADDR_MASK 0x00ff0000
326#define M68K_TTR_ADDR_MASK_SHIFT 8
327#define M68K_TTR_ENABLED 0x00008000
328#define M68K_TTR_SFIELD 0x00006000
329#define M68K_TTR_SFIELD_USER 0x0000
330#define M68K_TTR_SFIELD_SUPER 0x2000
331
332/* m68k Control Registers */
333
334/* ColdFire */
335/* Memory Management Control Registers */
336#define M68K_CR_ASID 0x003
337#define M68K_CR_ACR0 0x004
338#define M68K_CR_ACR1 0x005
339#define M68K_CR_ACR2 0x006
340#define M68K_CR_ACR3 0x007
341#define M68K_CR_MMUBAR 0x008
342
343/* Processor Miscellaneous Registers */
344#define M68K_CR_PC 0x80F
345
346/* Local Memory and Module Control Registers */
347#define M68K_CR_ROMBAR0 0xC00
348#define M68K_CR_ROMBAR1 0xC01
349#define M68K_CR_RAMBAR0 0xC04
350#define M68K_CR_RAMBAR1 0xC05
351#define M68K_CR_MPCR 0xC0C
352#define M68K_CR_EDRAMBAR 0xC0D
353#define M68K_CR_SECMBAR 0xC0E
354#define M68K_CR_MBAR 0xC0F
355
356/* Local Memory Address Permutation Control Registers */
357#define M68K_CR_PCR1U0 0xD02
358#define M68K_CR_PCR1L0 0xD03
359#define M68K_CR_PCR2U0 0xD04
360#define M68K_CR_PCR2L0 0xD05
361#define M68K_CR_PCR3U0 0xD06
362#define M68K_CR_PCR3L0 0xD07
363#define M68K_CR_PCR1U1 0xD0A
364#define M68K_CR_PCR1L1 0xD0B
365#define M68K_CR_PCR2U1 0xD0C
366#define M68K_CR_PCR2L1 0xD0D
367#define M68K_CR_PCR3U1 0xD0E
368#define M68K_CR_PCR3L1 0xD0F
369
370/* MC680x0 */
371/* MC680[1234]0/CPU32 */
372#define M68K_CR_SFC 0x000
373#define M68K_CR_DFC 0x001
374#define M68K_CR_USP 0x800
375#define M68K_CR_VBR 0x801 /* + Coldfire */
376
377/* MC680[234]0 */
378#define M68K_CR_CACR 0x002 /* + Coldfire */
379#define M68K_CR_CAAR 0x802 /* MC68020 and MC68030 only */
380#define M68K_CR_MSP 0x803
381#define M68K_CR_ISP 0x804
382
383/* MC68040/MC68LC040 */
384#define M68K_CR_TC 0x003
385#define M68K_CR_ITT0 0x004
386#define M68K_CR_ITT1 0x005
387#define M68K_CR_DTT0 0x006
388#define M68K_CR_DTT1 0x007
389#define M68K_CR_MMUSR 0x805
390#define M68K_CR_URP 0x806
391#define M68K_CR_SRP 0x807
392
393/* MC68EC040 */
394#define M68K_CR_IACR0 0x004
395#define M68K_CR_IACR1 0x005
396#define M68K_CR_DACR0 0x006
397#define M68K_CR_DACR1 0x007
398
399#define M68K_FPIAR_SHIFT 0
400#define M68K_FPIAR (1 << M68K_FPIAR_SHIFT)
401#define M68K_FPSR_SHIFT 1
402#define M68K_FPSR (1 << M68K_FPSR_SHIFT)
403#define M68K_FPCR_SHIFT 2
404#define M68K_FPCR (1 << M68K_FPCR_SHIFT)
405
406/* Floating-Point Status Register */
407
408/* Condition Code */
409#define FPSR_CC_MASK 0x0f000000
410#define FPSR_CC_A 0x01000000 /* Not-A-Number */
411#define FPSR_CC_I 0x02000000 /* Infinity */
412#define FPSR_CC_Z 0x04000000 /* Zero */
413#define FPSR_CC_N 0x08000000 /* Negative */
414
415/* Quotient */
416
417#define FPSR_QT_MASK 0x00ff0000
418#define FPSR_QT_SHIFT 16
419
420/* Floating-Point Control Register */
421/* Rounding mode */
422#define FPCR_RND_MASK 0x0030
423#define FPCR_RND_N 0x0000
424#define FPCR_RND_Z 0x0010
425#define FPCR_RND_M 0x0020
426#define FPCR_RND_P 0x0030
427
428/* Rounding precision */
429#define FPCR_PREC_MASK 0x00c0
430#define FPCR_PREC_X 0x0000
431#define FPCR_PREC_S 0x0040
432#define FPCR_PREC_D 0x0080
433#define FPCR_PREC_U 0x00c0
434
435#define FPCR_EXCP_MASK 0xff00
436
437/* CACR fields are implementation defined, but some bits are common. */
438#define M68K_CACR_EUSP 0x10
439
440#define MACSR_PAV0 0x100
441#define MACSR_OMC 0x080
442#define MACSR_SU 0x040
443#define MACSR_FI 0x020
444#define MACSR_RT 0x010
445#define MACSR_N 0x008
446#define MACSR_Z 0x004
447#define MACSR_V 0x002
448#define MACSR_EV 0x001
449
450void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
451void m68k_switch_sp(CPUM68KState *env);
452
453void do_m68k_semihosting(CPUM68KState *env, int nr);
454
455/*
456 * There are 4 ColdFire core ISA revisions: A, A+, B and C.
457 * Each feature covers the subset of instructions common to the
458 * ISA revisions mentioned.
459 */
460
461enum m68k_features {
462 M68K_FEATURE_M68000,
463 M68K_FEATURE_M68020,
464 M68K_FEATURE_M68030,
465 M68K_FEATURE_M68040,
466 M68K_FEATURE_M68060,
467 M68K_FEATURE_CF_ISA_A,
468 M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
469 M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
470 M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
471 M68K_FEATURE_CF_FPU,
472 M68K_FEATURE_CF_MAC,
473 M68K_FEATURE_CF_EMAC,
474 M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
475 M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
476 M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
477 M68K_FEATURE_WORD_INDEX, /* word sized address index registers. */
478 M68K_FEATURE_SCALED_INDEX, /* scaled address index registers. */
479 M68K_FEATURE_LONG_MULDIV, /* 32 bit multiply/divide. */
480 M68K_FEATURE_QUAD_MULDIV, /* 64 bit multiply/divide. */
481 M68K_FEATURE_BCCL, /* Long conditional branches. */
482 M68K_FEATURE_BITFIELD, /* Bit field insns. */
483 M68K_FEATURE_FPU,
484 M68K_FEATURE_CAS,
485 M68K_FEATURE_BKPT,
486 M68K_FEATURE_RTD,
487 M68K_FEATURE_CHK2,
488 M68K_FEATURE_MOVEP,
489};
490
491static inline int m68k_feature(CPUM68KState *env, int feature)
492{
493 return (env->features & (1u << feature)) != 0;
494}
495
496void m68k_cpu_list(void);
497
498void register_m68k_insns (CPUM68KState *env);
499
500enum {
501 /* 1 bit to define user level / supervisor access */
502 ACCESS_SUPER = 0x01,
503 /* 1 bit to indicate direction */
504 ACCESS_STORE = 0x02,
505 /* 1 bit to indicate debug access */
506 ACCESS_DEBUG = 0x04,
507 /* PTEST instruction */
508 ACCESS_PTEST = 0x08,
509 /* Type of instruction that generated the access */
510 ACCESS_CODE = 0x10, /* Code fetch access */
511 ACCESS_DATA = 0x20, /* Data load/store access */
512};
513
514#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU
515#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX
516#define CPU_RESOLVING_TYPE TYPE_M68K_CPU
517
518#define cpu_signal_handler cpu_m68k_signal_handler
519#define cpu_list m68k_cpu_list
520
521/* MMU modes definitions */
522#define MMU_KERNEL_IDX 0
523#define MMU_USER_IDX 1
524static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
525{
526 return (env->sr & SR_S) == 0 ? 1 : 0;
527}
528
529bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
530 MMUAccessType access_type, int mmu_idx,
531 bool probe, uintptr_t retaddr);
532void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
533 unsigned size, MMUAccessType access_type,
534 int mmu_idx, MemTxAttrs attrs,
535 MemTxResult response, uintptr_t retaddr);
536
537typedef CPUM68KState CPUArchState;
538typedef M68kCPU ArchCPU;
539
540#include "exec/cpu-all.h"
541
542/* TB flags */
543#define TB_FLAGS_MACSR 0x0f
544#define TB_FLAGS_MSR_S_BIT 13
545#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT)
546#define TB_FLAGS_SFC_S_BIT 14
547#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT)
548#define TB_FLAGS_DFC_S_BIT 15
549#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT)
550
551static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
552 target_ulong *cs_base, uint32_t *flags)
553{
554 *pc = env->pc;
555 *cs_base = 0;
556 *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
557 if (env->sr & SR_S) {
558 *flags |= TB_FLAGS_MSR_S;
559 *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
560 *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
561 }
562}
563
564void dump_mmu(CPUM68KState *env);
565
566#endif