jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28#ifndef XICS_H
29#define XICS_H
30
31#include "exec/memory.h"
32#include "hw/qdev-core.h"
33
34#define XICS_IPI 0x2
35#define XICS_BUID 0x1
36#define XICS_IRQ_BASE (XICS_BUID << 12)
37
38/*
39 * We currently only support one BUID which is our interrupt base
40 * (the kernel implementation supports more but we don't exploit
41 * that yet)
42 */
43typedef struct ICPStateClass ICPStateClass;
44typedef struct ICPState ICPState;
45typedef struct PnvICPState PnvICPState;
46typedef struct ICSStateClass ICSStateClass;
47typedef struct ICSState ICSState;
48typedef struct ICSIRQState ICSIRQState;
49typedef struct XICSFabric XICSFabric;
50
51#define TYPE_ICP "icp"
52#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
53
54#define TYPE_PNV_ICP "pnv-icp"
55#define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
56
57#define ICP_CLASS(klass) \
58 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
59#define ICP_GET_CLASS(obj) \
60 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
61
62struct ICPStateClass {
63 DeviceClass parent_class;
64
65 DeviceRealize parent_realize;
66};
67
68struct ICPState {
69 /*< private >*/
70 DeviceState parent_obj;
71 /*< public >*/
72 CPUState *cs;
73 ICSState *xirr_owner;
74 uint32_t xirr;
75 uint8_t pending_priority;
76 uint8_t mfrr;
77 qemu_irq output;
78
79 XICSFabric *xics;
80};
81
82#define ICP_PROP_XICS "xics"
83#define ICP_PROP_CPU "cpu"
84
85struct PnvICPState {
86 ICPState parent_obj;
87
88 MemoryRegion mmio;
89 uint32_t links[3];
90};
91
92#define TYPE_ICS "ics"
93#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
94
95#define ICS_CLASS(klass) \
96 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
97#define ICS_GET_CLASS(obj) \
98 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
99
100struct ICSStateClass {
101 DeviceClass parent_class;
102
103 DeviceRealize parent_realize;
104 DeviceReset parent_reset;
105
106 void (*reject)(ICSState *s, uint32_t irq);
107 void (*resend)(ICSState *s);
108};
109
110struct ICSState {
111 /*< private >*/
112 DeviceState parent_obj;
113 /*< public >*/
114 uint32_t nr_irqs;
115 uint32_t offset;
116 ICSIRQState *irqs;
117 XICSFabric *xics;
118};
119
120#define ICS_PROP_XICS "xics"
121
122static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
123{
124 return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
125}
126
127struct ICSIRQState {
128 uint32_t server;
129 uint8_t priority;
130 uint8_t saved_priority;
131#define XICS_STATUS_ASSERTED 0x1
132#define XICS_STATUS_SENT 0x2
133#define XICS_STATUS_REJECTED 0x4
134#define XICS_STATUS_MASKED_PENDING 0x8
135#define XICS_STATUS_PRESENTED 0x10
136#define XICS_STATUS_QUEUED 0x20
137 uint8_t status;
138/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
139#define XICS_FLAGS_IRQ_LSI 0x1
140#define XICS_FLAGS_IRQ_MSI 0x2
141#define XICS_FLAGS_IRQ_MASK 0x3
142 uint8_t flags;
143};
144
145#define TYPE_XICS_FABRIC "xics-fabric"
146#define XICS_FABRIC(obj) \
147 INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
148#define XICS_FABRIC_CLASS(klass) \
149 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
150#define XICS_FABRIC_GET_CLASS(obj) \
151 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
152
153typedef struct XICSFabricClass {
154 InterfaceClass parent;
155 ICSState *(*ics_get)(XICSFabric *xi, int irq);
156 void (*ics_resend)(XICSFabric *xi);
157 ICPState *(*icp_get)(XICSFabric *xi, int server);
158} XICSFabricClass;
159
160ICPState *xics_icp_get(XICSFabric *xi, int server);
161
162/* Internal XICS interfaces */
163void icp_set_cppr(ICPState *icp, uint8_t cppr);
164void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
165uint32_t icp_accept(ICPState *ss);
166uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
167void icp_eoi(ICPState *icp, uint32_t xirr);
168void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
169void icp_reset(ICPState *icp);
170
171void ics_write_xive(ICSState *ics, int nr, int server,
172 uint8_t priority, uint8_t saved_priority);
173void ics_set_irq(void *opaque, int srcno, int val);
174
175static inline bool ics_irq_free(ICSState *ics, uint32_t srcno)
176{
177 return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK);
178}
179
180void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
181void icp_pic_print_info(ICPState *icp, Monitor *mon);
182void ics_pic_print_info(ICSState *ics, Monitor *mon);
183
184void ics_resend(ICSState *ics);
185void icp_resend(ICPState *ss);
186
187Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
188 Error **errp);
189void icp_destroy(ICPState *icp);
190
191/* KVM */
192void icp_get_kvm_state(ICPState *icp);
193int icp_set_kvm_state(ICPState *icp, Error **errp);
194void icp_synchronize_state(ICPState *icp);
195void icp_kvm_realize(DeviceState *dev, Error **errp);
196
197void ics_get_kvm_state(ICSState *ics);
198int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp);
199int ics_set_kvm_state(ICSState *ics, Error **errp);
200void ics_synchronize_state(ICSState *ics);
201void ics_kvm_set_irq(ICSState *ics, int srcno, int val);
202
203#endif /* XICS_H */