jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * Copyright (c) 2009 Laurent Vivier
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#ifndef HW_MAC_DBDMA_H
24#define HW_MAC_DBDMA_H
25
26#include "exec/memory.h"
27#include "qemu/iov.h"
28#include "sysemu/dma.h"
29#include "hw/sysbus.h"
30
31typedef struct DBDMA_io DBDMA_io;
32
33typedef void (*DBDMA_flush)(DBDMA_io *io);
34typedef void (*DBDMA_rw)(DBDMA_io *io);
35typedef void (*DBDMA_end)(DBDMA_io *io);
36struct DBDMA_io {
37 void *opaque;
38 void *channel;
39 hwaddr addr;
40 int len;
41 int is_last;
42 int is_dma_out;
43 DBDMA_end dma_end;
44 /* DMA is in progress, don't start another one */
45 bool processing;
46 /* DMA request */
47 void *dma_mem;
48 dma_addr_t dma_len;
49 DMADirection dir;
50};
51
52/*
53 * DBDMA control/status registers. All little-endian.
54 */
55
56#define DBDMA_CONTROL 0x00
57#define DBDMA_STATUS 0x01
58#define DBDMA_CMDPTR_HI 0x02
59#define DBDMA_CMDPTR_LO 0x03
60#define DBDMA_INTR_SEL 0x04
61#define DBDMA_BRANCH_SEL 0x05
62#define DBDMA_WAIT_SEL 0x06
63#define DBDMA_XFER_MODE 0x07
64#define DBDMA_DATA2PTR_HI 0x08
65#define DBDMA_DATA2PTR_LO 0x09
66#define DBDMA_RES1 0x0A
67#define DBDMA_ADDRESS_HI 0x0B
68#define DBDMA_BRANCH_ADDR_HI 0x0C
69#define DBDMA_RES2 0x0D
70#define DBDMA_RES3 0x0E
71#define DBDMA_RES4 0x0F
72
73#define DBDMA_REGS 16
74#define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
75
76#define DBDMA_CHANNEL_SHIFT 7
77#define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
78
79#define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
80
81/* Bits in control and status registers */
82
83#define RUN 0x8000
84#define PAUSE 0x4000
85#define FLUSH 0x2000
86#define WAKE 0x1000
87#define DEAD 0x0800
88#define ACTIVE 0x0400
89#define BT 0x0100
90#define DEVSTAT 0x00ff
91
92/*
93 * DBDMA command structure. These fields are all little-endian!
94 */
95
96typedef struct dbdma_cmd {
97 uint16_t req_count; /* requested byte transfer count */
98 uint16_t command; /* command word (has bit-fields) */
99 uint32_t phy_addr; /* physical data address */
100 uint32_t cmd_dep; /* command-dependent field */
101 uint16_t res_count; /* residual count after completion */
102 uint16_t xfer_status; /* transfer status */
103} dbdma_cmd;
104
105/* DBDMA command values in command field */
106
107#define COMMAND_MASK 0xf000
108#define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
109#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
110#define INPUT_MORE 0x2000 /* transfer stream data to memory */
111#define INPUT_LAST 0x3000 /* ditto, expect end marker */
112#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
113#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
114#define DBDMA_NOP 0x6000 /* do nothing */
115#define DBDMA_STOP 0x7000 /* suspend processing */
116
117/* Key values in command field */
118
119#define KEY_MASK 0x0700
120#define KEY_STREAM0 0x0000 /* usual data stream */
121#define KEY_STREAM1 0x0100 /* control/status stream */
122#define KEY_STREAM2 0x0200 /* device-dependent stream */
123#define KEY_STREAM3 0x0300 /* device-dependent stream */
124#define KEY_STREAM4 0x0400 /* reserved */
125#define KEY_REGS 0x0500 /* device register space */
126#define KEY_SYSTEM 0x0600 /* system memory-mapped space */
127#define KEY_DEVICE 0x0700 /* device memory-mapped space */
128
129/* Interrupt control values in command field */
130
131#define INTR_MASK 0x0030
132#define INTR_NEVER 0x0000 /* don't interrupt */
133#define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
134#define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
135#define INTR_ALWAYS 0x0030 /* always interrupt */
136
137/* Branch control values in command field */
138
139#define BR_MASK 0x000c
140#define BR_NEVER 0x0000 /* don't branch */
141#define BR_IFSET 0x0004 /* branch if condition bit is 1 */
142#define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
143#define BR_ALWAYS 0x000c /* always branch */
144
145/* Wait control values in command field */
146
147#define WAIT_MASK 0x0003
148#define WAIT_NEVER 0x0000 /* don't wait */
149#define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
150#define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
151#define WAIT_ALWAYS 0x0003 /* always wait */
152
153typedef struct DBDMA_channel {
154 int channel;
155 uint32_t regs[DBDMA_REGS];
156 qemu_irq irq;
157 DBDMA_io io;
158 DBDMA_rw rw;
159 DBDMA_flush flush;
160 dbdma_cmd current;
161} DBDMA_channel;
162
163typedef struct {
164 SysBusDevice parent_obj;
165
166 MemoryRegion mem;
167 DBDMA_channel channels[DBDMA_CHANNELS];
168 QEMUBH *bh;
169} DBDMAState;
170
171/* Externally callable functions */
172
173void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
174 DBDMA_rw rw, DBDMA_flush flush,
175 void *opaque);
176void DBDMA_kick(DBDMAState *dbdma);
177
178#define TYPE_MAC_DBDMA "mac-dbdma"
179#define MAC_DBDMA(obj) OBJECT_CHECK(DBDMAState, (obj), TYPE_MAC_DBDMA)
180
181#endif