jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * QEMU lowRISC Ibex UART device
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#ifndef HW_IBEX_UART_H
26#define HW_IBEX_UART_H
27
28#include "hw/sysbus.h"
29#include "chardev/char-fe.h"
30#include "qemu/timer.h"
31
32#define IBEX_UART_INTR_STATE 0x00
33 #define INTR_STATE_TX_WATERMARK (1 << 0)
34 #define INTR_STATE_RX_WATERMARK (1 << 1)
35 #define INTR_STATE_TX_EMPTY (1 << 2)
36 #define INTR_STATE_RX_OVERFLOW (1 << 3)
37#define IBEX_UART_INTR_ENABLE 0x04
38#define IBEX_UART_INTR_TEST 0x08
39
40#define IBEX_UART_CTRL 0x0c
41 #define UART_CTRL_TX_ENABLE (1 << 0)
42 #define UART_CTRL_RX_ENABLE (1 << 1)
43 #define UART_CTRL_NF (1 << 2)
44 #define UART_CTRL_SLPBK (1 << 4)
45 #define UART_CTRL_LLPBK (1 << 5)
46 #define UART_CTRL_PARITY_EN (1 << 6)
47 #define UART_CTRL_PARITY_ODD (1 << 7)
48 #define UART_CTRL_RXBLVL (3 << 8)
49 #define UART_CTRL_NCO (0xFFFF << 16)
50
51#define IBEX_UART_STATUS 0x10
52 #define UART_STATUS_TXFULL (1 << 0)
53 #define UART_STATUS_RXFULL (1 << 1)
54 #define UART_STATUS_TXEMPTY (1 << 2)
55 #define UART_STATUS_RXIDLE (1 << 4)
56 #define UART_STATUS_RXEMPTY (1 << 5)
57
58#define IBEX_UART_RDATA 0x14
59#define IBEX_UART_WDATA 0x18
60
61#define IBEX_UART_FIFO_CTRL 0x1c
62 #define FIFO_CTRL_RXRST (1 << 0)
63 #define FIFO_CTRL_TXRST (1 << 1)
64 #define FIFO_CTRL_RXILVL (7 << 2)
65 #define FIFO_CTRL_RXILVL_SHIFT (2)
66 #define FIFO_CTRL_TXILVL (3 << 5)
67 #define FIFO_CTRL_TXILVL_SHIFT (5)
68
69#define IBEX_UART_FIFO_STATUS 0x20
70#define IBEX_UART_OVRD 0x24
71#define IBEX_UART_VAL 0x28
72#define IBEX_UART_TIMEOUT_CTRL 0x2c
73
74#define IBEX_UART_TX_FIFO_SIZE 16
75
76#define TYPE_IBEX_UART "ibex-uart"
77#define IBEX_UART(obj) \
78 OBJECT_CHECK(IbexUartState, (obj), TYPE_IBEX_UART)
79
80typedef struct {
81 /* <private> */
82 SysBusDevice parent_obj;
83
84 /* <public> */
85 MemoryRegion mmio;
86
87 uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
88 uint32_t tx_level;
89
90 QEMUTimer *fifo_trigger_handle;
91 uint64_t char_tx_time;
92
93 uint32_t uart_intr_state;
94 uint32_t uart_intr_enable;
95 uint32_t uart_ctrl;
96 uint32_t uart_status;
97 uint32_t uart_rdata;
98 uint32_t uart_fifo_ctrl;
99 uint32_t uart_fifo_status;
100 uint32_t uart_ovrd;
101 uint32_t uart_val;
102 uint32_t uart_timeout_ctrl;
103
104 CharBackend chr;
105 qemu_irq tx_watermark;
106 qemu_irq rx_watermark;
107 qemu_irq tx_empty;
108 qemu_irq rx_overflow;
109} IbexUartState;
110#endif /* HW_IBEX_UART_H */