jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1#ifndef HW_ESCC_H
2#define HW_ESCC_H
3
4#include "chardev/char-fe.h"
5#include "chardev/char-serial.h"
6#include "hw/sysbus.h"
7#include "ui/input.h"
8
9/* escc.c */
10#define TYPE_ESCC "escc"
11#define ESCC_SIZE 4
12
13#define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC)
14
15typedef enum {
16 escc_chn_a, escc_chn_b,
17} ESCCChnID;
18
19typedef enum {
20 escc_serial, escc_kbd, escc_mouse,
21} ESCCChnType;
22
23#define ESCC_SERIO_QUEUE_SIZE 256
24
25typedef struct {
26 uint8_t data[ESCC_SERIO_QUEUE_SIZE];
27 int rptr, wptr, count;
28} ESCCSERIOQueue;
29
30#define ESCC_SERIAL_REGS 16
31typedef struct ESCCChannelState {
32 qemu_irq irq;
33 uint32_t rxint, txint, rxint_under_svc, txint_under_svc;
34 struct ESCCChannelState *otherchn;
35 uint32_t reg;
36 uint8_t wregs[ESCC_SERIAL_REGS], rregs[ESCC_SERIAL_REGS];
37 ESCCSERIOQueue queue;
38 CharBackend chr;
39 int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
40 int disabled;
41 int clock;
42 uint32_t vmstate_dummy;
43 ESCCChnID chn; /* this channel, A (base+4) or B (base+0) */
44 ESCCChnType type;
45 uint8_t rx, tx;
46 QemuInputHandlerState *hs;
47} ESCCChannelState;
48
49typedef struct ESCCState {
50 SysBusDevice parent_obj;
51
52 struct ESCCChannelState chn[2];
53 uint32_t it_shift;
54 bool bit_swap;
55 MemoryRegion mmio;
56 uint32_t disabled;
57 uint32_t frequency;
58} ESCCState;
59
60#endif