jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "hw/core/cpu.h"
24#include "sysemu/hw_accel.h"
25#include "qemu/notify.h"
26#include "qemu/log.h"
27#include "qemu/main-loop.h"
28#include "exec/log.h"
29#include "qemu/error-report.h"
30#include "qemu/qemu-print.h"
31#include "sysemu/tcg.h"
32#include "hw/boards.h"
33#include "hw/qdev-properties.h"
34#include "trace-root.h"
35#include "qemu/plugin.h"
36
37CPUInterruptHandler cpu_interrupt_handler;
38
39CPUState *cpu_by_arch_id(int64_t id)
40{
41 CPUState *cpu;
42
43 CPU_FOREACH(cpu) {
44 CPUClass *cc = CPU_GET_CLASS(cpu);
45
46 if (cc->get_arch_id(cpu) == id) {
47 return cpu;
48 }
49 }
50 return NULL;
51}
52
53bool cpu_exists(int64_t id)
54{
55 return !!cpu_by_arch_id(id);
56}
57
58CPUState *cpu_create(const char *typename)
59{
60 Error *err = NULL;
61 CPUState *cpu = CPU(object_new(typename));
62 if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
63 error_report_err(err);
64 object_unref(OBJECT(cpu));
65 exit(EXIT_FAILURE);
66 }
67 return cpu;
68}
69
70bool cpu_paging_enabled(const CPUState *cpu)
71{
72 CPUClass *cc = CPU_GET_CLASS(cpu);
73
74 return cc->get_paging_enabled(cpu);
75}
76
77static bool cpu_common_get_paging_enabled(const CPUState *cpu)
78{
79 return false;
80}
81
82void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
83 Error **errp)
84{
85 CPUClass *cc = CPU_GET_CLASS(cpu);
86
87 cc->get_memory_mapping(cpu, list, errp);
88}
89
90static void cpu_common_get_memory_mapping(CPUState *cpu,
91 MemoryMappingList *list,
92 Error **errp)
93{
94 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
95}
96
97/* Resetting the IRQ comes from across the code base so we take the
98 * BQL here if we need to. cpu_interrupt assumes it is held.*/
99void cpu_reset_interrupt(CPUState *cpu, int mask)
100{
101 bool need_lock = !qemu_mutex_iothread_locked();
102
103 if (need_lock) {
104 qemu_mutex_lock_iothread();
105 }
106 cpu->interrupt_request &= ~mask;
107 if (need_lock) {
108 qemu_mutex_unlock_iothread();
109 }
110}
111
112void cpu_exit(CPUState *cpu)
113{
114 atomic_set(&cpu->exit_request, 1);
115 /* Ensure cpu_exec will see the exit request after TCG has exited. */
116 smp_wmb();
117 atomic_set(&cpu->icount_decr_ptr->u16.high, -1);
118}
119
120int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
121 void *opaque)
122{
123 CPUClass *cc = CPU_GET_CLASS(cpu);
124
125 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
126}
127
128static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
129 CPUState *cpu, void *opaque)
130{
131 return 0;
132}
133
134int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
135 int cpuid, void *opaque)
136{
137 CPUClass *cc = CPU_GET_CLASS(cpu);
138
139 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
140}
141
142static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
143 CPUState *cpu, int cpuid,
144 void *opaque)
145{
146 return -1;
147}
148
149int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
150 void *opaque)
151{
152 CPUClass *cc = CPU_GET_CLASS(cpu);
153
154 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
155}
156
157static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
158 CPUState *cpu, void *opaque)
159{
160 return 0;
161}
162
163int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
164 int cpuid, void *opaque)
165{
166 CPUClass *cc = CPU_GET_CLASS(cpu);
167
168 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
169}
170
171static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
172 CPUState *cpu, int cpuid,
173 void *opaque)
174{
175 return -1;
176}
177
178
179static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
180{
181 return 0;
182}
183
184static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
185{
186 return 0;
187}
188
189static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
190{
191 /* If no extra check is required, QEMU watchpoint match can be considered
192 * as an architectural match.
193 */
194 return true;
195}
196
197static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
198{
199 return target_words_bigendian();
200}
201
202static void cpu_common_noop(CPUState *cpu)
203{
204}
205
206static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
207{
208 return false;
209}
210
211#if !defined(CONFIG_USER_ONLY)
212GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
213{
214 CPUClass *cc = CPU_GET_CLASS(cpu);
215 GuestPanicInformation *res = NULL;
216
217 if (cc->get_crash_info) {
218 res = cc->get_crash_info(cpu);
219 }
220 return res;
221}
222#endif
223
224void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
225{
226 CPUClass *cc = CPU_GET_CLASS(cpu);
227
228 if (cc->dump_state) {
229 cpu_synchronize_state(cpu);
230 cc->dump_state(cpu, f, flags);
231 }
232}
233
234void cpu_dump_statistics(CPUState *cpu, int flags)
235{
236 CPUClass *cc = CPU_GET_CLASS(cpu);
237
238 if (cc->dump_statistics) {
239 cc->dump_statistics(cpu, flags);
240 }
241}
242
243void cpu_reset(CPUState *cpu)
244{
245 device_cold_reset(DEVICE(cpu));
246
247 trace_guest_cpu_reset(cpu);
248}
249
250static void cpu_common_reset(DeviceState *dev)
251{
252 CPUState *cpu = CPU(dev);
253 CPUClass *cc = CPU_GET_CLASS(cpu);
254
255 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
256 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
257 log_cpu_state(cpu, cc->reset_dump_flags);
258 }
259
260 cpu->interrupt_request = 0;
261 cpu->halted = 0;
262 cpu->mem_io_pc = 0;
263 cpu->icount_extra = 0;
264 atomic_set(&cpu->icount_decr_ptr->u32, 0);
265 cpu->can_do_io = 1;
266 cpu->exception_index = -1;
267 cpu->crash_occurred = false;
268 cpu->cflags_next_tb = -1;
269
270 if (tcg_enabled()) {
271 cpu_tb_jmp_cache_clear(cpu);
272
273 tcg_flush_softmmu_tlb(cpu);
274 }
275}
276
277static bool cpu_common_has_work(CPUState *cs)
278{
279 return false;
280}
281
282ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
283{
284 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
285
286 assert(cpu_model && cc->class_by_name);
287 return cc->class_by_name(cpu_model);
288}
289
290static void cpu_common_parse_features(const char *typename, char *features,
291 Error **errp)
292{
293 char *val;
294 static bool cpu_globals_initialized;
295 /* Single "key=value" string being parsed */
296 char *featurestr = features ? strtok(features, ",") : NULL;
297
298 /* should be called only once, catch invalid users */
299 assert(!cpu_globals_initialized);
300 cpu_globals_initialized = true;
301
302 while (featurestr) {
303 val = strchr(featurestr, '=');
304 if (val) {
305 GlobalProperty *prop = g_new0(typeof(*prop), 1);
306 *val = 0;
307 val++;
308 prop->driver = typename;
309 prop->property = g_strdup(featurestr);
310 prop->value = g_strdup(val);
311 qdev_prop_register_global(prop);
312 } else {
313 error_setg(errp, "Expected key=value format, found %s.",
314 featurestr);
315 return;
316 }
317 featurestr = strtok(NULL, ",");
318 }
319}
320
321static void cpu_common_realizefn(DeviceState *dev, Error **errp)
322{
323 CPUState *cpu = CPU(dev);
324 Object *machine = qdev_get_machine();
325
326 /* qdev_get_machine() can return something that's not TYPE_MACHINE
327 * if this is one of the user-only emulators; in that case there's
328 * no need to check the ignore_memory_transaction_failures board flag.
329 */
330 if (object_dynamic_cast(machine, TYPE_MACHINE)) {
331 ObjectClass *oc = object_get_class(machine);
332 MachineClass *mc = MACHINE_CLASS(oc);
333
334 if (mc) {
335 cpu->ignore_memory_transaction_failures =
336 mc->ignore_memory_transaction_failures;
337 }
338 }
339
340 if (dev->hotplugged) {
341 cpu_synchronize_post_init(cpu);
342 cpu_resume(cpu);
343 }
344
345 /* NOTE: latest generic point where the cpu is fully realized */
346 trace_init_vcpu(cpu);
347}
348
349static void cpu_common_unrealizefn(DeviceState *dev)
350{
351 CPUState *cpu = CPU(dev);
352 /* NOTE: latest generic point before the cpu is fully unrealized */
353 trace_fini_vcpu(cpu);
354 qemu_plugin_vcpu_exit_hook(cpu);
355 cpu_exec_unrealizefn(cpu);
356}
357
358static void cpu_common_initfn(Object *obj)
359{
360 CPUState *cpu = CPU(obj);
361 CPUClass *cc = CPU_GET_CLASS(obj);
362
363 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
364 cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
365 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
366 /* *-user doesn't have configurable SMP topology */
367 /* the default value is changed by qemu_init_vcpu() for softmmu */
368 cpu->nr_cores = 1;
369 cpu->nr_threads = 1;
370
371 qemu_mutex_init(&cpu->work_mutex);
372 QSIMPLEQ_INIT(&cpu->work_list);
373 QTAILQ_INIT(&cpu->breakpoints);
374 QTAILQ_INIT(&cpu->watchpoints);
375
376 cpu_exec_initfn(cpu);
377}
378
379static void cpu_common_finalize(Object *obj)
380{
381 CPUState *cpu = CPU(obj);
382
383 qemu_mutex_destroy(&cpu->work_mutex);
384}
385
386static int64_t cpu_common_get_arch_id(CPUState *cpu)
387{
388 return cpu->cpu_index;
389}
390
391static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
392{
393 return addr;
394}
395
396static void generic_handle_interrupt(CPUState *cpu, int mask)
397{
398 cpu->interrupt_request |= mask;
399
400 if (!qemu_cpu_is_self(cpu)) {
401 qemu_cpu_kick(cpu);
402 }
403}
404
405CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt;
406
407static void cpu_class_init(ObjectClass *klass, void *data)
408{
409 DeviceClass *dc = DEVICE_CLASS(klass);
410 CPUClass *k = CPU_CLASS(klass);
411
412 k->parse_features = cpu_common_parse_features;
413 k->get_arch_id = cpu_common_get_arch_id;
414 k->has_work = cpu_common_has_work;
415 k->get_paging_enabled = cpu_common_get_paging_enabled;
416 k->get_memory_mapping = cpu_common_get_memory_mapping;
417 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
418 k->write_elf32_note = cpu_common_write_elf32_note;
419 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
420 k->write_elf64_note = cpu_common_write_elf64_note;
421 k->gdb_read_register = cpu_common_gdb_read_register;
422 k->gdb_write_register = cpu_common_gdb_write_register;
423 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
424 k->debug_excp_handler = cpu_common_noop;
425 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
426 k->cpu_exec_enter = cpu_common_noop;
427 k->cpu_exec_exit = cpu_common_noop;
428 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
429 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
430 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
431 dc->realize = cpu_common_realizefn;
432 dc->unrealize = cpu_common_unrealizefn;
433 dc->reset = cpu_common_reset;
434 device_class_set_props(dc, cpu_common_props);
435 /*
436 * Reason: CPUs still need special care by board code: wiring up
437 * IRQs, adding reset handlers, halting non-first CPUs, ...
438 */
439 dc->user_creatable = false;
440}
441
442static const TypeInfo cpu_type_info = {
443 .name = TYPE_CPU,
444 .parent = TYPE_DEVICE,
445 .instance_size = sizeof(CPUState),
446 .instance_init = cpu_common_initfn,
447 .instance_finalize = cpu_common_finalize,
448 .abstract = true,
449 .class_size = sizeof(CPUClass),
450 .class_init = cpu_class_init,
451};
452
453static void cpu_register_types(void)
454{
455 type_register_static(&cpu_type_info);
456}
457
458type_init(cpu_register_types)