jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H
3
4/* CPU interfaces that are target independent. */
5
6#ifndef CONFIG_USER_ONLY
7#include "exec/hwaddr.h"
8#endif
9
10/* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
11void qemu_init_cpu_list(void);
12void cpu_list_lock(void);
13void cpu_list_unlock(void);
14
15void tcg_flush_softmmu_tlb(CPUState *cs);
16
17#if !defined(CONFIG_USER_ONLY)
18
19enum device_endian {
20 DEVICE_NATIVE_ENDIAN,
21 DEVICE_BIG_ENDIAN,
22 DEVICE_LITTLE_ENDIAN,
23};
24
25#if defined(HOST_WORDS_BIGENDIAN)
26#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
27#else
28#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
29#endif
30
31/* address in the RAM (different from a physical address) */
32#if defined(CONFIG_XEN_BACKEND)
33typedef uint64_t ram_addr_t;
34# define RAM_ADDR_MAX UINT64_MAX
35# define RAM_ADDR_FMT "%" PRIx64
36#else
37typedef uintptr_t ram_addr_t;
38# define RAM_ADDR_MAX UINTPTR_MAX
39# define RAM_ADDR_FMT "%" PRIxPTR
40#endif
41
42extern ram_addr_t ram_size;
43
44/* memory API */
45
46typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
47typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
48
49void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
50/* This should not be used by devices. */
51ram_addr_t qemu_ram_addr_from_host(void *ptr);
52RAMBlock *qemu_ram_block_by_name(const char *name);
53RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
54 ram_addr_t *offset);
55ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
56void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
57void qemu_ram_unset_idstr(RAMBlock *block);
58const char *qemu_ram_get_idstr(RAMBlock *rb);
59void *qemu_ram_get_host_addr(RAMBlock *rb);
60ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
61ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
62bool qemu_ram_is_shared(RAMBlock *rb);
63bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
64void qemu_ram_set_uf_zeroable(RAMBlock *rb);
65bool qemu_ram_is_migratable(RAMBlock *rb);
66void qemu_ram_set_migratable(RAMBlock *rb);
67void qemu_ram_unset_migratable(RAMBlock *rb);
68
69size_t qemu_ram_pagesize(RAMBlock *block);
70size_t qemu_ram_pagesize_largest(void);
71
72void cpu_physical_memory_rw(hwaddr addr, void *buf,
73 hwaddr len, bool is_write);
74static inline void cpu_physical_memory_read(hwaddr addr,
75 void *buf, hwaddr len)
76{
77 cpu_physical_memory_rw(addr, buf, len, false);
78}
79static inline void cpu_physical_memory_write(hwaddr addr,
80 const void *buf, hwaddr len)
81{
82 cpu_physical_memory_rw(addr, (void *)buf, len, true);
83}
84void *cpu_physical_memory_map(hwaddr addr,
85 hwaddr *plen,
86 bool is_write);
87void cpu_physical_memory_unmap(void *buffer, hwaddr len,
88 bool is_write, hwaddr access_len);
89void cpu_register_map_client(QEMUBH *bh);
90void cpu_unregister_map_client(QEMUBH *bh);
91
92bool cpu_physical_memory_is_io(hwaddr phys_addr);
93
94/* Coalesced MMIO regions are areas where write operations can be reordered.
95 * This usually implies that write operations are side-effect free. This allows
96 * batching which can make a major impact on performance when using
97 * virtualization.
98 */
99void qemu_flush_coalesced_mmio_buffer(void);
100
101void cpu_flush_icache_range(hwaddr start, hwaddr len);
102
103typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
104
105int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
106int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
107
108#endif
109
110#endif /* CPU_COMMON_H */