jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1#ifndef CPU_COMMON_H
2#define CPU_COMMON_H
3
4/* CPU interfaces that are target independent. */
5
6#ifndef CONFIG_USER_ONLY
7#include "exec/hwaddr.h"
8#endif
9
10#include "qemu/bswap.h"
11#include "qemu/queue.h"
12#include "qemu/fprintf-fn.h"
13
14/**
15 * CPUListState:
16 * @cpu_fprintf: Print function.
17 * @file: File to print to using @cpu_fprint.
18 *
19 * State commonly used for iterating over CPU models.
20 */
21typedef struct CPUListState {
22 fprintf_function cpu_fprintf;
23 FILE *file;
24} CPUListState;
25
26/* The CPU list lock nests outside tb_lock/tb_unlock. */
27void qemu_init_cpu_list(void);
28void cpu_list_lock(void);
29void cpu_list_unlock(void);
30
31void tcg_flush_softmmu_tlb(CPUState *cs);
32
33#if !defined(CONFIG_USER_ONLY)
34
35enum device_endian {
36 DEVICE_NATIVE_ENDIAN,
37 DEVICE_BIG_ENDIAN,
38 DEVICE_LITTLE_ENDIAN,
39};
40
41#if defined(HOST_WORDS_BIGENDIAN)
42#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
43#else
44#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
45#endif
46
47/* address in the RAM (different from a physical address) */
48#if defined(CONFIG_XEN_BACKEND)
49typedef uint64_t ram_addr_t;
50# define RAM_ADDR_MAX UINT64_MAX
51# define RAM_ADDR_FMT "%" PRIx64
52#else
53typedef uintptr_t ram_addr_t;
54# define RAM_ADDR_MAX UINTPTR_MAX
55# define RAM_ADDR_FMT "%" PRIxPTR
56#endif
57
58extern ram_addr_t ram_size;
59
60/* memory API */
61
62typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
63typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
64
65void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
66/* This should not be used by devices. */
67ram_addr_t qemu_ram_addr_from_host(void *ptr);
68RAMBlock *qemu_ram_block_by_name(const char *name);
69RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
70 ram_addr_t *offset);
71ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
72void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
73void qemu_ram_unset_idstr(RAMBlock *block);
74const char *qemu_ram_get_idstr(RAMBlock *rb);
75bool qemu_ram_is_shared(RAMBlock *rb);
76bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
77void qemu_ram_set_uf_zeroable(RAMBlock *rb);
78
79size_t qemu_ram_pagesize(RAMBlock *block);
80size_t qemu_ram_pagesize_largest(void);
81
82void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
83 int len, int is_write);
84static inline void cpu_physical_memory_read(hwaddr addr,
85 void *buf, int len)
86{
87 cpu_physical_memory_rw(addr, buf, len, 0);
88}
89static inline void cpu_physical_memory_write(hwaddr addr,
90 const void *buf, int len)
91{
92 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
93}
94void *cpu_physical_memory_map(hwaddr addr,
95 hwaddr *plen,
96 int is_write);
97void cpu_physical_memory_unmap(void *buffer, hwaddr len,
98 int is_write, hwaddr access_len);
99void cpu_register_map_client(QEMUBH *bh);
100void cpu_unregister_map_client(QEMUBH *bh);
101
102bool cpu_physical_memory_is_io(hwaddr phys_addr);
103
104/* Coalesced MMIO regions are areas where write operations can be reordered.
105 * This usually implies that write operations are side-effect free. This allows
106 * batching which can make a major impact on performance when using
107 * virtualization.
108 */
109void qemu_flush_coalesced_mmio_buffer(void);
110
111void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
112 const uint8_t *buf, int len);
113void cpu_flush_icache_range(hwaddr start, int len);
114
115extern struct MemoryRegion io_mem_rom;
116extern struct MemoryRegion io_mem_notdirty;
117
118typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
119 ram_addr_t offset, ram_addr_t length, void *opaque);
120
121int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
122int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
123
124#endif
125
126#endif /* CPU_COMMON_H */