jcs.org
qemu with hax to log dma reads & writes
jcs.org/2018/11/12/vfio
1/*
2 * QEMU float support
3 *
4 * The code in this source file is derived from release 2a of the SoftFloat
5 * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
6 * some later contributions) are provided under that license, as detailed below.
7 * It has subsequently been modified by contributors to the QEMU Project,
8 * so some portions are provided under:
9 * the SoftFloat-2a license
10 * the BSD license
11 * GPL-v2-or-later
12 *
13 * Any future contributions to this file after December 1st 2014 will be
14 * taken to be licensed under the Softfloat-2a license unless specifically
15 * indicated otherwise.
16 */
17
18/*
19===============================================================================
20This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
21Arithmetic Package, Release 2a.
22
23Written by John R. Hauser. This work was made possible in part by the
24International Computer Science Institute, located at Suite 600, 1947 Center
25Street, Berkeley, California 94704. Funding was partially provided by the
26National Science Foundation under grant MIP-9311980. The original version
27of this code was written as part of a project to build a fixed-point vector
28processor in collaboration with the University of California at Berkeley,
29overseen by Profs. Nelson Morgan and John Wawrzynek. More information
30is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
31arithmetic/SoftFloat.html'.
32
33THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
34has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
35TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
36PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
37AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
38
39Derivative works are acceptable, even for commercial purposes, so long as
40(1) they include prominent notice that the work is derivative, and (2) they
41include prominent notice akin to these four paragraphs for those parts of
42this code that are retained.
43
44===============================================================================
45*/
46
47/* BSD licensing:
48 * Copyright (c) 2006, Fabrice Bellard
49 * All rights reserved.
50 *
51 * Redistribution and use in source and binary forms, with or without
52 * modification, are permitted provided that the following conditions are met:
53 *
54 * 1. Redistributions of source code must retain the above copyright notice,
55 * this list of conditions and the following disclaimer.
56 *
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 *
61 * 3. Neither the name of the copyright holder nor the names of its contributors
62 * may be used to endorse or promote products derived from this software without
63 * specific prior written permission.
64 *
65 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
66 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
68 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
69 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
75 * THE POSSIBILITY OF SUCH DAMAGE.
76 */
77
78/* Portions of this work are licensed under the terms of the GNU GPL,
79 * version 2 or later. See the COPYING file in the top-level directory.
80 */
81
82#if defined(TARGET_XTENSA)
83/* Define for architectures which deviate from IEEE in not supporting
84 * signaling NaNs (so all NaNs are treated as quiet).
85 */
86#define NO_SIGNALING_NANS 1
87#endif
88
89/*----------------------------------------------------------------------------
90| The pattern for a default generated half-precision NaN.
91*----------------------------------------------------------------------------*/
92float16 float16_default_nan(float_status *status)
93{
94#if defined(TARGET_ARM)
95 return const_float16(0x7E00);
96#else
97 if (status->snan_bit_is_one) {
98 return const_float16(0x7DFF);
99 } else {
100#if defined(TARGET_MIPS)
101 return const_float16(0x7E00);
102#else
103 return const_float16(0xFE00);
104#endif
105 }
106#endif
107}
108
109/*----------------------------------------------------------------------------
110| The pattern for a default generated single-precision NaN.
111*----------------------------------------------------------------------------*/
112float32 float32_default_nan(float_status *status)
113{
114#if defined(TARGET_SPARC) || defined(TARGET_M68K)
115 return const_float32(0x7FFFFFFF);
116#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
117 defined(TARGET_XTENSA) || defined(TARGET_S390X) || \
118 defined(TARGET_TRICORE) || defined(TARGET_RISCV)
119 return const_float32(0x7FC00000);
120#elif defined(TARGET_HPPA)
121 return const_float32(0x7FA00000);
122#else
123 if (status->snan_bit_is_one) {
124 return const_float32(0x7FBFFFFF);
125 } else {
126#if defined(TARGET_MIPS)
127 return const_float32(0x7FC00000);
128#else
129 return const_float32(0xFFC00000);
130#endif
131 }
132#endif
133}
134
135/*----------------------------------------------------------------------------
136| The pattern for a default generated double-precision NaN.
137*----------------------------------------------------------------------------*/
138float64 float64_default_nan(float_status *status)
139{
140#if defined(TARGET_SPARC) || defined(TARGET_M68K)
141 return const_float64(LIT64(0x7FFFFFFFFFFFFFFF));
142#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
143 defined(TARGET_S390X) || defined(TARGET_RISCV)
144 return const_float64(LIT64(0x7FF8000000000000));
145#elif defined(TARGET_HPPA)
146 return const_float64(LIT64(0x7FF4000000000000));
147#else
148 if (status->snan_bit_is_one) {
149 return const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
150 } else {
151#if defined(TARGET_MIPS)
152 return const_float64(LIT64(0x7FF8000000000000));
153#else
154 return const_float64(LIT64(0xFFF8000000000000));
155#endif
156 }
157#endif
158}
159
160/*----------------------------------------------------------------------------
161| The pattern for a default generated extended double-precision NaN.
162*----------------------------------------------------------------------------*/
163floatx80 floatx80_default_nan(float_status *status)
164{
165 floatx80 r;
166#if defined(TARGET_M68K)
167 r.low = LIT64(0xFFFFFFFFFFFFFFFF);
168 r.high = 0x7FFF;
169#else
170 if (status->snan_bit_is_one) {
171 r.low = LIT64(0xBFFFFFFFFFFFFFFF);
172 r.high = 0x7FFF;
173 } else {
174 r.low = LIT64(0xC000000000000000);
175 r.high = 0xFFFF;
176 }
177#endif
178 return r;
179}
180
181/*----------------------------------------------------------------------------
182| The pattern for a default generated extended double-precision inf.
183*----------------------------------------------------------------------------*/
184
185#define floatx80_infinity_high 0x7FFF
186#if defined(TARGET_M68K)
187#define floatx80_infinity_low LIT64(0x0000000000000000)
188#else
189#define floatx80_infinity_low LIT64(0x8000000000000000)
190#endif
191
192const floatx80 floatx80_infinity
193 = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
194
195/*----------------------------------------------------------------------------
196| The pattern for a default generated quadruple-precision NaN.
197*----------------------------------------------------------------------------*/
198float128 float128_default_nan(float_status *status)
199{
200 float128 r;
201
202 if (status->snan_bit_is_one) {
203 r.low = LIT64(0xFFFFFFFFFFFFFFFF);
204 r.high = LIT64(0x7FFF7FFFFFFFFFFF);
205 } else {
206 r.low = LIT64(0x0000000000000000);
207#if defined(TARGET_S390X) || defined(TARGET_PPC) || defined(TARGET_RISCV)
208 r.high = LIT64(0x7FFF800000000000);
209#else
210 r.high = LIT64(0xFFFF800000000000);
211#endif
212 }
213 return r;
214}
215
216/*----------------------------------------------------------------------------
217| Raises the exceptions specified by `flags'. Floating-point traps can be
218| defined here if desired. It is currently not possible for such a trap
219| to substitute a result value. If traps are not implemented, this routine
220| should be simply `float_exception_flags |= flags;'.
221*----------------------------------------------------------------------------*/
222
223void float_raise(uint8_t flags, float_status *status)
224{
225 status->float_exception_flags |= flags;
226}
227
228/*----------------------------------------------------------------------------
229| Internal canonical NaN format.
230*----------------------------------------------------------------------------*/
231typedef struct {
232 flag sign;
233 uint64_t high, low;
234} commonNaNT;
235
236#ifdef NO_SIGNALING_NANS
237int float16_is_quiet_nan(float16 a_, float_status *status)
238{
239 return float16_is_any_nan(a_);
240}
241
242int float16_is_signaling_nan(float16 a_, float_status *status)
243{
244 return 0;
245}
246#else
247/*----------------------------------------------------------------------------
248| Returns 1 if the half-precision floating-point value `a' is a quiet
249| NaN; otherwise returns 0.
250*----------------------------------------------------------------------------*/
251
252int float16_is_quiet_nan(float16 a_, float_status *status)
253{
254 uint16_t a = float16_val(a_);
255 if (status->snan_bit_is_one) {
256 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
257 } else {
258 return ((a & ~0x8000) >= 0x7C80);
259 }
260}
261
262/*----------------------------------------------------------------------------
263| Returns 1 if the half-precision floating-point value `a' is a signaling
264| NaN; otherwise returns 0.
265*----------------------------------------------------------------------------*/
266
267int float16_is_signaling_nan(float16 a_, float_status *status)
268{
269 uint16_t a = float16_val(a_);
270 if (status->snan_bit_is_one) {
271 return ((a & ~0x8000) >= 0x7C80);
272 } else {
273 return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
274 }
275}
276#endif
277
278/*----------------------------------------------------------------------------
279| Returns a quiet NaN if the half-precision floating point value `a' is a
280| signaling NaN; otherwise returns `a'.
281*----------------------------------------------------------------------------*/
282float16 float16_maybe_silence_nan(float16 a_, float_status *status)
283{
284 if (float16_is_signaling_nan(a_, status)) {
285 if (status->snan_bit_is_one) {
286 return float16_default_nan(status);
287 } else {
288 uint16_t a = float16_val(a_);
289 a |= (1 << 9);
290 return make_float16(a);
291 }
292 }
293 return a_;
294}
295
296/*----------------------------------------------------------------------------
297| Returns the result of converting the half-precision floating-point NaN
298| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
299| exception is raised.
300*----------------------------------------------------------------------------*/
301
302static commonNaNT float16ToCommonNaN(float16 a, float_status *status)
303{
304 commonNaNT z;
305
306 if (float16_is_signaling_nan(a, status)) {
307 float_raise(float_flag_invalid, status);
308 }
309 z.sign = float16_val(a) >> 15;
310 z.low = 0;
311 z.high = ((uint64_t) float16_val(a)) << 54;
312 return z;
313}
314
315/*----------------------------------------------------------------------------
316| Returns the result of converting the canonical NaN `a' to the half-
317| precision floating-point format.
318*----------------------------------------------------------------------------*/
319
320static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
321{
322 uint16_t mantissa = a.high >> 54;
323
324 if (status->default_nan_mode) {
325 return float16_default_nan(status);
326 }
327
328 if (mantissa) {
329 return make_float16(((((uint16_t) a.sign) << 15)
330 | (0x1F << 10) | mantissa));
331 } else {
332 return float16_default_nan(status);
333 }
334}
335
336#ifdef NO_SIGNALING_NANS
337int float32_is_quiet_nan(float32 a_, float_status *status)
338{
339 return float32_is_any_nan(a_);
340}
341
342int float32_is_signaling_nan(float32 a_, float_status *status)
343{
344 return 0;
345}
346#else
347/*----------------------------------------------------------------------------
348| Returns 1 if the single-precision floating-point value `a' is a quiet
349| NaN; otherwise returns 0.
350*----------------------------------------------------------------------------*/
351
352int float32_is_quiet_nan(float32 a_, float_status *status)
353{
354 uint32_t a = float32_val(a_);
355 if (status->snan_bit_is_one) {
356 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
357 } else {
358 return ((uint32_t)(a << 1) >= 0xFF800000);
359 }
360}
361
362/*----------------------------------------------------------------------------
363| Returns 1 if the single-precision floating-point value `a' is a signaling
364| NaN; otherwise returns 0.
365*----------------------------------------------------------------------------*/
366
367int float32_is_signaling_nan(float32 a_, float_status *status)
368{
369 uint32_t a = float32_val(a_);
370 if (status->snan_bit_is_one) {
371 return ((uint32_t)(a << 1) >= 0xFF800000);
372 } else {
373 return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
374 }
375}
376#endif
377
378/*----------------------------------------------------------------------------
379| Returns a quiet NaN if the single-precision floating point value `a' is a
380| signaling NaN; otherwise returns `a'.
381*----------------------------------------------------------------------------*/
382
383float32 float32_maybe_silence_nan(float32 a_, float_status *status)
384{
385 if (float32_is_signaling_nan(a_, status)) {
386 if (status->snan_bit_is_one) {
387#ifdef TARGET_HPPA
388 uint32_t a = float32_val(a_);
389 a &= ~0x00400000;
390 a |= 0x00200000;
391 return make_float32(a);
392#else
393 return float32_default_nan(status);
394#endif
395 } else {
396 uint32_t a = float32_val(a_);
397 a |= (1 << 22);
398 return make_float32(a);
399 }
400 }
401 return a_;
402}
403
404/*----------------------------------------------------------------------------
405| Returns the result of converting the single-precision floating-point NaN
406| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
407| exception is raised.
408*----------------------------------------------------------------------------*/
409
410static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
411{
412 commonNaNT z;
413
414 if (float32_is_signaling_nan(a, status)) {
415 float_raise(float_flag_invalid, status);
416 }
417 z.sign = float32_val(a) >> 31;
418 z.low = 0;
419 z.high = ((uint64_t)float32_val(a)) << 41;
420 return z;
421}
422
423/*----------------------------------------------------------------------------
424| Returns the result of converting the canonical NaN `a' to the single-
425| precision floating-point format.
426*----------------------------------------------------------------------------*/
427
428static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
429{
430 uint32_t mantissa = a.high >> 41;
431
432 if (status->default_nan_mode) {
433 return float32_default_nan(status);
434 }
435
436 if (mantissa) {
437 return make_float32(
438 (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
439 } else {
440 return float32_default_nan(status);
441 }
442}
443
444/*----------------------------------------------------------------------------
445| Select which NaN to propagate for a two-input operation.
446| IEEE754 doesn't specify all the details of this, so the
447| algorithm is target-specific.
448| The routine is passed various bits of information about the
449| two NaNs and should return 0 to select NaN a and 1 for NaN b.
450| Note that signalling NaNs are always squashed to quiet NaNs
451| by the caller, by calling floatXX_maybe_silence_nan() before
452| returning them.
453|
454| aIsLargerSignificand is only valid if both a and b are NaNs
455| of some kind, and is true if a has the larger significand,
456| or if both a and b have the same significand but a is
457| positive but b is negative. It is only needed for the x87
458| tie-break rule.
459*----------------------------------------------------------------------------*/
460
461#if defined(TARGET_ARM)
462static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
463 flag aIsLargerSignificand)
464{
465 /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
466 * the first of:
467 * 1. A if it is signaling
468 * 2. B if it is signaling
469 * 3. A (quiet)
470 * 4. B (quiet)
471 * A signaling NaN is always quietened before returning it.
472 */
473 if (aIsSNaN) {
474 return 0;
475 } else if (bIsSNaN) {
476 return 1;
477 } else if (aIsQNaN) {
478 return 0;
479 } else {
480 return 1;
481 }
482}
483#elif defined(TARGET_MIPS) || defined(TARGET_HPPA)
484static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
485 flag aIsLargerSignificand)
486{
487 /* According to MIPS specifications, if one of the two operands is
488 * a sNaN, a new qNaN has to be generated. This is done in
489 * floatXX_maybe_silence_nan(). For qNaN inputs the specifications
490 * says: "When possible, this QNaN result is one of the operand QNaN
491 * values." In practice it seems that most implementations choose
492 * the first operand if both operands are qNaN. In short this gives
493 * the following rules:
494 * 1. A if it is signaling
495 * 2. B if it is signaling
496 * 3. A (quiet)
497 * 4. B (quiet)
498 * A signaling NaN is always silenced before returning it.
499 */
500 if (aIsSNaN) {
501 return 0;
502 } else if (bIsSNaN) {
503 return 1;
504 } else if (aIsQNaN) {
505 return 0;
506 } else {
507 return 1;
508 }
509}
510#elif defined(TARGET_PPC) || defined(TARGET_XTENSA)
511static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
512 flag aIsLargerSignificand)
513{
514 /* PowerPC propagation rules:
515 * 1. A if it sNaN or qNaN
516 * 2. B if it sNaN or qNaN
517 * A signaling NaN is always silenced before returning it.
518 */
519 if (aIsSNaN || aIsQNaN) {
520 return 0;
521 } else {
522 return 1;
523 }
524}
525#elif defined(TARGET_M68K)
526static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
527 flag aIsLargerSignificand)
528{
529 /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
530 * 3.4 FLOATING-POINT INSTRUCTION DETAILS
531 * If either operand, but not both operands, of an operation is a
532 * nonsignaling NaN, then that NaN is returned as the result. If both
533 * operands are nonsignaling NaNs, then the destination operand
534 * nonsignaling NaN is returned as the result.
535 * If either operand to an operation is a signaling NaN (SNaN), then the
536 * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
537 * is set in the FPCR ENABLE byte, then the exception is taken and the
538 * destination is not modified. If the SNaN exception enable bit is not
539 * set, setting the SNaN bit in the operand to a one converts the SNaN to
540 * a nonsignaling NaN. The operation then continues as described in the
541 * preceding paragraph for nonsignaling NaNs.
542 */
543 if (aIsQNaN || aIsSNaN) { /* a is the destination operand */
544 return 0; /* return the destination operand */
545 } else {
546 return 1; /* return b */
547 }
548}
549#else
550static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
551 flag aIsLargerSignificand)
552{
553 /* This implements x87 NaN propagation rules:
554 * SNaN + QNaN => return the QNaN
555 * two SNaNs => return the one with the larger significand, silenced
556 * two QNaNs => return the one with the larger significand
557 * SNaN and a non-NaN => return the SNaN, silenced
558 * QNaN and a non-NaN => return the QNaN
559 *
560 * If we get down to comparing significands and they are the same,
561 * return the NaN with the positive sign bit (if any).
562 */
563 if (aIsSNaN) {
564 if (bIsSNaN) {
565 return aIsLargerSignificand ? 0 : 1;
566 }
567 return bIsQNaN ? 1 : 0;
568 } else if (aIsQNaN) {
569 if (bIsSNaN || !bIsQNaN) {
570 return 0;
571 } else {
572 return aIsLargerSignificand ? 0 : 1;
573 }
574 } else {
575 return 1;
576 }
577}
578#endif
579
580/*----------------------------------------------------------------------------
581| Select which NaN to propagate for a three-input operation.
582| For the moment we assume that no CPU needs the 'larger significand'
583| information.
584| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
585*----------------------------------------------------------------------------*/
586#if defined(TARGET_ARM)
587static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
588 flag cIsQNaN, flag cIsSNaN, flag infzero,
589 float_status *status)
590{
591 /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
592 * the default NaN
593 */
594 if (infzero && cIsQNaN) {
595 float_raise(float_flag_invalid, status);
596 return 3;
597 }
598
599 /* This looks different from the ARM ARM pseudocode, because the ARM ARM
600 * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
601 */
602 if (cIsSNaN) {
603 return 2;
604 } else if (aIsSNaN) {
605 return 0;
606 } else if (bIsSNaN) {
607 return 1;
608 } else if (cIsQNaN) {
609 return 2;
610 } else if (aIsQNaN) {
611 return 0;
612 } else {
613 return 1;
614 }
615}
616#elif defined(TARGET_MIPS)
617static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
618 flag cIsQNaN, flag cIsSNaN, flag infzero,
619 float_status *status)
620{
621 /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
622 * the default NaN
623 */
624 if (infzero) {
625 float_raise(float_flag_invalid, status);
626 return 3;
627 }
628
629 if (status->snan_bit_is_one) {
630 /* Prefer sNaN over qNaN, in the a, b, c order. */
631 if (aIsSNaN) {
632 return 0;
633 } else if (bIsSNaN) {
634 return 1;
635 } else if (cIsSNaN) {
636 return 2;
637 } else if (aIsQNaN) {
638 return 0;
639 } else if (bIsQNaN) {
640 return 1;
641 } else {
642 return 2;
643 }
644 } else {
645 /* Prefer sNaN over qNaN, in the c, a, b order. */
646 if (cIsSNaN) {
647 return 2;
648 } else if (aIsSNaN) {
649 return 0;
650 } else if (bIsSNaN) {
651 return 1;
652 } else if (cIsQNaN) {
653 return 2;
654 } else if (aIsQNaN) {
655 return 0;
656 } else {
657 return 1;
658 }
659 }
660}
661#elif defined(TARGET_PPC)
662static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
663 flag cIsQNaN, flag cIsSNaN, flag infzero,
664 float_status *status)
665{
666 /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
667 * to return an input NaN if we have one (ie c) rather than generating
668 * a default NaN
669 */
670 if (infzero) {
671 float_raise(float_flag_invalid, status);
672 return 2;
673 }
674
675 /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
676 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
677 */
678 if (aIsSNaN || aIsQNaN) {
679 return 0;
680 } else if (cIsSNaN || cIsQNaN) {
681 return 2;
682 } else {
683 return 1;
684 }
685}
686#else
687/* A default implementation: prefer a to b to c.
688 * This is unlikely to actually match any real implementation.
689 */
690static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
691 flag cIsQNaN, flag cIsSNaN, flag infzero,
692 float_status *status)
693{
694 if (aIsSNaN || aIsQNaN) {
695 return 0;
696 } else if (bIsSNaN || bIsQNaN) {
697 return 1;
698 } else {
699 return 2;
700 }
701}
702#endif
703
704/*----------------------------------------------------------------------------
705| Takes two single-precision floating-point values `a' and `b', one of which
706| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
707| signaling NaN, the invalid exception is raised.
708*----------------------------------------------------------------------------*/
709
710static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
711{
712 flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
713 flag aIsLargerSignificand;
714 uint32_t av, bv;
715
716 aIsQuietNaN = float32_is_quiet_nan(a, status);
717 aIsSignalingNaN = float32_is_signaling_nan(a, status);
718 bIsQuietNaN = float32_is_quiet_nan(b, status);
719 bIsSignalingNaN = float32_is_signaling_nan(b, status);
720 av = float32_val(a);
721 bv = float32_val(b);
722
723 if (aIsSignalingNaN | bIsSignalingNaN) {
724 float_raise(float_flag_invalid, status);
725 }
726
727 if (status->default_nan_mode) {
728 return float32_default_nan(status);
729 }
730
731 if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
732 aIsLargerSignificand = 0;
733 } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
734 aIsLargerSignificand = 1;
735 } else {
736 aIsLargerSignificand = (av < bv) ? 1 : 0;
737 }
738
739 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
740 aIsLargerSignificand)) {
741 return float32_maybe_silence_nan(b, status);
742 } else {
743 return float32_maybe_silence_nan(a, status);
744 }
745}
746
747#ifdef NO_SIGNALING_NANS
748int float64_is_quiet_nan(float64 a_, float_status *status)
749{
750 return float64_is_any_nan(a_);
751}
752
753int float64_is_signaling_nan(float64 a_, float_status *status)
754{
755 return 0;
756}
757#else
758/*----------------------------------------------------------------------------
759| Returns 1 if the double-precision floating-point value `a' is a quiet
760| NaN; otherwise returns 0.
761*----------------------------------------------------------------------------*/
762
763int float64_is_quiet_nan(float64 a_, float_status *status)
764{
765 uint64_t a = float64_val(a_);
766 if (status->snan_bit_is_one) {
767 return (((a >> 51) & 0xFFF) == 0xFFE)
768 && (a & 0x0007FFFFFFFFFFFFULL);
769 } else {
770 return ((a << 1) >= 0xFFF0000000000000ULL);
771 }
772}
773
774/*----------------------------------------------------------------------------
775| Returns 1 if the double-precision floating-point value `a' is a signaling
776| NaN; otherwise returns 0.
777*----------------------------------------------------------------------------*/
778
779int float64_is_signaling_nan(float64 a_, float_status *status)
780{
781 uint64_t a = float64_val(a_);
782 if (status->snan_bit_is_one) {
783 return ((a << 1) >= 0xFFF0000000000000ULL);
784 } else {
785 return (((a >> 51) & 0xFFF) == 0xFFE)
786 && (a & LIT64(0x0007FFFFFFFFFFFF));
787 }
788}
789#endif
790
791/*----------------------------------------------------------------------------
792| Returns a quiet NaN if the double-precision floating point value `a' is a
793| signaling NaN; otherwise returns `a'.
794*----------------------------------------------------------------------------*/
795
796float64 float64_maybe_silence_nan(float64 a_, float_status *status)
797{
798 if (float64_is_signaling_nan(a_, status)) {
799 if (status->snan_bit_is_one) {
800#ifdef TARGET_HPPA
801 uint64_t a = float64_val(a_);
802 a &= ~0x0008000000000000ULL;
803 a |= 0x0004000000000000ULL;
804 return make_float64(a);
805#else
806 return float64_default_nan(status);
807#endif
808 } else {
809 uint64_t a = float64_val(a_);
810 a |= LIT64(0x0008000000000000);
811 return make_float64(a);
812 }
813 }
814 return a_;
815}
816
817/*----------------------------------------------------------------------------
818| Returns the result of converting the double-precision floating-point NaN
819| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
820| exception is raised.
821*----------------------------------------------------------------------------*/
822
823static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
824{
825 commonNaNT z;
826
827 if (float64_is_signaling_nan(a, status)) {
828 float_raise(float_flag_invalid, status);
829 }
830 z.sign = float64_val(a) >> 63;
831 z.low = 0;
832 z.high = float64_val(a) << 12;
833 return z;
834}
835
836/*----------------------------------------------------------------------------
837| Returns the result of converting the canonical NaN `a' to the double-
838| precision floating-point format.
839*----------------------------------------------------------------------------*/
840
841static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
842{
843 uint64_t mantissa = a.high >> 12;
844
845 if (status->default_nan_mode) {
846 return float64_default_nan(status);
847 }
848
849 if (mantissa) {
850 return make_float64(
851 (((uint64_t) a.sign) << 63)
852 | LIT64(0x7FF0000000000000)
853 | (a.high >> 12));
854 } else {
855 return float64_default_nan(status);
856 }
857}
858
859/*----------------------------------------------------------------------------
860| Takes two double-precision floating-point values `a' and `b', one of which
861| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
862| signaling NaN, the invalid exception is raised.
863*----------------------------------------------------------------------------*/
864
865static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
866{
867 flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
868 flag aIsLargerSignificand;
869 uint64_t av, bv;
870
871 aIsQuietNaN = float64_is_quiet_nan(a, status);
872 aIsSignalingNaN = float64_is_signaling_nan(a, status);
873 bIsQuietNaN = float64_is_quiet_nan(b, status);
874 bIsSignalingNaN = float64_is_signaling_nan(b, status);
875 av = float64_val(a);
876 bv = float64_val(b);
877
878 if (aIsSignalingNaN | bIsSignalingNaN) {
879 float_raise(float_flag_invalid, status);
880 }
881
882 if (status->default_nan_mode) {
883 return float64_default_nan(status);
884 }
885
886 if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
887 aIsLargerSignificand = 0;
888 } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
889 aIsLargerSignificand = 1;
890 } else {
891 aIsLargerSignificand = (av < bv) ? 1 : 0;
892 }
893
894 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
895 aIsLargerSignificand)) {
896 return float64_maybe_silence_nan(b, status);
897 } else {
898 return float64_maybe_silence_nan(a, status);
899 }
900}
901
902#ifdef NO_SIGNALING_NANS
903int floatx80_is_quiet_nan(floatx80 a_, float_status *status)
904{
905 return floatx80_is_any_nan(a_);
906}
907
908int floatx80_is_signaling_nan(floatx80 a_, float_status *status)
909{
910 return 0;
911}
912#else
913/*----------------------------------------------------------------------------
914| Returns 1 if the extended double-precision floating-point value `a' is a
915| quiet NaN; otherwise returns 0. This slightly differs from the same
916| function for other types as floatx80 has an explicit bit.
917*----------------------------------------------------------------------------*/
918
919int floatx80_is_quiet_nan(floatx80 a, float_status *status)
920{
921 if (status->snan_bit_is_one) {
922 uint64_t aLow;
923
924 aLow = a.low & ~0x4000000000000000ULL;
925 return ((a.high & 0x7FFF) == 0x7FFF)
926 && (aLow << 1)
927 && (a.low == aLow);
928 } else {
929 return ((a.high & 0x7FFF) == 0x7FFF)
930 && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
931 }
932}
933
934/*----------------------------------------------------------------------------
935| Returns 1 if the extended double-precision floating-point value `a' is a
936| signaling NaN; otherwise returns 0. This slightly differs from the same
937| function for other types as floatx80 has an explicit bit.
938*----------------------------------------------------------------------------*/
939
940int floatx80_is_signaling_nan(floatx80 a, float_status *status)
941{
942 if (status->snan_bit_is_one) {
943 return ((a.high & 0x7FFF) == 0x7FFF)
944 && ((a.low << 1) >= 0x8000000000000000ULL);
945 } else {
946 uint64_t aLow;
947
948 aLow = a.low & ~LIT64(0x4000000000000000);
949 return ((a.high & 0x7FFF) == 0x7FFF)
950 && (uint64_t)(aLow << 1)
951 && (a.low == aLow);
952 }
953}
954#endif
955
956/*----------------------------------------------------------------------------
957| Returns a quiet NaN if the extended double-precision floating point value
958| `a' is a signaling NaN; otherwise returns `a'.
959*----------------------------------------------------------------------------*/
960
961floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status)
962{
963 if (floatx80_is_signaling_nan(a, status)) {
964 if (status->snan_bit_is_one) {
965 a = floatx80_default_nan(status);
966 } else {
967 a.low |= LIT64(0xC000000000000000);
968 return a;
969 }
970 }
971 return a;
972}
973
974/*----------------------------------------------------------------------------
975| Returns the result of converting the extended double-precision floating-
976| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
977| invalid exception is raised.
978*----------------------------------------------------------------------------*/
979
980static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
981{
982 floatx80 dflt;
983 commonNaNT z;
984
985 if (floatx80_is_signaling_nan(a, status)) {
986 float_raise(float_flag_invalid, status);
987 }
988 if (a.low >> 63) {
989 z.sign = a.high >> 15;
990 z.low = 0;
991 z.high = a.low << 1;
992 } else {
993 dflt = floatx80_default_nan(status);
994 z.sign = dflt.high >> 15;
995 z.low = 0;
996 z.high = dflt.low << 1;
997 }
998 return z;
999}
1000
1001/*----------------------------------------------------------------------------
1002| Returns the result of converting the canonical NaN `a' to the extended
1003| double-precision floating-point format.
1004*----------------------------------------------------------------------------*/
1005
1006static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
1007{
1008 floatx80 z;
1009
1010 if (status->default_nan_mode) {
1011 return floatx80_default_nan(status);
1012 }
1013
1014 if (a.high >> 1) {
1015 z.low = LIT64(0x8000000000000000) | a.high >> 1;
1016 z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
1017 } else {
1018 z = floatx80_default_nan(status);
1019 }
1020 return z;
1021}
1022
1023/*----------------------------------------------------------------------------
1024| Takes two extended double-precision floating-point values `a' and `b', one
1025| of which is a NaN, and returns the appropriate NaN result. If either `a' or
1026| `b' is a signaling NaN, the invalid exception is raised.
1027*----------------------------------------------------------------------------*/
1028
1029floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
1030{
1031 flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1032 flag aIsLargerSignificand;
1033
1034 aIsQuietNaN = floatx80_is_quiet_nan(a, status);
1035 aIsSignalingNaN = floatx80_is_signaling_nan(a, status);
1036 bIsQuietNaN = floatx80_is_quiet_nan(b, status);
1037 bIsSignalingNaN = floatx80_is_signaling_nan(b, status);
1038
1039 if (aIsSignalingNaN | bIsSignalingNaN) {
1040 float_raise(float_flag_invalid, status);
1041 }
1042
1043 if (status->default_nan_mode) {
1044 return floatx80_default_nan(status);
1045 }
1046
1047 if (a.low < b.low) {
1048 aIsLargerSignificand = 0;
1049 } else if (b.low < a.low) {
1050 aIsLargerSignificand = 1;
1051 } else {
1052 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1053 }
1054
1055 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1056 aIsLargerSignificand)) {
1057 return floatx80_maybe_silence_nan(b, status);
1058 } else {
1059 return floatx80_maybe_silence_nan(a, status);
1060 }
1061}
1062
1063#ifdef NO_SIGNALING_NANS
1064int float128_is_quiet_nan(float128 a_, float_status *status)
1065{
1066 return float128_is_any_nan(a_);
1067}
1068
1069int float128_is_signaling_nan(float128 a_, float_status *status)
1070{
1071 return 0;
1072}
1073#else
1074/*----------------------------------------------------------------------------
1075| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1076| NaN; otherwise returns 0.
1077*----------------------------------------------------------------------------*/
1078
1079int float128_is_quiet_nan(float128 a, float_status *status)
1080{
1081 if (status->snan_bit_is_one) {
1082 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1083 && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1084 } else {
1085 return ((a.high << 1) >= 0xFFFF000000000000ULL)
1086 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1087 }
1088}
1089
1090/*----------------------------------------------------------------------------
1091| Returns 1 if the quadruple-precision floating-point value `a' is a
1092| signaling NaN; otherwise returns 0.
1093*----------------------------------------------------------------------------*/
1094
1095int float128_is_signaling_nan(float128 a, float_status *status)
1096{
1097 if (status->snan_bit_is_one) {
1098 return ((a.high << 1) >= 0xFFFF000000000000ULL)
1099 && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1100 } else {
1101 return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1102 && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF)));
1103 }
1104}
1105#endif
1106
1107/*----------------------------------------------------------------------------
1108| Returns a quiet NaN if the quadruple-precision floating point value `a' is
1109| a signaling NaN; otherwise returns `a'.
1110*----------------------------------------------------------------------------*/
1111
1112float128 float128_maybe_silence_nan(float128 a, float_status *status)
1113{
1114 if (float128_is_signaling_nan(a, status)) {
1115 if (status->snan_bit_is_one) {
1116 a = float128_default_nan(status);
1117 } else {
1118 a.high |= LIT64(0x0000800000000000);
1119 return a;
1120 }
1121 }
1122 return a;
1123}
1124
1125/*----------------------------------------------------------------------------
1126| Returns the result of converting the quadruple-precision floating-point NaN
1127| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
1128| exception is raised.
1129*----------------------------------------------------------------------------*/
1130
1131static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1132{
1133 commonNaNT z;
1134
1135 if (float128_is_signaling_nan(a, status)) {
1136 float_raise(float_flag_invalid, status);
1137 }
1138 z.sign = a.high >> 63;
1139 shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1140 return z;
1141}
1142
1143/*----------------------------------------------------------------------------
1144| Returns the result of converting the canonical NaN `a' to the quadruple-
1145| precision floating-point format.
1146*----------------------------------------------------------------------------*/
1147
1148static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1149{
1150 float128 z;
1151
1152 if (status->default_nan_mode) {
1153 return float128_default_nan(status);
1154 }
1155
1156 shift128Right(a.high, a.low, 16, &z.high, &z.low);
1157 z.high |= (((uint64_t)a.sign) << 63) | LIT64(0x7FFF000000000000);
1158 return z;
1159}
1160
1161/*----------------------------------------------------------------------------
1162| Takes two quadruple-precision floating-point values `a' and `b', one of
1163| which is a NaN, and returns the appropriate NaN result. If either `a' or
1164| `b' is a signaling NaN, the invalid exception is raised.
1165*----------------------------------------------------------------------------*/
1166
1167static float128 propagateFloat128NaN(float128 a, float128 b,
1168 float_status *status)
1169{
1170 flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1171 flag aIsLargerSignificand;
1172
1173 aIsQuietNaN = float128_is_quiet_nan(a, status);
1174 aIsSignalingNaN = float128_is_signaling_nan(a, status);
1175 bIsQuietNaN = float128_is_quiet_nan(b, status);
1176 bIsSignalingNaN = float128_is_signaling_nan(b, status);
1177
1178 if (aIsSignalingNaN | bIsSignalingNaN) {
1179 float_raise(float_flag_invalid, status);
1180 }
1181
1182 if (status->default_nan_mode) {
1183 return float128_default_nan(status);
1184 }
1185
1186 if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1187 aIsLargerSignificand = 0;
1188 } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1189 aIsLargerSignificand = 1;
1190 } else {
1191 aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1192 }
1193
1194 if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1195 aIsLargerSignificand)) {
1196 return float128_maybe_silence_nan(b, status);
1197 } else {
1198 return float128_maybe_silence_nan(a, status);
1199 }
1200}